coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
me_status.c File Reference
#include <console/console.h>
#include "me.h"
Include dependency graph for me_status.c:

Go to the source code of this file.

Functions

void intel_me_status (union me_hfs *hfs, union me_gmes *gmes)
 

Variables

static const char * me_cws_values []
 
static const char * me_opstate_values []
 
static const char * me_opmode_values []
 
static const char * me_error_values []
 
static const char * me_progress_values []
 
static const char * me_pmevent_values []
 
static const char * me_progress_rom_values []
 
static const char * me_progress_bup_values []
 
static const char * me_progress_policy_values []
 

Function Documentation

◆ intel_me_status()

Variable Documentation

◆ me_cws_values

const char* me_cws_values[]
static
Initial value:
= {
[ME_HFS_CWS_RESET] = "Reset",
[ME_HFS_CWS_INIT] = "Initializing",
[ME_HFS_CWS_REC] = "Recovery",
[ME_HFS_CWS_NORMAL] = "Normal",
[ME_HFS_CWS_WAIT] = "Platform Disable Wait",
[ME_HFS_CWS_TRANS] = "OP State Transition",
[ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In"
}
#define ME_HFS_CWS_REC
Definition: me.h:21
#define ME_HFS_CWS_RESET
Definition: me.h:19
#define ME_HFS_CWS_NORMAL
Definition: me.h:22
#define ME_HFS_CWS_INIT
Definition: me.h:20
#define ME_HFS_CWS_WAIT
Definition: me.h:23
#define ME_HFS_CWS_TRANS
Definition: me.h:24
#define ME_HFS_CWS_INVALID
Definition: me.h:25

Definition at line 7 of file me_status.c.

Referenced by intel_me_status().

◆ me_error_values

const char* me_error_values[]
static
Initial value:
= {
[ME_HFS_ERROR_NONE] = "No Error",
[ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",
[ME_HFS_ERROR_IMAGE] = "Image Failure",
[ME_HFS_ERROR_DEBUG] = "Debug Failure"
}
#define ME_HFS_ERROR_IMAGE
Definition: me.h:34
#define ME_HFS_ERROR_UNCAT
Definition: me.h:33
#define ME_HFS_ERROR_DEBUG
Definition: me.h:35
#define ME_HFS_ERROR_NONE
Definition: me.h:32

Definition at line 37 of file me_status.c.

Referenced by intel_me_status().

◆ me_opmode_values

const char* me_opmode_values[]
static
Initial value:
= {
[ME_HFS_MODE_NORMAL] = "Normal",
[ME_HFS_MODE_DEBUG] = "Debug or Disabled by AltDisableBit",
[ME_HFS_MODE_DIS] = "Soft Temporary Disable",
[ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
[ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"
}
#define ME_HFS_MODE_NORMAL
Definition: me.h:36
#define ME_HFS_MODE_DIS
Definition: me.h:38
#define ME_HFS_MODE_OVER_MEI
Definition: me.h:40
#define ME_HFS_MODE_OVER_JMPR
Definition: me.h:39
#define ME_HFS_MODE_DEBUG
Definition: me.h:37

Definition at line 28 of file me_status.c.

Referenced by intel_me_status().

◆ me_opstate_values

const char* me_opstate_values[]
static
Initial value:
= {
[ME_HFS_STATE_PREBOOT] = "Preboot",
[ME_HFS_STATE_M0_UMA] = "M0 with UMA",
[ME_HFS_STATE_M3] = "M3 without UMA",
[ME_HFS_STATE_M0] = "M0 without UMA",
[ME_HFS_STATE_BRINGUP] = "Bring up",
[ME_HFS_STATE_ERROR] = "M0 without UMA but with error"
}
#define ME_HFS_STATE_M0
Definition: me.h:29
#define ME_HFS_STATE_M0_UMA
Definition: me.h:27
#define ME_HFS_STATE_PREBOOT
Definition: me.h:26
#define ME_HFS_STATE_M3
Definition: me.h:28
#define ME_HFS_STATE_BRINGUP
Definition: me.h:30
#define ME_HFS_STATE_ERROR
Definition: me.h:31

Definition at line 18 of file me_status.c.

Referenced by intel_me_status().

◆ me_pmevent_values

const char* me_pmevent_values[]
static
Initial value:
= {
[0x00] = "Clean Moff->Mx wake",
[0x01] = "Moff->Mx wake after an error",
[0x02] = "Clean global reset",
[0x03] = "Global reset after an error",
[0x04] = "Clean Intel ME reset",
[0x05] = "Intel ME reset due to exception",
[0x06] = "Pseudo-global reset",
[0x07] = "S0/M0->Sx/M3",
[0x08] = "Sx/M3->S0/M0",
[0x09] = "Non-power cycle reset",
[0x0a] = "Power cycle reset through M3",
[0x0b] = "Power cycle reset through Moff",
[0x0c] = "Sx/Mx->Sx/Moff"
}

Definition at line 56 of file me_status.c.

Referenced by intel_me_status().

◆ me_progress_bup_values

const char* me_progress_bup_values[]
static
Initial value:
= {
[0x00] = "Initialization starts",
[0x01] = "Disable the host wake event",
[0x04] = "Flow determination start process",
[0x08] = "Error reading/matching the VSCC table in the descriptor",
[0x0a] = "Check to see if straps say ME DISABLED",
[0x0b] = "Timeout waiting for PWROK",
[0x0d] = "Possibly handle BUP manufacturing override strap",
[0x11] = "Bringup in M3",
[0x12] = "Bringup in M0",
[0x13] = "Flow detection error",
[0x15] = "M3 clock switching error",
[0x18] = "M3 kernel load",
[0x1c] = "T34 missing - cannot program ICC",
[0x1f] = "Waiting for DID BIOS message",
[0x20] = "Waiting for DID BIOS message failure",
[0x21] = "DID reported an error",
[0x22] = "Enabling UMA",
[0x23] = "Enabling UMA error",
[0x24] = "Sending DID Ack to BIOS",
[0x25] = "Sending DID Ack to BIOS error",
[0x26] = "Switching clocks in M0",
[0x27] = "Switching clocks in M0 error",
[0x28] = "ME in temp disable",
[0x32] = "M0 kernel load",
}

Definition at line 79 of file me_status.c.

Referenced by intel_me_status().

◆ me_progress_policy_values

const char* me_progress_policy_values[]
static
Initial value:
= {
[0x00] = "Entry into Policy Module",
[0x03] = "Received S3 entry",
[0x04] = "Received S4 entry",
[0x05] = "Received S5 entry",
[0x06] = "Received UPD entry",
[0x07] = "Received PCR entry",
[0x08] = "Received NPCR entry",
[0x09] = "Received host wake",
[0x0a] = "Received AC<>DC switch",
[0x0b] = "Received DRAM Init Done",
[0x0c] = "VSCC Data not found for flash device",
[0x0d] = "VSCC Table is not valid",
[0x0e] = "Flash Partition Boundary is outside address space",
[0x0f] = "ME cannot access the chipset descriptor region",
[0x10] = "Required VSCC values for flash parts do not match",
}

Definition at line 107 of file me_status.c.

Referenced by intel_me_status().

◆ me_progress_rom_values

const char* me_progress_rom_values[]
static
Initial value:
= {
[0x00] = "BEGIN",
[0x06] = "DISABLE"
}

Definition at line 73 of file me_status.c.

Referenced by intel_me_status().

◆ me_progress_values

const char* me_progress_values[]
static
Initial value:
= {
[ME_GMES_PHASE_ROM] = "ROM Phase",
[ME_GMES_PHASE_BUP] = "BUP Phase",
[ME_GMES_PHASE_UKERNEL] = "uKernel Phase",
[ME_GMES_PHASE_POLICY] = "Policy Module",
[ME_GMES_PHASE_MODULE] = "Module Loading",
[ME_GMES_PHASE_UNKNOWN] = "Unknown",
[ME_GMES_PHASE_HOST] = "Host Communication"
}
#define ME_GMES_PHASE_BUP
Definition: me.h:103
#define ME_GMES_PHASE_POLICY
Definition: me.h:105
#define ME_GMES_PHASE_UNKNOWN
Definition: me.h:107
#define ME_GMES_PHASE_HOST
Definition: me.h:108
#define ME_GMES_PHASE_UKERNEL
Definition: me.h:104
#define ME_GMES_PHASE_MODULE
Definition: me.h:106
#define ME_GMES_PHASE_ROM
Definition: me.h:102

Definition at line 45 of file me_status.c.

Referenced by intel_me_status().