57 [0x00] =
"Clean Moff->Mx wake",
58 [0x01] =
"Moff->Mx wake after an error",
59 [0x02] =
"Clean global reset",
60 [0x03] =
"Global reset after an error",
61 [0x04] =
"Clean Intel ME reset",
62 [0x05] =
"Intel ME reset due to exception",
63 [0x06] =
"Pseudo-global reset",
64 [0x07] =
"S0/M0->Sx/M3",
65 [0x08] =
"Sx/M3->S0/M0",
66 [0x09] =
"Non-power cycle reset",
67 [0x0a] =
"Power cycle reset through M3",
68 [0x0b] =
"Power cycle reset through Moff",
69 [0x0c] =
"Sx/Mx->Sx/Moff"
80 [0x00] =
"Initialization starts",
81 [0x01] =
"Disable the host wake event",
82 [0x04] =
"Flow determination start process",
83 [0x08] =
"Error reading/matching the VSCC table in the descriptor",
84 [0x0a] =
"Check to see if straps say ME DISABLED",
85 [0x0b] =
"Timeout waiting for PWROK",
86 [0x0d] =
"Possibly handle BUP manufacturing override strap",
87 [0x11] =
"Bringup in M3",
88 [0x12] =
"Bringup in M0",
89 [0x13] =
"Flow detection error",
90 [0x15] =
"M3 clock switching error",
91 [0x18] =
"M3 kernel load",
92 [0x1c] =
"T34 missing - cannot program ICC",
93 [0x1f] =
"Waiting for DID BIOS message",
94 [0x20] =
"Waiting for DID BIOS message failure",
95 [0x21] =
"DID reported an error",
96 [0x22] =
"Enabling UMA",
97 [0x23] =
"Enabling UMA error",
98 [0x24] =
"Sending DID Ack to BIOS",
99 [0x25] =
"Sending DID Ack to BIOS error",
100 [0x26] =
"Switching clocks in M0",
101 [0x27] =
"Switching clocks in M0 error",
102 [0x28] =
"ME in temp disable",
103 [0x32] =
"M0 kernel load",
108 [0x00] =
"Entry into Policy Module",
109 [0x03] =
"Received S3 entry",
110 [0x04] =
"Received S4 entry",
111 [0x05] =
"Received S5 entry",
112 [0x06] =
"Received UPD entry",
113 [0x07] =
"Received PCR entry",
114 [0x08] =
"Received NPCR entry",
115 [0x09] =
"Received host wake",
116 [0x0a] =
"Received AC<>DC switch",
117 [0x0b] =
"Received DRAM Init Done",
118 [0x0c] =
"VSCC Data not found for flash device",
119 [0x0d] =
"VSCC Table is not valid",
120 [0x0e] =
"Flash Partition Boundary is outside address space",
121 [0x0f] =
"ME cannot access the chipset descriptor region",
122 [0x10] =
"Required VSCC values for flash parts do not match",
127 if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL <
BIOS_DEBUG)
#define printk(level,...)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define ME_HFS_ERROR_IMAGE
#define ME_HFS_ERROR_UNCAT
#define ME_HFS_MODE_NORMAL
#define ME_HFS_ERROR_DEBUG
#define ME_HFS_STATE_M0_UMA
#define ME_HFS_MODE_OVER_MEI
#define ME_HFS_CWS_NORMAL
#define ME_HFS_STATE_PREBOOT
#define ME_HFS_MODE_OVER_JMPR
#define ME_HFS_STATE_BRINGUP
#define ME_HFS_MODE_DEBUG
#define ME_HFS_CWS_INVALID
#define ME_HFS_ERROR_NONE
#define ME_HFS_STATE_ERROR
void intel_me_status(void)
#define ME_GMES_PHASE_BUP
#define ME_GMES_PHASE_POLICY
#define ME_GMES_PHASE_UNKNOWN
#define ME_GMES_PHASE_HOST
#define ME_GMES_PHASE_UKERNEL
#define ME_GMES_PHASE_MODULE
#define ME_GMES_PHASE_ROM
static const char * me_progress_bup_values[]
static const char * me_opstate_values[]
static const char * me_cws_values[]
static const char * me_pmevent_values[]
static const char * me_progress_rom_values[]
static const char * me_progress_values[]
static const char * me_error_values[]
static const char * me_progress_policy_values[]
static const char * me_opmode_values[]