37 #define ADC_POWER_CTRL (1 << 3)
38 #define START_MODE (1 << 4)
41 #define INTER_PD_SHIFT 6
42 #define INTER_PD_MASK 0x3f
45 #define LAST_TSHUT (1 << 24)
46 #define SRC3_EN (1 << 7)
47 #define SRC2_EN (1 << 6)
48 #define SRC1_EN (1 << 5)
49 #define SRC0_EN (1 << 4)
50 #define Q_SEL (1 << 1)
51 #define AUTO_EN (1 << 0)
54 #define TSHUT_CRU_EN_SRC3 (1 << 11)
55 #define TSHUT_CRU_EN_SRC2 (1 << 10)
56 #define TSHUT_CRU_EN_SRC1 (1 << 9)
57 #define TSHUT_CRU_EN_SRC0 (1 << 8)
58 #define TSHUT_GPIO_EN_SRC3 (1 << 7)
59 #define TSHUT_GPIO_EN_SRC2 (1 << 6)
60 #define TSHUT_GPIO_EN_SRC1 (1 << 5)
61 #define TSHUT_GPIO_EN_SRC0 (1 << 4)
63 #define AUTO_PERIOD 187500
64 #define AUTO_DEBOUNCE 4
65 #define AUTO_PERIOD_HT 37500
66 #define AUTO_DEBOUNCE_HT 4
67 #define TSADC_CLOCK_HZ (750 * KHz)
76 #define TSADC_SHUT_VALUE 677
78 #define GRF_TSADC_TSEN_PD0_ON RK_SETBITS(0)
79 #define GRF_TSADC_TSEN_PD0_OFF RK_CLRBITS(0)
80 #define GRF_SARADC_TSEN_ON RK_SETBITS(0)
static void write32(void *addr, uint32_t val)
#define setbits32(addr, set)
#define clrbits32(addr, clear)
check_member(rk3288_tsadc_regs, auto_period_ht, 0x6c)
static struct rk3399_pmugrf_regs *const rk3399_pmugrf
static struct rk3399_grf_regs *const rk3399_grf
#define TSHUT_CRU_EN_SRC0
#define TSHUT_GPIO_EN_SRC0
#define GRF_SARADC_TSEN_ON
#define GRF_TSADC_TSEN_PD0_ON
#define GRF_TSADC_TSEN_PD0_OFF
struct rk3399_tsadc_regs * rk3399_tsadc
void rkclk_configure_tsadc(unsigned int hz)
u32 reserved0[(0x20 - 0x10)/4]
u32 reserved1[(0x60 - 0x50)/4]