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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
| struct | video_info |
| struct | link_train |
| struct | s5p_dp_device |
Macros | |
| #define | STREAM_ON_TIMEOUT 100 |
| #define | PLL_LOCK_TIMEOUT 10 |
| #define | DP_INIT_TRIES 10 |
| #define | MAX_CR_LOOP 5 |
| #define | MAX_EQ_LOOP 4 |
Enumerations | |
| enum | link_rate { LINK_RATE_1_62GBPS = 0x06 , LINK_RATE_2_70GBPS = 0x0a } |
| enum | link_lane_count { LANE_COUNT1 = 1 , LANE_COUNT2 = 2 , LANE_COUNT4 = 4 } |
| enum | pre_emphasis_level { PRE_EMPHASIS_LEVEL_0 , PRE_EMPHASIS_LEVEL_1 , PRE_EMPHASIS_LEVEL_2 , PRE_EMPHASIS_LEVEL_3 , PRE_EMPHASIS_LEVEL_0 , PRE_EMPHASIS_LEVEL_1 , PRE_EMPHASIS_LEVEL_2 , PRE_EMPHASIS_LEVEL_3 } |
| enum | color_space { CS_RGB , CS_YCBCR422 , CS_YCBCR444 , COLOR_RGB , COLOR_YCBCR422 , COLOR_YCBCR444 } |
| enum | color_depth { COLOR_6 , COLOR_8 , COLOR_10 , COLOR_12 , COLOR_6 , COLOR_8 , COLOR_10 , COLOR_12 } |
| enum | color_coefficient { COLOR_YCBCR601 , COLOR_YCBCR709 , COLOR_YCBCR601 , COLOR_YCBCR709 } |
| enum | dynamic_range { VESA , CEA , VESA , CEA } |
| enum | pll_status { DP_PLL_UNLOCKED , DP_PLL_LOCKED , PLL_UNLOCKED , PLL_LOCKED , PLL_UNLOCKED = 0 , PLL_LOCKED } |
| enum | clock_recovery_m_value_type { CALCULATED_M , REGISTER_M , CALCULATED_M , REGISTER_M } |
| enum color_coefficient |
| enum color_depth |
| enum color_space |
| enum dynamic_range |
| enum link_lane_count |
| enum link_rate |
| enum pll_status |
| enum pre_emphasis_level |
| int dp_controller_init | ( | struct s5p_dp_device * | dp_device | ) |
Definition at line 475 of file fb.c.
References base, s5p_dp_device::base, BIOS_ERR, clock_init_dp_clock(), ENHANCED, link_train::lane_count, video_info::lane_count, link_train::link_rate, video_info::link_rate, s5p_dp_device::link_train, power_enable_dp_phy(), printk, s5p_dp_config_video(), s5p_dp_enable_rx_to_enhanced_mode(), s5p_dp_enable_scramble(), s5p_dp_hw_link_training(), s5p_dp_init_dp(), s5p_dp_init_video(), setbits32, udelay(), s5p_dp_device::video_info, and write32().
Referenced by mainboard_init().
| void fb_init | ( | unsigned long int | fb_size, |
| void * | lcdbase, | ||
| struct exynos5_fimd_panel * | pd | ||
| ) |
Definition at line 98 of file fb.c.
References ALIGN, BPPMODE_F_OFFSET, BPPMODE_F_RGB_16BIT_565, CHANNEL0_EN, exynos5_fimd_panel::clkval_f, CLKVAL_F_OFFSET, exynos5_fimd::dpclkcon, ENVID_F_ON, ENVID_ON, ENWIN_F_ENABLE, exynos_disp_ctrl, exynos_fimd, exynos5_fimd_panel::fixvclk, H_BACK_PORCH_OFFSET, H_FRONT_PORCH_OFFSET, HALF_WORD_SWAP_EN, HOZVAL_OFFSET, exynos5_fimd_panel::hsync, HSYNC_PULSE_WIDTH_OFFSET, exynos5_fimd_panel::ivclk, exynos5_fimd_panel::left_margin, LINEVAL_OFFSET, exynos5_fimd_panel::lower_margin, OSD_RIGHTBOTX_F_OFFSET, OSD_RIGHTBOTY_F_OFFSET, exynos5_fimd_panel::right_margin, setbits32, exynos5_fimd::shadowcon, exynos5_fimd_panel::upper_margin, V_BACK_PORCH_OFFSET, V_FRONT_PORCH_OFFSET, val, exynos5_fimd::vidcon0, exynos5_disp_ctrl::vidcon1, exynos5_fimd::vidosd0b, exynos5_fimd::vidosd0c, exynos5_disp_ctrl::vidtcon0, exynos5_disp_ctrl::vidtcon1, exynos5_disp_ctrl::vidtcon2, exynos5_fimd::vidw00add0b0, exynos5_fimd::vidw00add1b0, exynos5_fimd::vidw00add2, exynos5_fimd_panel::vsync, VSYNC_PULSE_WIDTH_OFFSET, exynos5_fimd::wincon0, write32(), exynos5_fimd_panel::xres, and exynos5_fimd_panel::yres.
Referenced by lcd_ctrl_init().
| int lcd_ctrl_init | ( | unsigned long int | fb_size, |
| struct exynos5_fimd_panel * | panel_data, | ||
| void * | lcdbase | ||
| ) |
Init the LCD controller.
| panel_data | |
| lcdbase | Base address of LCD frame buffer |
Definition at line 535 of file fb.c.
References fb_init(), and fimd_bypass().
Referenced by exynos_displayport_init().
| void s5p_dp_config_video_slave_mode | ( | struct s5p_dp_device * | dp, |
| struct video_info * | video_info | ||
| ) |
Definition at line 442 of file dp-reg.c.
References AUDIO_MODE_SPDIF_MODE, base, s5p_dp_device::base, video_info::h_sync_polarity, HSYNC_POLARITY_CFG, INTERACE_SCAN_CFG, video_info::interlaced, MASTER_VID_FUNC_EN_N, read32(), SLAVE_VID_FUNC_EN_N, video_info::v_sync_polarity, VIDEO_MODE_SLAVE_MODE, VSYNC_POLARITY_CFG, and write32().
Referenced by s5p_dp_config_video().
| void s5p_dp_enable_video_master | ( | struct s5p_dp_device * | dp | ) |
Definition at line 404 of file dp-reg.c.
References base, s5p_dp_device::base, read32(), VIDEO_MODE_MASK, VIDEO_MODE_SLAVE_MODE, and write32().
Referenced by s5p_dp_config_video().
| unsigned int s5p_dp_get_pll_lock_status | ( | struct s5p_dp_device * | dp | ) |
Definition at line 92 of file dp-reg.c.
References s5p_dp_device::base, exynos5_dp::dp_debug_ctl, PLL_LOCK, PLL_LOCKED, PLL_UNLOCKED, and read32().
Referenced by s5p_dp_config_video(), s5p_dp_hw_link_training(), and s5p_dp_init_analog_func().
| int s5p_dp_init_analog_func | ( | struct s5p_dp_device * | dp | ) |
Definition at line 103 of file dp-reg.c.
References AUX_FUNC_EN_N, base, s5p_dp_device::base, BIOS_ERR, clrbits32, DP_PLL_PD, F_PLL_LOCK, LS_CLK_DOMAIN_FUNC_EN_N, PLL_LOCK_CHG, PLL_LOCK_CTRL, PLL_LOCK_TIMEOUT, PLL_UNLOCKED, printk, s5p_dp_get_pll_lock_status(), SERDES_FIFO_FUNC_EN_N, stopwatch_expired(), stopwatch_init_msecs_expire(), and write32().
Referenced by s5p_dp_init_dp().
| void s5p_dp_init_aux | ( | struct s5p_dp_device * | dp | ) |
Definition at line 138 of file dp-reg.c.
References AUX_BIT_PERIOD_MASK, AUX_BIT_PERIOD_SHIFT, AUX_ERR, AUX_FUNC_EN_N, AUX_HW_RETRY_COUNT_MASK, AUX_HW_RETRY_COUNT_SHIFT, AUX_HW_RETRY_INTERVAL_600_US, AUX_HW_RETRY_INTERVAL_SHIFT, base, s5p_dp_device::base, clrbits32, DEFER_COUNT_MASK, DEFER_COUNT_SHIFT, DEFER_CTRL_EN, RPLY_RECEIV, setbits32, and write32().
Referenced by s5p_dp_init_dp().
| void s5p_dp_init_video | ( | struct s5p_dp_device * | dp | ) |
Definition at line 297 of file dp-reg.c.
References base, s5p_dp_device::base, CHA_CRI_MASK, CHA_CRI_SHIFT, CHA_CTRL, VID_CLK_CHG, VID_FORMAT_CHG, VSYNC_DET, and write32().
Referenced by dp_controller_init().
| int s5p_dp_is_slave_video_stream_clock_on | ( | struct s5p_dp_device * | dp | ) |
Definition at line 341 of file dp-reg.c.
References base, s5p_dp_device::base, BIOS_DEBUG, CHA_STA, DET_STA, printk, read32(), and write32().
Referenced by s5p_dp_config_video().
| int s5p_dp_is_video_stream_on | ( | struct s5p_dp_device * | dp | ) |
Definition at line 415 of file dp-reg.c.
References base, s5p_dp_device::base, BIOS_DEBUG, printk, read32(), stopwatch_expired(), stopwatch_init_msecs_expire(), STREAM_ON_TIMEOUT, VSYNC_DET, and write32().
Referenced by s5p_dp_config_video().
| int s5p_dp_read_byte_from_dpcd | ( | struct s5p_dp_device * | dp, |
| unsigned int | reg_addr, | ||
| unsigned char * | data | ||
| ) |
Definition at line 248 of file dp-reg.c.
References AUX_ADDR_15_8_MASK, AUX_ADDR_15_8_SHIFT, AUX_ADDR_19_16_MASK, AUX_ADDR_19_16_SHIFT, AUX_ADDR_7_0_MASK, AUX_ADDR_7_0_SHIFT, AUX_TX_COMM_DP_TRANSACTION, AUX_TX_COMM_READ, base, s5p_dp_device::base, BIOS_DEBUG, BUF_CLR, MAX_AUX_RETRY_COUNT, printk, read32(), s5p_dp_start_aux_transaction(), and write32().
Referenced by s5p_dp_enable_rx_to_enhanced_mode(), s5p_dp_enable_scramble(), s5p_dp_get_max_rx_bandwidth(), and s5p_dp_get_max_rx_lane_count().
| void s5p_dp_reset | ( | struct s5p_dp_device * | dp | ) |
Definition at line 16 of file dp-reg.c.
References AUD_FIFO_FUNC_EN_N, AUD_FUNC_EN_N, AUX_FUNC_EN_N, base, s5p_dp_device::base, clrbits32, HDCP_FUNC_EN_N, HDCP_VIDEO_MUTE, INT_POL0, INT_POL1, LANE0_MAP_LOGIC_LANE_0, LANE1_MAP_LOGIC_LANE_1, LANE2_MAP_LOGIC_LANE_2, LANE3_MAP_LOGIC_LANE_3, LS_CLK_DOMAIN_FUNC_EN_N, MASTER_VID_FUNC_EN_N, RESET_DP_TX, SERDES_FIFO_FUNC_EN_N, SLAVE_VID_FUNC_EN_N, SSC_FUNC_EN_N, SW_FUNC_EN_N, udelay(), VIDEO_EN, and write32().
Referenced by s5p_dp_init_dp().
| void s5p_dp_set_video_color_format | ( | struct s5p_dp_device * | dp, |
| unsigned int | color_depth, | ||
| unsigned int | color_space, | ||
| unsigned int | dynamic_range, | ||
| unsigned int | coeff | ||
| ) |
Definition at line 316 of file dp-reg.c.
References base, s5p_dp_device::base, IN_BPC_SHIFT, IN_COLOR_F_SHIFT, IN_D_RANGE_SHIFT, IN_YC_COEFFI_ITU601, IN_YC_COEFFI_ITU709, IN_YC_COEFFI_MASK, read32(), and write32().
Referenced by s5p_dp_config_video().
| void s5p_dp_set_video_cr_mn | ( | struct s5p_dp_device * | dp, |
| enum clock_recovery_m_value_type | type, | ||
| unsigned int | m_value, | ||
| unsigned int | n_value | ||
| ) |
Definition at line 367 of file dp-reg.c.
References base, s5p_dp_device::base, clrbits32, FIX_M_VID, M_VID_0_VALUE_SHIFT, M_VID_1_VALUE_SHIFT, M_VID_2_VALUE_SHIFT, N_VID_0_VALUE_SHIFT, N_VID_1_VALUE_SHIFT, N_VID_2_VALUE_SHIFT, REGISTER_M, setbits32, type, and write32().
Referenced by s5p_dp_config_video().
| int s5p_dp_start_aux_transaction | ( | struct s5p_dp_device * | dp | ) |
Definition at line 165 of file dp-reg.c.
References AUX_EN, AUX_ERR, AUX_STATUS_MASK, base, s5p_dp_device::base, BIOS_ERR, printk, read32(), RPLY_RECEIV, setbits32, and write32().
Referenced by s5p_dp_read_byte_from_dpcd(), and s5p_dp_write_byte_to_dpcd().
| void s5p_dp_wait_hw_link_training_done | ( | struct s5p_dp_device * | dp | ) |
Definition at line 472 of file dp-reg.c.
References base, s5p_dp_device::base, HW_TRAINING_EN, and read32().
Referenced by s5p_dp_hw_link_training().
| int s5p_dp_write_byte_to_dpcd | ( | struct s5p_dp_device * | dp, |
| unsigned int | reg_addr, | ||
| unsigned char | data | ||
| ) |
Definition at line 201 of file dp-reg.c.
References AUX_ADDR_15_8_MASK, AUX_ADDR_15_8_SHIFT, AUX_ADDR_19_16_MASK, AUX_ADDR_19_16_SHIFT, AUX_ADDR_7_0_MASK, AUX_ADDR_7_0_SHIFT, AUX_TX_COMM_DP_TRANSACTION, AUX_TX_COMM_WRITE, base, s5p_dp_device::base, BIOS_DEBUG, BUF_CLR, MAX_AUX_RETRY_COUNT, printk, s5p_dp_start_aux_transaction(), and write32().
Referenced by s5p_dp_enable_rx_to_enhanced_mode(), s5p_dp_enable_scramble(), and s5p_dp_hw_link_training().
1.9.1