coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Data Structures | Macros | Enumerations | Functions | Variables
dp.h File Reference
#include <soc/cpu.h>
Include dependency graph for dp.h:

Go to the source code of this file.

Data Structures

struct  exynos_dp
 
struct  exynos_fb
 
struct  edp_disp_info
 
struct  edp_link_train_info
 
struct  edp_video_info
 
struct  edp_device_info
 
struct  exynos_dp_platform_data
 

Macros

#define VIDEO_EN_MASK   (0x01 << 7)
 
#define VIDEO_MUTE_MASK   (0x01 << 6)
 
#define VIDEO_BIST_MASK   (0x1 << 3)
 
#define SEL_BG_NEW_BANDGAP   (0x0 << 6)
 
#define SEL_BG_INTERNAL_RESISTOR   (0x1 << 6)
 
#define TX_TERMINAL_CTRL_73_OHM   (0x0 << 4)
 
#define TX_TERMINAL_CTRL_61_OHM   (0x1 << 4)
 
#define TX_TERMINAL_CTRL_50_OHM   (0x2 << 4)
 
#define TX_TERMINAL_CTRL_45_OHM   (0x3 << 4)
 
#define SWING_A_30PER_G_INCREASE   (0x1 << 3)
 
#define SWING_A_30PER_G_NORMAL   (0x0 << 3)
 
#define CPREG_BLEED   (0x1 << 4)
 
#define SEL_24M   (0x1 << 3)
 
#define TX_DVDD_BIT_1_0000V   (0x3 << 0)
 
#define TX_DVDD_BIT_1_0625V   (0x4 << 0)
 
#define TX_DVDD_BIT_1_1250V   (0x5 << 0)
 
#define DRIVE_DVDD_BIT_1_0000V   (0x3 << 5)
 
#define DRIVE_DVDD_BIT_1_0625V   (0x4 << 5)
 
#define DRIVE_DVDD_BIT_1_1250V   (0x5 << 5)
 
#define SEL_CURRENT_DEFAULT   (0x0 << 3)
 
#define VCO_BIT_000_MICRO   (0x0 << 0)
 
#define VCO_BIT_200_MICRO   (0x1 << 0)
 
#define VCO_BIT_300_MICRO   (0x2 << 0)
 
#define VCO_BIT_400_MICRO   (0x3 << 0)
 
#define VCO_BIT_500_MICRO   (0x4 << 0)
 
#define VCO_BIT_600_MICRO   (0x5 << 0)
 
#define VCO_BIT_700_MICRO   (0x6 << 0)
 
#define VCO_BIT_900_MICRO   (0x7 << 0)
 
#define PD_RING_OSC   (0x1 << 6)
 
#define AUX_TERMINAL_CTRL_52_OHM   (0x3 << 4)
 
#define AUX_TERMINAL_CTRL_69_OHM   (0x2 << 4)
 
#define AUX_TERMINAL_CTRL_102_OHM   (0x1 << 4)
 
#define AUX_TERMINAL_CTRL_200_OHM   (0x0 << 4)
 
#define TX_CUR1_1X   (0x0 << 2)
 
#define TX_CUR1_2X   (0x1 << 2)
 
#define TX_CUR1_3X   (0x2 << 2)
 
#define TX_CUR_1_MA   (0x0 << 0)
 
#define TX_CUR_2_MA   (0x1 << 0)
 
#define TX_CUR_3_MA   (0x2 << 0)
 
#define TX_CUR_4_MA   (0x3 << 0)
 
#define CH3_AMP_0_MV   (0x3 << 12)
 
#define CH2_AMP_0_MV   (0x3 << 8)
 
#define CH1_AMP_0_MV   (0x3 << 4)
 
#define CH0_AMP_0_MV   (0x3 << 0)
 
#define DP_PLL_PD   (0x1 << 7)
 
#define DP_PLL_RESET   (0x1 << 6)
 
#define DP_PLL_LOOP_BIT_DEFAULT   (0x1 << 4)
 
#define DP_PLL_REF_BIT_1_1250V   (0x5 << 0)
 
#define DP_PLL_REF_BIT_1_2500V   (0x7 << 0)
 
#define SOFT_INT_CTRL   (0x1 << 2)
 
#define INT_POL   (0x1 << 0)
 
#define RESET_DP_TX   (0x01 << 0)
 
#define MASTER_VID_FUNC_EN_N   (0x1 << 7)
 
#define SLAVE_VID_FUNC_EN_N   (0x1 << 5)
 
#define AUD_FIFO_FUNC_EN_N   (0x1 << 4)
 
#define AUD_FUNC_EN_N   (0x1 << 3)
 
#define HDCP_FUNC_EN_N   (0x1 << 2)
 
#define CRC_FUNC_EN_N   (0x1 << 1)
 
#define SW_FUNC_EN_N   (0x1 << 0)
 
#define SSC_FUNC_EN_N   (0x1 << 7)
 
#define AUX_FUNC_EN_N   (0x1 << 2)
 
#define SERDES_FIFO_FUNC_EN_N   (0x1 << 1)
 
#define LS_CLK_DOMAIN_FUNC_EN_N   (0x1 << 0)
 
#define PHY_PD   (0x1 << 5)
 
#define AUX_PD   (0x1 << 4)
 
#define CH3_PD   (0x1 << 3)
 
#define CH2_PD   (0x1 << 2)
 
#define CH1_PD   (0x1 << 1)
 
#define CH0_PD   (0x1 << 0)
 
#define VSYNC_DET   (0x1 << 7)
 
#define PLL_LOCK_CHG   (0x1 << 6)
 
#define SPDIF_ERR   (0x1 << 5)
 
#define SPDIF_UNSTBL   (0x1 << 4)
 
#define VID_FORMAT_CHG   (0x1 << 3)
 
#define AUD_CLK_CHG   (0x1 << 2)
 
#define VID_CLK_CHG   (0x1 << 1)
 
#define SW_INT   (0x1 << 0)
 
#define PLL_LOCK   (0x1 << 4)
 
#define F_PLL_LOCK   (0x1 << 3)
 
#define PLL_LOCK_CTRL   (0x1 << 2)
 
#define SSC_FUNC_EN_N   (0x1 << 7)
 
#define AUX_FUNC_EN_N   (0x1 << 2)
 
#define SERDES_FIFO_FUNC_EN_N   (0x1 << 1)
 
#define LS_CLK_DOMAIN_FUNC_EN_N   (0x1 << 0)
 
#define PSR_ACTIVE   (0x1 << 7)
 
#define PSR_INACTIVE   (0x1 << 6)
 
#define SPDIF_BI_PHASE_ERR   (0x1 << 5)
 
#define HOTPLUG_CHG   (0x1 << 2)
 
#define HPD_LOST   (0x1 << 1)
 
#define PLUG   (0x1 << 0)
 
#define INT_HPD   (0x1 << 6)
 
#define HW_TRAINING_FINISH   (0x1 << 5)
 
#define RPLY_RECEIV   (0x1 << 1)
 
#define AUX_ERR   (0x1 << 0)
 
#define HPD_STATUS   (0x1 << 6)
 
#define F_HPD   (0x1 << 5)
 
#define HPD_CTRL   (0x1 << 4)
 
#define HDCP_RDY   (0x1 << 3)
 
#define STRM_VALID   (0x1 << 2)
 
#define F_VALID   (0x1 << 1)
 
#define VALID_CTRL   (0x1 << 0)
 
#define AUX_BIT_PERIOD_EXPECTED_DELAY(x)   (((x) & 0x7) << 8)
 
#define AUX_HW_RETRY_INTERVAL_MASK   (0x3 << 3)
 
#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS   (0x0 << 3)
 
#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS   (0x1 << 3)
 
#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS   (0x2 << 3)
 
#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS   (0x3 << 3)
 
#define AUX_HW_RETRY_COUNT_SEL(x)   (((x) & 0x7) << 0)
 
#define DEFER_CTRL_EN   (0x1 << 7)
 
#define DEFER_COUNT(x)   (((x) & 0x7f) << 0)
 
#define COMMON_INT_MASK_1   (0)
 
#define COMMON_INT_MASK_2   (0)
 
#define COMMON_INT_MASK_3   (0)
 
#define COMMON_INT_MASK_4   (0)
 
#define INT_STA_MASK   (0)
 
#define BUF_CLR   (0x1 << 7)
 
#define BUF_DATA_COUNT(x)   (((x) & 0x1f) << 0)
 
#define AUX_ADDR_7_0(x)   (((x) >> 0) & 0xff)
 
#define AUX_ADDR_15_8(x)   (((x) >> 8) & 0xff)
 
#define AUX_ADDR_19_16(x)   (((x) >> 16) & 0x0f)
 
#define AUX_LENGTH(x)   (((x - 1) & 0xf) << 4)
 
#define AUX_TX_COMM_MASK   (0xf << 0)
 
#define AUX_TX_COMM_DP_TRANSACTION   (0x1 << 3)
 
#define AUX_TX_COMM_I2C_TRANSACTION   (0x0 << 3)
 
#define AUX_TX_COMM_MOT   (0x1 << 2)
 
#define AUX_TX_COMM_WRITE   (0x0 << 0)
 
#define AUX_TX_COMM_READ   (0x1 << 0)
 
#define ADDR_ONLY   (0x1 << 1)
 
#define AUX_EN   (0x1 << 0)
 
#define AUX_BUSY   (0x1 << 4)
 
#define AUX_STATUS_MASK   (0xf << 0)
 
#define AUX_RX_COMM_I2C_DEFER   (0x2 << 2)
 
#define AUX_RX_COMM_AUX_DEFER   (0x2 << 0)
 
#define MACRO_RST   (0x1 << 5)
 
#define CH1_TEST   (0x1 << 1)
 
#define CH0_TEST   (0x1 << 0)
 
#define SCRAMBLER_TYPE   (0x1 << 9)
 
#define HW_LINK_TRAINING_PATTERN   (0x1 << 8)
 
#define SCRAMBLING_DISABLE   (0x1 << 5)
 
#define SCRAMBLING_ENABLE   (0x0 << 5)
 
#define LINK_QUAL_PATTERN_SET_MASK   (0x3 << 2)
 
#define LINK_QUAL_PATTERN_SET_PRBS7   (0x3 << 2)
 
#define LINK_QUAL_PATTERN_SET_D10_2   (0x1 << 2)
 
#define LINK_QUAL_PATTERN_SET_DISABLE   (0x0 << 2)
 
#define SW_TRAINING_PATTERN_SET_MASK   (0x3 << 0)
 
#define SW_TRAINING_PATTERN_SET_PTN2   (0x2 << 0)
 
#define SW_TRAINING_PATTERN_SET_PTN1   (0x1 << 0)
 
#define SW_TRAINING_PATTERN_SET_NORMAL   (0x0 << 0)
 
#define TOTAL_LINE_CFG_L(x)   ((x) & 0xff)
 
#define TOTAL_LINE_CFG_H(x)   ((((x) >> 8)) & 0xff)
 
#define ACTIVE_LINE_CFG_L(x)   ((x) & 0xff)
 
#define ACTIVE_LINE_CFG_H(x)   (((x) >> 8) & 0xff)
 
#define TOTAL_PIXEL_CFG_L(x)   ((x) & 0xff)
 
#define TOTAL_PIXEL_CFG_H(x)   ((((x) >> 8)) & 0xff)
 
#define ACTIVE_PIXEL_CFG_L(x)   ((x) & 0xff)
 
#define ACTIVE_PIXEL_CFG_H(x)   ((((x) >> 8)) & 0xff)
 
#define H_F_PORCH_CFG_L(x)   ((x) & 0xff)
 
#define H_F_PORCH_CFG_H(x)   ((((x) >> 8)) & 0xff)
 
#define H_SYNC_PORCH_CFG_L(x)   ((x) & 0xff)
 
#define H_SYNC_PORCH_CFG_H(x)   ((((x) >> 8)) & 0xff)
 
#define H_B_PORCH_CFG_L(x)   ((x) & 0xff)
 
#define H_B_PORCH_CFG_H(x)   ((((x) >> 8)) & 0xff)
 
#define MAX_PRE_EMPHASIS_REACH_0   (0x1 << 5)
 
#define PRE_EMPHASIS_SET_0_SET(x)   (((x) & 0x3) << 3)
 
#define PRE_EMPHASIS_SET_0_GET(x)   (((x) >> 3) & 0x3)
 
#define PRE_EMPHASIS_SET_0_MASK   (0x3 << 3)
 
#define PRE_EMPHASIS_SET_0_SHIFT   (3)
 
#define PRE_EMPHASIS_SET_0_LEVEL_3   (0x3 << 3)
 
#define PRE_EMPHASIS_SET_0_LEVEL_2   (0x2 << 3)
 
#define PRE_EMPHASIS_SET_0_LEVEL_1   (0x1 << 3)
 
#define PRE_EMPHASIS_SET_0_LEVEL_0   (0x0 << 3)
 
#define MAX_DRIVE_CURRENT_REACH_0   (0x1 << 2)
 
#define DRIVE_CURRENT_SET_0_MASK   (0x3 << 0)
 
#define DRIVE_CURRENT_SET_0_SET(x)   (((x) & 0x3) << 0)
 
#define DRIVE_CURRENT_SET_0_GET(x)   (((x) >> 0) & 0x3)
 
#define DRIVE_CURRENT_SET_0_LEVEL_3   (0x3 << 0)
 
#define DRIVE_CURRENT_SET_0_LEVEL_2   (0x2 << 0)
 
#define DRIVE_CURRENT_SET_0_LEVEL_1   (0x1 << 0)
 
#define DRIVE_CURRENT_SET_0_LEVEL_0   (0x0 << 0)
 
#define MAX_PRE_EMPHASIS_REACH_1   (0x1 << 5)
 
#define PRE_EMPHASIS_SET_1_SET(x)   (((x) & 0x3) << 3)
 
#define PRE_EMPHASIS_SET_1_GET(x)   (((x) >> 3) & 0x3)
 
#define PRE_EMPHASIS_SET_1_MASK   (0x3 << 3)
 
#define PRE_EMPHASIS_SET_1_SHIFT   (3)
 
#define PRE_EMPHASIS_SET_1_LEVEL_3   (0x3 << 3)
 
#define PRE_EMPHASIS_SET_1_LEVEL_2   (0x2 << 3)
 
#define PRE_EMPHASIS_SET_1_LEVEL_1   (0x1 << 3)
 
#define PRE_EMPHASIS_SET_1_LEVEL_0   (0x0 << 3)
 
#define MAX_DRIVE_CURRENT_REACH_1   (0x1 << 2)
 
#define DRIVE_CURRENT_SET_1_MASK   (0x3 << 0)
 
#define DRIVE_CURRENT_SET_1_SET(x)   (((x) & 0x3) << 0)
 
#define DRIVE_CURRENT_SET_1_GET(x)   (((x) >> 0) & 0x3)
 
#define DRIVE_CURRENT_SET_1_LEVEL_3   (0x3 << 0)
 
#define DRIVE_CURRENT_SET_1_LEVEL_2   (0x2 << 0)
 
#define DRIVE_CURRENT_SET_1_LEVEL_1   (0x1 << 0)
 
#define DRIVE_CURRENT_SET_1_LEVEL_0   (0x0 << 0)
 
#define MAX_PRE_EMPHASIS_REACH_2   (0x1 << 5)
 
#define PRE_EMPHASIS_SET_2_SET(x)   (((x) & 0x3) << 3)
 
#define PRE_EMPHASIS_SET_2_GET(x)   (((x) >> 3) & 0x3)
 
#define PRE_EMPHASIS_SET_2_MASK   (0x3 << 3)
 
#define PRE_EMPHASIS_SET_2_SHIFT   (3)
 
#define PRE_EMPHASIS_SET_2_LEVEL_3   (0x3 << 3)
 
#define PRE_EMPHASIS_SET_2_LEVEL_2   (0x2 << 3)
 
#define PRE_EMPHASIS_SET_2_LEVEL_1   (0x1 << 3)
 
#define PRE_EMPHASIS_SET_2_LEVEL_0   (0x0 << 3)
 
#define MAX_DRIVE_CURRENT_REACH_2   (0x1 << 2)
 
#define DRIVE_CURRENT_SET_2_MASK   (0x3 << 0)
 
#define DRIVE_CURRENT_SET_2_SET(x)   (((x) & 0x3) << 0)
 
#define DRIVE_CURRENT_SET_2_GET(x)   (((x) >> 0) & 0x3)
 
#define DRIVE_CURRENT_SET_2_LEVEL_3   (0x3 << 0)
 
#define DRIVE_CURRENT_SET_2_LEVEL_2   (0x2 << 0)
 
#define DRIVE_CURRENT_SET_2_LEVEL_1   (0x1 << 0)
 
#define DRIVE_CURRENT_SET_2_LEVEL_0   (0x0 << 0)
 
#define MAX_PRE_EMPHASIS_REACH_3   (0x1 << 5)
 
#define PRE_EMPHASIS_SET_3_SET(x)   (((x) & 0x3) << 3)
 
#define PRE_EMPHASIS_SET_3_GET(x)   (((x) >> 3) & 0x3)
 
#define PRE_EMPHASIS_SET_3_MASK   (0x3 << 3)
 
#define PRE_EMPHASIS_SET_3_SHIFT   (3)
 
#define PRE_EMPHASIS_SET_3_LEVEL_3   (0x3 << 3)
 
#define PRE_EMPHASIS_SET_3_LEVEL_2   (0x2 << 3)
 
#define PRE_EMPHASIS_SET_3_LEVEL_1   (0x1 << 3)
 
#define PRE_EMPHASIS_SET_3_LEVEL_0   (0x0 << 3)
 
#define MAX_DRIVE_CURRENT_REACH_3   (0x1 << 2)
 
#define DRIVE_CURRENT_SET_3_MASK   (0x3 << 0)
 
#define DRIVE_CURRENT_SET_3_SET(x)   (((x) & 0x3) << 0)
 
#define DRIVE_CURRENT_SET_3_GET(x)   (((x) >> 0) & 0x3)
 
#define DRIVE_CURRENT_SET_3_LEVEL_3   (0x3 << 0)
 
#define DRIVE_CURRENT_SET_3_LEVEL_2   (0x2 << 0)
 
#define DRIVE_CURRENT_SET_3_LEVEL_1   (0x1 << 0)
 
#define DRIVE_CURRENT_SET_3_LEVEL_0   (0x0 << 0)
 
#define FORMAT_SEL   (0x1 << 4)
 
#define INTERACE_SCAN_CFG   (0x1 << 2)
 
#define INTERACE_SCAN_CFG_SHIFT   (2)
 
#define VSYNC_POLARITY_CFG   (0x1 << 1)
 
#define V_S_POLARITY_CFG_SHIFT   (1)
 
#define HSYNC_POLARITY_CFG   (0x1 << 0)
 
#define H_S_POLARITY_CFG_SHIFT   (0)
 
#define AUDIO_MODE_SPDIF_MODE   (0x1 << 8)
 
#define AUDIO_MODE_MASTER_MODE   (0x0 << 8)
 
#define MASTER_VIDEO_INTERLACE_EN   (0x1 << 4)
 
#define VIDEO_MASTER_CLK_SEL   (0x1 << 2)
 
#define VIDEO_MASTER_MODE_EN   (0x1 << 1)
 
#define VIDEO_MODE_MASK   (0x1 << 0)
 
#define VIDEO_MODE_SLAVE_MODE   (0x1 << 0)
 
#define VIDEO_MODE_MASTER_MODE   (0x0 << 0)
 
#define VIDEO_EN   (0x1 << 7)
 
#define HDCP_VIDEO_MUTE   (0x1 << 6)
 
#define IN_D_RANGE_MASK   (0x1 << 7)
 
#define IN_D_RANGE_SHIFT   (7)
 
#define IN_D_RANGE_CEA   (0x1 << 7)
 
#define IN_D_RANGE_VESA   (0x0 << 7)
 
#define IN_BPC_MASK   (0x7 << 4)
 
#define IN_BPC_SHIFT   (4)
 
#define IN_BPC_12_BITS   (0x3 << 4)
 
#define IN_BPC_10_BITS   (0x2 << 4)
 
#define IN_BPC_8_BITS   (0x1 << 4)
 
#define IN_BPC_6_BITS   (0x0 << 4)
 
#define IN_COLOR_F_MASK   (0x3 << 0)
 
#define IN_COLOR_F_SHIFT   (0)
 
#define IN_COLOR_F_YCBCR444   (0x2 << 0)
 
#define IN_COLOR_F_YCBCR422   (0x1 << 0)
 
#define IN_COLOR_F_RGB   (0x0 << 0)
 
#define IN_YC_COEFFI_MASK   (0x1 << 7)
 
#define IN_YC_COEFFI_SHIFT   (7)
 
#define IN_YC_COEFFI_ITU709   (0x1 << 7)
 
#define IN_YC_COEFFI_ITU601   (0x0 << 7)
 
#define VID_CHK_UPDATE_TYPE_MASK   (0x1 << 4)
 
#define VID_CHK_UPDATE_TYPE_SHIFT   (4)
 
#define VID_CHK_UPDATE_TYPE_1   (0x1 << 4)
 
#define VID_CHK_UPDATE_TYPE_0   (0x0 << 4)
 
#define TEST_PATTERN_GEN_EN   (0x1 << 0)
 
#define TEST_PATTERN_GEN_DIS   (0x0 << 0)
 
#define TEST_PATTERN_MODE_COLOR_SQUARE   (0x3 << 0)
 
#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES   (0x2 << 0)
 
#define TEST_PATTERN_MODE_COLOR_RAMP   (0x1 << 0)
 
#define BIST_EN   (0x1 << 3)
 
#define BIST_WIDTH_MASK   (0x1 << 2)
 
#define BIST_WIDTH_BAR_32_PIXEL   (0x0 << 2)
 
#define BIST_WIDTH_BAR_64_PIXEL   (0x1 << 2)
 
#define BIST_TYPE_MASK   (0x3 << 0)
 
#define BIST_TYPE_COLOR_BAR   (0x0 << 0)
 
#define BIST_TYPE_WHITE_GRAY_BLACK_BAR   (0x1 << 0)
 
#define BIST_TYPE_MOBILE_WHITE_BAR   (0x2 << 0)
 
#define DET_STA   (0x1 << 2)
 
#define FORCE_DET   (0x1 << 1)
 
#define DET_CTRL   (0x1 << 0)
 
#define CHA_CRI(x)   (((x) & 0xf) << 4)
 
#define CHA_STA   (0x1 << 2)
 
#define FORCE_CHA   (0x1 << 1)
 
#define CHA_CTRL   (0x1 << 0)
 
#define HPD_STATUS   (0x1 << 6)
 
#define F_HPD   (0x1 << 5)
 
#define HPD_CTRL   (0x1 << 4)
 
#define HDCP_RDY   (0x1 << 3)
 
#define STRM_VALID   (0x1 << 2)
 
#define F_VALID   (0x1 << 1)
 
#define VALID_CTRL   (0x1 << 0)
 
#define FIX_M_AUD   (0x1 << 4)
 
#define ENHANCED   (0x1 << 3)
 
#define FIX_M_VID   (0x1 << 2)
 
#define M_VID_UPDATE_CTRL   (0x3 << 0)
 
#define M_VID0_CFG(x)   ((x) & 0xff)
 
#define M_VID1_CFG(x)   (((x) >> 8) & 0xff)
 
#define M_VID2_CFG(x)   (((x) >> 16) & 0xff)
 
#define N_VID0_CFG(x)   ((x) & 0xff)
 
#define N_VID1_CFG(x)   (((x) >> 8) & 0xff)
 
#define N_VID2_CFG(x)   (((x) >> 16) & 0xff)
 
#define DPCD_SCRAMBLING_DISABLED   (0x1 << 5)
 
#define DPCD_SCRAMBLING_ENABLED   (0x0 << 5)
 
#define DPCD_TRAINING_PATTERN_2   (0x2 << 0)
 
#define DPCD_TRAINING_PATTERN_1   (0x1 << 0)
 
#define DPCD_TRAINING_PATTERN_DISABLED   (0x0 << 0)
 
#define DPCD_DPCD_REV   (0x0000)
 
#define DPCD_MAX_LINK_RATE   (0x0001)
 
#define DPCD_MAX_LANE_COUNT   (0x0002)
 
#define DPCD_LINK_BW_SET   (0x0100)
 
#define DPCD_LANE_COUNT_SET   (0x0101)
 
#define DPCD_TRAINING_PATTERN_SET   (0x0102)
 
#define DPCD_TRAINING_LANE0_SET   (0x0103)
 
#define DPCD_LANE0_1_STATUS   (0x0202)
 
#define DPCD_LN_ALIGN_UPDATED   (0x0204)
 
#define DPCD_ADJUST_REQUEST_LANE0_1   (0x0206)
 
#define DPCD_ADJUST_REQUEST_LANE2_3   (0x0207)
 
#define DPCD_TEST_REQUEST   (0x0218)
 
#define DPCD_TEST_RESPONSE   (0x0260)
 
#define DPCD_TEST_EDID_CHECKSUM   (0x0261)
 
#define DPCD_SINK_POWER_STATE   (0x0600)
 
#define DPCD_TEST_EDID_READ   (0x1 << 2)
 
#define DPCD_TEST_EDID_CHECKSUM_WRITE   (0x1 << 2)
 
#define DPCD_SET_POWER_STATE_D0   (0x1 << 0)
 
#define DPCD_SET_POWER_STATE_D4   (0x2 << 0)
 
#define I2C_EDID_DEVICE_ADDR   (0x50)
 
#define I2C_E_EDID_DEVICE_ADDR   (0x30)
 
#define EDID_BLOCK_LENGTH   (0x80)
 
#define EDID_HEADER_PATTERN   (0x00)
 
#define EDID_EXTENSION_FLAG   (0x7e)
 
#define EDID_CHECKSUM   (0x7f)
 
#define DPCD_LANE1_SYMBOL_LOCKED   (0x1 << 6)
 
#define DPCD_LANE1_CHANNEL_EQ_DONE   (0x1 << 5)
 
#define DPCD_LANE1_CR_DONE   (0x1 << 4)
 
#define DPCD_LANE0_SYMBOL_LOCKED   (0x1 << 2)
 
#define DPCD_LANE0_CHANNEL_EQ_DONE   (0x1 << 1)
 
#define DPCD_LANE0_CR_DONE   (0x1 << 0)
 
#define DPCD_PRE_EMPHASIS_LANE1_MASK   (0x3 << 6)
 
#define DPCD_PRE_EMPHASIS_LANE1(x)   (((x) >> 6) & 0x3)
 
#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3   (0x3 << 6)
 
#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2   (0x2 << 6)
 
#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1   (0x1 << 6)
 
#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0   (0x0 << 6)
 
#define DPCD_VOLTAGE_SWING_LANE1_MASK   (0x3 << 4)
 
#define DPCD_VOLTAGE_SWING_LANE1(x)   (((x) >> 4) & 0x3)
 
#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3   (0x3 << 4)
 
#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2   (0x2 << 4)
 
#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1   (0x1 << 4)
 
#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0   (0x0 << 4)
 
#define DPCD_PRE_EMPHASIS_LANE0_MASK   (0x3 << 2)
 
#define DPCD_PRE_EMPHASIS_LANE0(x)   (((x) >> 2) & 0x3)
 
#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3   (0x3 << 2)
 
#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2   (0x2 << 2)
 
#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1   (0x1 << 2)
 
#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0   (0x0 << 2)
 
#define DPCD_VOLTAGE_SWING_LANE0_MASK   (0x3 << 0)
 
#define DPCD_VOLTAGE_SWING_LANE0(x)   (((x) >> 0) & 0x3)
 
#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3   (0x3 << 0)
 
#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2   (0x2 << 0)
 
#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1   (0x1 << 0)
 
#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0   (0x0 << 0)
 
#define DPCD_PRE_EMPHASIS_LANE2_MASK   (0x3 << 6)
 
#define DPCD_PRE_EMPHASIS_LANE2(x)   (((x) >> 6) & 0x3)
 
#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3   (0x3 << 6)
 
#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2   (0x2 << 6)
 
#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1   (0x1 << 6)
 
#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0   (0x0 << 6)
 
#define DPCD_VOLTAGE_SWING_LANE2_MASK   (0x3 << 4)
 
#define DPCD_VOLTAGE_SWING_LANE2(x)   (((x) >> 4) & 0x3)
 
#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3   (0x3 << 4)
 
#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2   (0x2 << 4)
 
#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1   (0x1 << 4)
 
#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0   (0x0 << 4)
 
#define DPCD_PRE_EMPHASIS_LANE3_MASK   (0x3 << 2)
 
#define DPCD_PRE_EMPHASIS_LANE3(x)   (((x) >> 2) & 0x3)
 
#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3   (0x3 << 2)
 
#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2   (0x2 << 2)
 
#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1   (0x1 << 2)
 
#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0   (0x0 << 2)
 
#define DPCD_VOLTAGE_SWING_LANE3_MASK   (0x3 << 0)
 
#define DPCD_VOLTAGE_SWING_LANE3(x)   (((x) >> 0) & 0x3)
 
#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3   (0x3 << 0)
 
#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2   (0x2 << 0)
 
#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1   (0x1 << 0)
 
#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0   (0x0 << 0)
 
#define DPCD_ENHANCED_FRAME_EN   (0x1 << 7)
 
#define DPCD_LN_COUNT_SET(x)   ((x) & 0x1f)
 
#define DPCD_LINK_STATUS_UPDATED   (0x1 << 7)
 
#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED   (0x1 << 6)
 
#define DPCD_INTERLANE_ALIGN_DONE   (0x1 << 0)
 
#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3   (0x3 << 3)
 
#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2   (0x2 << 3)
 
#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1   (0x1 << 3)
 
#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0   (0x0 << 3)
 
#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3   (0x3 << 0)
 
#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2   (0x2 << 0)
 
#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1   (0x1 << 0)
 
#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0   (0x0 << 0)
 
#define DPCD_REQ_ADJ_SWING   (0x00)
 
#define DPCD_REQ_ADJ_EMPHASIS   (0x01)
 
#define DP_LANE_STAT_CR_DONE   (0x01 << 0)
 
#define DP_LANE_STAT_CE_DONE   (0x01 << 1)
 
#define DP_LANE_STAT_SYM_LOCK   (0x01 << 2)
 
#define EXYNOS5_LCD_IF_BASE_OFFSET   0x20000
 
#define EXYNOS_WINCON(x)   (x)
 
#define EXYNOS_VIDOSD(x)   (x * 4)
 
#define EXYNOS_BUFFER_OFFSET(x)   (x * 2)
 
#define EXYNOS_BUFFER_SIZE(x)   (x)
 
#define EXYNOS_VIDCON0_DSI_DISABLE   (0 << 30)
 
#define EXYNOS_VIDCON0_DSI_ENABLE   (1 << 30)
 
#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE   (0 << 29)
 
#define EXYNOS_VIDCON0_SCAN_INTERLACE   (1 << 29)
 
#define EXYNOS_VIDCON0_SCAN_MASK   (1 << 29)
 
#define EXYNOS_VIDCON0_VIDOUT_RGB   (0 << 26)
 
#define EXYNOS_VIDCON0_VIDOUT_ITU   (1 << 26)
 
#define EXYNOS_VIDCON0_VIDOUT_I80LDI0   (2 << 26)
 
#define EXYNOS_VIDCON0_VIDOUT_I80LDI1   (3 << 26)
 
#define EXYNOS_VIDCON0_VIDOUT_WB_RGB   (4 << 26)
 
#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0   (6 << 26)
 
#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1   (7 << 26)
 
#define EXYNOS_VIDCON0_VIDOUT_MASK   (7 << 26)
 
#define EXYNOS_VIDCON0_PNRMODE_RGB_P   (0 << 17)
 
#define EXYNOS_VIDCON0_PNRMODE_BGR_P   (1 << 17)
 
#define EXYNOS_VIDCON0_PNRMODE_RGB_S   (2 << 17)
 
#define EXYNOS_VIDCON0_PNRMODE_BGR_S   (3 << 17)
 
#define EXYNOS_VIDCON0_PNRMODE_MASK   (3 << 17)
 
#define EXYNOS_VIDCON0_PNRMODE_SHIFT   (17)
 
#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS   (0 << 16)
 
#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME   (1 << 16)
 
#define EXYNOS_VIDCON0_CLKVALUP_MASK   (1 << 16)
 
#define EXYNOS_VIDCON0_CLKVAL_F(x)   (((x) & 0xff) << 6)
 
#define EXYNOS_VIDCON0_VCLKEN_NORMAL   (0 << 5)
 
#define EXYNOS_VIDCON0_VCLKEN_FREERUN   (1 << 5)
 
#define EXYNOS_VIDCON0_VCLKEN_MASK   (1 << 5)
 
#define EXYNOS_VIDCON0_CLKDIR_DIRECTED   (0 << 4)
 
#define EXYNOS_VIDCON0_CLKDIR_DIVIDED   (1 << 4)
 
#define EXYNOS_VIDCON0_CLKDIR_MASK   (1 << 4)
 
#define EXYNOS_VIDCON0_CLKSEL_HCLK   (0 << 2)
 
#define EXYNOS_VIDCON0_CLKSEL_SCLK   (1 << 2)
 
#define EXYNOS_VIDCON0_CLKSEL_MASK   (1 << 2)
 
#define EXYNOS_VIDCON0_ENVID_ENABLE   (1 << 1)
 
#define EXYNOS_VIDCON0_ENVID_DISABLE   (0 << 1)
 
#define EXYNOS_VIDCON0_ENVID_F_ENABLE   (1 << 0)
 
#define EXYNOS_VIDCON0_ENVID_F_DISABLE   (0 << 0)
 
#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE   (0 << 7)
 
#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE   (1 << 7)
 
#define EXYNOS_VIDCON1_IHSYNC_NORMAL   (0 << 6)
 
#define EXYNOS_VIDCON1_IHSYNC_INVERT   (1 << 6)
 
#define EXYNOS_VIDCON1_IVSYNC_NORMAL   (0 << 5)
 
#define EXYNOS_VIDCON1_IVSYNC_INVERT   (1 << 5)
 
#define EXYNOS_VIDCON1_IVDEN_NORMAL   (0 << 4)
 
#define EXYNOS_VIDCON1_IVDEN_INVERT   (1 << 4)
 
#define EXYNOS_VIDCON2_EN601_DISABLE   (0 << 23)
 
#define EXYNOS_VIDCON2_EN601_ENABLE   (1 << 23)
 
#define EXYNOS_VIDCON2_EN601_MASK   (1 << 23)
 
#define EXYNOS_VIDCON2_WB_DISABLE   (0 << 15)
 
#define EXYNOS_VIDCON2_WB_ENABLE   (1 << 15)
 
#define EXYNOS_VIDCON2_WB_MASK   (1 << 15)
 
#define EXYNOS_VIDCON2_TVFORMATSEL_HW   (0 << 14)
 
#define EXYNOS_VIDCON2_TVFORMATSEL_SW   (1 << 14)
 
#define EXYNOS_VIDCON2_TVFORMATSEL_MASK   (1 << 14)
 
#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422   (1 << 12)
 
#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444   (2 << 12)
 
#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK   (3 << 12)
 
#define EXYNOS_VIDCON2_ORGYUV_YCBCR   (0 << 8)
 
#define EXYNOS_VIDCON2_ORGYUV_CBCRY   (1 << 8)
 
#define EXYNOS_VIDCON2_ORGYUV_MASK   (1 << 8)
 
#define EXYNOS_VIDCON2_YUVORD_CBCR   (0 << 7)
 
#define EXYNOS_VIDCON2_YUVORD_CRCB   (1 << 7)
 
#define EXYNOS_VIDCON2_YUVORD_MASK   (1 << 7)
 
#define EXYNOS_PRTCON_UPDATABLE   (0 << 11)
 
#define EXYNOS_PRTCON_PROTECT   (1 << 11)
 
#define EXYNOS_VIDTCON0_VBPDE(x)   (((x) & 0xff) << 24)
 
#define EXYNOS_VIDTCON0_VBPD(x)   (((x) & 0xff) << 16)
 
#define EXYNOS_VIDTCON0_VFPD(x)   (((x) & 0xff) << 8)
 
#define EXYNOS_VIDTCON0_VSPW(x)   (((x) & 0xff) << 0)
 
#define EXYNOS_VIDTCON1_VFPDE(x)   (((x) & 0xff) << 24)
 
#define EXYNOS_VIDTCON1_HBPD(x)   (((x) & 0xff) << 16)
 
#define EXYNOS_VIDTCON1_HFPD(x)   (((x) & 0xff) << 8)
 
#define EXYNOS_VIDTCON1_HSPW(x)   (((x) & 0xff) << 0)
 
#define EXYNOS_VIDTCON2_LINEVAL(x)   (((x) & 0x7ff) << 11)
 
#define EXYNOS_VIDTCON2_HOZVAL(x)   (((x) & 0x7ff) << 0)
 
#define EXYNOS_VIDTCON2_LINEVAL_E(x)   ((((x) & 0x800) >> 11) << 23)
 
#define EXYNOS_VIDTCON2_HOZVAL_E(x)   ((((x) & 0x800) >> 11) << 22)
 
#define EXYNOS_WINCON_DATAPATH_DMA   (0 << 22)
 
#define EXYNOS_WINCON_DATAPATH_LOCAL   (1 << 22)
 
#define EXYNOS_WINCON_DATAPATH_MASK   (1 << 22)
 
#define EXYNOS_WINCON_BUFSEL_0   (0 << 20)
 
#define EXYNOS_WINCON_BUFSEL_1   (1 << 20)
 
#define EXYNOS_WINCON_BUFSEL_MASK   (1 << 20)
 
#define EXYNOS_WINCON_BUFSEL_SHIFT   (20)
 
#define EXYNOS_WINCON_BUFAUTO_DISABLE   (0 << 19)
 
#define EXYNOS_WINCON_BUFAUTO_ENABLE   (1 << 19)
 
#define EXYNOS_WINCON_BUFAUTO_MASK   (1 << 19)
 
#define EXYNOS_WINCON_BITSWP_DISABLE   (0 << 18)
 
#define EXYNOS_WINCON_BITSWP_ENABLE   (1 << 18)
 
#define EXYNOS_WINCON_BITSWP_SHIFT   (18)
 
#define EXYNOS_WINCON_BYTESWP_DISABLE   (0 << 17)
 
#define EXYNOS_WINCON_BYTESWP_ENABLE   (1 << 17)
 
#define EXYNOS_WINCON_BYTESWP_SHIFT   (17)
 
#define EXYNOS_WINCON_HAWSWP_DISABLE   (0 << 16)
 
#define EXYNOS_WINCON_HAWSWP_ENABLE   (1 << 16)
 
#define EXYNOS_WINCON_HAWSWP_SHIFT   (16)
 
#define EXYNOS_WINCON_WSWP_DISABLE   (0 << 15)
 
#define EXYNOS_WINCON_WSWP_ENABLE   (1 << 15)
 
#define EXYNOS_WINCON_WSWP_SHIFT   (15)
 
#define EXYNOS_WINCON_INRGB_RGB   (0 << 13)
 
#define EXYNOS_WINCON_INRGB_YUV   (1 << 13)
 
#define EXYNOS_WINCON_INRGB_MASK   (1 << 13)
 
#define EXYNOS_WINCON_BURSTLEN_16WORD   (0 << 9)
 
#define EXYNOS_WINCON_BURSTLEN_8WORD   (1 << 9)
 
#define EXYNOS_WINCON_BURSTLEN_4WORD   (2 << 9)
 
#define EXYNOS_WINCON_BURSTLEN_MASK   (3 << 9)
 
#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE   (0 << 7)
 
#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE   (1 << 7)
 
#define EXYNOS_WINCON_BLD_PLANE   (0 << 6)
 
#define EXYNOS_WINCON_BLD_PIXEL   (1 << 6)
 
#define EXYNOS_WINCON_BLD_MASK   (1 << 6)
 
#define EXYNOS_WINCON_BPPMODE_1BPP   (0 << 2)
 
#define EXYNOS_WINCON_BPPMODE_2BPP   (1 << 2)
 
#define EXYNOS_WINCON_BPPMODE_4BPP   (2 << 2)
 
#define EXYNOS_WINCON_BPPMODE_8BPP_PAL   (3 << 2)
 
#define EXYNOS_WINCON_BPPMODE_8BPP   (4 << 2)
 
#define EXYNOS_WINCON_BPPMODE_16BPP_565   (5 << 2)
 
#define EXYNOS_WINCON_BPPMODE_16BPP_A555   (6 << 2)
 
#define EXYNOS_WINCON_BPPMODE_18BPP_666   (8 << 2)
 
#define EXYNOS_WINCON_BPPMODE_18BPP_A665   (9 << 2)
 
#define EXYNOS_WINCON_BPPMODE_24BPP_888   (0xb << 2)
 
#define EXYNOS_WINCON_BPPMODE_24BPP_A887   (0xc << 2)
 
#define EXYNOS_WINCON_BPPMODE_32BPP   (0xd << 2)
 
#define EXYNOS_WINCON_BPPMODE_16BPP_A444   (0xe << 2)
 
#define EXYNOS_WINCON_BPPMODE_15BPP_555   (0xf << 2)
 
#define EXYNOS_WINCON_BPPMODE_MASK   (0xf << 2)
 
#define EXYNOS_WINCON_BPPMODE_SHIFT   (2)
 
#define EXYNOS_WINCON_ALPHA0_SEL   (0 << 1)
 
#define EXYNOS_WINCON_ALPHA1_SEL   (1 << 1)
 
#define EXYNOS_WINCON_ALPHA_SEL_MASK   (1 << 1)
 
#define EXYNOS_WINCON_ENWIN_DISABLE   (0 << 0)
 
#define EXYNOS_WINCON_ENWIN_ENABLE   (1 << 0)
 
#define EXYNOS_WINCON1_VP_DISABLE   (0 << 24)
 
#define EXYNOS_WINCON1_VP_ENABLE   (1 << 24)
 
#define EXYNOS_WINCON1_LOCALSEL_FIMC1   (0 << 23)
 
#define EXYNOS_WINCON1_LOCALSEL_VP   (1 << 23)
 
#define EXYNOS_WINCON1_LOCALSEL_MASK   (1 << 23)
 
#define EXYNOS_WINSHMAP_PROTECT(x)   (((x) & 0x1f) << 10)
 
#define EXYNOS_WINSHMAP_CH_ENABLE(x)   (1 << (x))
 
#define EXYNOS_WINSHMAP_CH_DISABLE(x)   (1 << (x))
 
#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x)   (0x20 << (x))
 
#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x)   (0x20 << (x))
 
#define EXYNOS_VIDOSD_LEFT_X(x)   (((x) & 0x7ff) << 11)
 
#define EXYNOS_VIDOSD_TOP_Y(x)   (((x) & 0x7ff) << 0)
 
#define EXYNOS_VIDOSD_RIGHT_X(x)   (((x) & 0x7ff) << 11)
 
#define EXYNOS_VIDOSD_BOTTOM_Y(x)   (((x) & 0x7ff) << 0)
 
#define EXYNOS_VIDOSD_RIGHT_X_E(x)   (((x) & 0x1) << 23)
 
#define EXYNOS_VIDOSD_BOTTOM_Y_E(x)   (((x) & 0x1) << 22)
 
#define EXYNOS_VIDOSD_SIZE(x)   (((x) & 0xffffff) << 0)
 
#define EXYNOS_VIDOSD_ALPHA0_R(x)   (((x) & 0xf) << 20)
 
#define EXYNOS_VIDOSD_ALPHA0_G(x)   (((x) & 0xf) << 16)
 
#define EXYNOS_VIDOSD_ALPHA0_B(x)   (((x) & 0xf) << 12)
 
#define EXYNOS_VIDOSD_ALPHA1_R(x)   (((x) & 0xf) << 8)
 
#define EXYNOS_VIDOSD_ALPHA1_G(x)   (((x) & 0xf) << 4)
 
#define EXYNOS_VIDOSD_ALPHA1_B(x)   (((x) & 0xf) << 0)
 
#define EXYNOS_VIDOSD_ALPHA0_SHIFT   (12)
 
#define EXYNOS_VIDOSD_ALPHA1_SHIFT   (0)
 
#define EXYNOS_VIDADDR_START_VBANK(x)   (((x) & 0xff) << 24)
 
#define EXYNOS_VIDADDR_START_VBASEU(x)   (((x) & 0xffffff) << 0)
 
#define EXYNOS_VIDADDR_END_VBASEL(x)   (((x) & 0xffffff) << 0)
 
#define EXYNOS_VIDADDR_OFFSIZE(x)   (((x) & 0x1fff) << 13)
 
#define EXYNOS_VIDADDR_PAGEWIDTH(x)   (((x) & 0x1fff) << 0)
 
#define EXYNOS_VIDADDR_OFFSIZE_E(x)   ((((x) & 0x2000) >> 13) << 27)
 
#define EXYNOS_VIDADDR_PAGEWIDTH_E(x)   ((((x) & 0x2000) >> 13) << 26)
 
#define EXYNOS_WINMAP_COLOR(x)   ((x) & 0xffffff)
 
#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE   (0 << 19)
 
#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE   (1 << 19)
 
#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE   (0 << 18)
 
#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE   (1 << 18)
 
#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE   (0 << 17)
 
#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE   (1 << 17)
 
#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK   (0 << 15)
 
#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC   (1 << 15)
 
#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE   (2 << 15)
 
#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT   (3 << 15)
 
#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK   (3 << 15)
 
#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE   (0 << 13)
 
#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK   (1 << 13)
 
#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC   (2 << 13)
 
#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT   (3 << 13)
 
#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE   (0 << 12)
 
#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE   (1 << 12)
 
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4   (1 << 11)
 
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3   (1 << 10)
 
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2   (1 << 9)
 
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1   (1 << 6)
 
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0   (1 << 5)
 
#define EXYNOS_VIDINTCON0_FIFOSEL_ALL   (0x73 << 5)
 
#define EXYNOS_VIDINTCON0_FIFOSEL_MASK   (0x73 << 5)
 
#define EXYNOS_VIDINTCON0_FIFOLEVEL_25   (0 << 2)
 
#define EXYNOS_VIDINTCON0_FIFOLEVEL_50   (1 << 2)
 
#define EXYNOS_VIDINTCON0_FIFOLEVEL_75   (2 << 2)
 
#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY   (3 << 2)
 
#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL   (4 << 2)
 
#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK   (7 << 2)
 
#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE   (0 << 1)
 
#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE   (1 << 1)
 
#define EXYNOS_VIDINTCON0_INT_DISABLE   (0 << 0)
 
#define EXYNOS_VIDINTCON0_INT_ENABLE   (1 << 0)
 
#define EXYNOS_VIDINTCON0_INT_MASK   (1 << 0)
 
#define EXYNOS_VIDINTCON1_INTVPPEND   (1 << 5)
 
#define EXYNOS_VIDINTCON1_INTI80PEND   (1 << 2)
 
#define EXYNOS_VIDINTCON1_INTFRMPEND   (1 << 1)
 
#define EXYNOS_VIDINTCON1_INTFIFOPEND   (1 << 0)
 
#define EXYNOS_WINMAP_ENABLE   (1 << 24)
 
#define EXYNOS_KEYCON0_KEYBLEN_DISABLE   (0 << 26)
 
#define EXYNOS_KEYCON0_KEYBLEN_ENABLE   (1 << 26)
 
#define EXYNOS_KEYCON0_KEY_DISABLE   (0 << 25)
 
#define EXYNOS_KEYCON0_KEY_ENABLE   (1 << 25)
 
#define EXYNOS_KEYCON0_DIRCON_MATCH_FG   (0 << 24)
 
#define EXYNOS_KEYCON0_DIRCON_MATCH_BG   (1 << 24)
 
#define EXYNOS_KEYCON0_COMPKEY(x)   (((x) & 0xffffff) << 0)
 
#define EXYNOS_KEYCON1_COLVAL(x)   (((x) & 0xffffff) << 0)
 
#define EXYNOS_DUALRGB_BYPASS_SINGLE   (0x00 << 0)
 
#define EXYNOS_DUALRGB_BYPASS_DUAL   (0x01 << 0)
 
#define EXYNOS_DUALRGB_MIE_DUAL   (0x10 << 0)
 
#define EXYNOS_DUALRGB_MIE_SINGLE   (0x11 << 0)
 
#define EXYNOS_DUALRGB_LINESPLIT   (0x0 << 2)
 
#define EXYNOS_DUALRGB_FRAMESPLIT   (0x1 << 2)
 
#define EXYNOS_DUALRGB_SUB_CNT(x)   ((x & 0xfff) << 4)
 
#define EXYNOS_DUALRGB_VDEN_EN_DISABLE   (0x0 << 16)
 
#define EXYNOS_DUALRGB_VDEN_EN_ENABLE   (0x1 << 16)
 
#define EXYNOS_DUALRGB_MAIN_CNT(x)   ((x & 0xfff) << 18)
 
#define EXYNOS_LCD_CS_SETUP(x)   (((x) & 0xf) << 16)
 
#define EXYNOS_LCD_WR_SETUP(x)   (((x) & 0xf) << 12)
 
#define EXYNOS_LCD_WR_ACT(x)   (((x) & 0xf) << 8)
 
#define EXYNOS_LCD_WR_HOLD(x)   (((x) & 0xf) << 4)
 
#define EXYNOS_RSPOL_LOW   (0 << 2)
 
#define EXYNOS_RSPOL_HIGH   (1 << 2)
 
#define EXYNOS_I80IFEN_DISABLE   (0 << 0)
 
#define EXYNOS_I80IFEN_ENABLE   (1 << 0)
 
#define EXYNOS_I80SOFT_TRIG_EN   (1 << 0)
 
#define EXYNOS_I80START_TRIG   (1 << 1)
 
#define EXYNOS_I80STATUS_TRIG_DONE   (1 << 2)
 
#define EXYNOS_DP_MIE_DISABLE   (0 << 0)
 
#define EXYNOS_DP_CLK_ENABLE   (1 << 1)
 
#define EXYNOS_MIE_CLK_ENABLE   (3 << 0)
 
#define DP_TIMEOUT_LOOP_COUNT   1000
 
#define MAX_CR_LOOP   5
 
#define MAX_EQ_LOOP   4
 
#define EXYNOS_DP_SUCCESS   0
 

Enumerations

enum  { DP_DISABLE , DP_ENABLE }
 
enum  analog_power_block {
  AUX_BLOCK , CH0_BLOCK , CH1_BLOCK , CH2_BLOCK ,
  CH3_BLOCK , ANALOG_TOTAL , POWER_ALL , AUX_BLOCK ,
  CH0_BLOCK , CH1_BLOCK , CH2_BLOCK , CH3_BLOCK ,
  ANALOG_TOTAL , POWER_ALL
}
 
enum  pll_status {
  DP_PLL_UNLOCKED , DP_PLL_LOCKED , PLL_UNLOCKED , PLL_LOCKED ,
  PLL_UNLOCKED = 0 , PLL_LOCKED
}
 
enum  { COLOR_RGB , COLOR_YCBCR422 , COLOR_YCBCR444 }
 
enum  { VESA , CEA }
 
enum  { COLOR_YCBCR601 , COLOR_YCBCR709 }
 
enum  { COLOR_6 , COLOR_8 , COLOR_10 , COLOR_12 }
 
enum  { DP_LANE_BW_1_62 = 0x06 , DP_LANE_BW_2_70 = 0x0a }
 
enum  { DP_LANE_CNT_1 = 1 , DP_LANE_CNT_2 = 2 , DP_LANE_CNT_4 = 4 }
 
enum  { DP_DPCD_REV_10 = 0x10 , DP_DPCD_REV_11 = 0x11 }
 
enum  {
  DP_LT_NONE , DP_LT_START , DP_LT_CR , DP_LT_ET ,
  DP_LT_FINISHED , DP_LT_FAIL
}
 
enum  { PRE_EMPHASIS_LEVEL_0 , PRE_EMPHASIS_LEVEL_1 , PRE_EMPHASIS_LEVEL_2 , PRE_EMPHASIS_LEVEL_3 }
 
enum  {
  PRBS7 , D10_2 , TRAINING_PTN1 , TRAINING_PTN2 ,
  DP_NONE
}
 
enum  { VOLTAGE_LEVEL_0 , VOLTAGE_LEVEL_1 , VOLTAGE_LEVEL_2 , VOLTAGE_LEVEL_3 }
 
enum  pattern_type {
  NO_PATTERN , COLOR_RAMP , BALCK_WHITE_V_LINES , COLOR_SQUARE ,
  INVALID_PATTERN , COLORBAR_32 , COLORBAR_64 , WHITE_GRAY_BALCKBAR_32 ,
  WHITE_GRAY_BALCKBAR_64 , MOBILE_WHITEBAR_32 , MOBILE_WHITEBAR_64
}
 
enum  { CALCULATED_M , REGISTER_M }
 
enum  { VIDEO_TIMING_FROM_CAPTURE , VIDEO_TIMING_FROM_REGISTER }
 

Functions

 check_member (exynos_dp, phy_ctrl, 0x924)
 
int exynos_init_dp (struct edp_device_info *edp_info)
 
void exynos_set_dp_platform_data (struct exynos_dp_platform_data *pd)
 
void exynos_dp_disable_video_bist (void)
 
void exynos_dp_enable_video_mute (unsigned int enable)
 
void exynos_dp_reset (void)
 
void exynos_dp_enable_sw_func (unsigned int enable)
 
unsigned int exynos_dp_set_analog_power_down (unsigned int block, u32 enable)
 
unsigned int exynos_dp_get_pll_lock_status (void)
 
int exynos_dp_init_analog_func (void)
 
void exynos_dp_init_hpd (void)
 
void exynos_dp_init_aux (void)
 
void exynos_dp_config_interrupt (void)
 
unsigned int exynos_dp_get_plug_in_status (void)
 
unsigned int exynos_dp_detect_hpd (void)
 
unsigned int exynos_dp_start_aux_transaction (void)
 
unsigned int exynos_dp_write_byte_to_dpcd (u32 reg_addr, u8 data)
 
unsigned int exynos_dp_read_byte_from_dpcd (u32 reg_addr, u8 *data)
 
unsigned int exynos_dp_write_bytes_to_dpcd (u32 reg_addr, unsigned int count, u8 data[])
 
u32 exynos_dp_read_bytes_from_dpcd (unsigned int reg_addr, unsigned int count, u8 data[])
 
int exynos_dp_select_i2c_device (u32 device_addr, u32 reg_addr)
 
int exynos_dp_read_byte_from_i2c (u32 device_addr, u32 reg_addr, unsigned int *data)
 
int exynos_dp_read_bytes_from_i2c (u32 device_addr, u32 reg_addr, unsigned int count, u8 edid[])
 
void exynos_dp_reset_macro (void)
 
void exynos_dp_set_link_bandwidth (u8 bwtype)
 
u8 exynos_dp_get_link_bandwidth (void)
 
void exynos_dp_set_lane_count (u8 count)
 
unsigned int exynos_dp_get_lane_count (void)
 
u8 exynos_dp_get_lanex_pre_emphasis (u8 lanecnt)
 
void exynos_dp_set_lane_pre_emphasis (unsigned int level, u8 lanecnt)
 
void exynos_dp_set_lanex_pre_emphasis (u8 request_val, u8 lanecnt)
 
void exynos_dp_set_training_pattern (unsigned int pattern)
 
void exynos_dp_enable_enhanced_mode (u8 enable)
 
void exynos_dp_enable_scrambling (unsigned int enable)
 
int exynos_dp_init_video (void)
 
void exynos_dp_config_video_slave_mode (struct edp_video_info *video_info)
 
void exynos_dp_set_video_color_format (struct edp_video_info *video_info)
 
int exynos_dp_config_video_bist (struct edp_device_info *edp_info)
 
unsigned int exynos_dp_is_slave_video_stream_clock_on (void)
 
void exynos_dp_set_video_cr_mn (unsigned int type, unsigned int m_value, unsigned int n_value)
 
void exynos_dp_set_video_timing_mode (unsigned int type)
 
void exynos_dp_enable_video_master (unsigned int enable)
 
void exynos_dp_start_video (void)
 
unsigned int exynos_dp_is_video_stream_on (void)
 
void exynos_dp_set_base_addr (void)
 
void dp_phy_control (unsigned int enable)
 

Variables

static struct exynos_dp *const exynos_dp0 = (void *)EXYNOS5_DP0_BASE
 
static struct exynos_dp *const exynos_dp1 = (void *)EXYNOS5_DP1_BASE
 

Macro Definition Documentation

◆ ACTIVE_LINE_CFG_H

#define ACTIVE_LINE_CFG_H (   x)    (((x) >> 8) & 0xff)

Definition at line 415 of file dp.h.

◆ ACTIVE_LINE_CFG_L

#define ACTIVE_LINE_CFG_L (   x)    ((x) & 0xff)

Definition at line 414 of file dp.h.

◆ ACTIVE_PIXEL_CFG_H

#define ACTIVE_PIXEL_CFG_H (   x)    ((((x) >> 8)) & 0xff)

Definition at line 419 of file dp.h.

◆ ACTIVE_PIXEL_CFG_L

#define ACTIVE_PIXEL_CFG_L (   x)    ((x) & 0xff)

Definition at line 418 of file dp.h.

◆ ADDR_ONLY

#define ADDR_ONLY   (0x1 << 1)

Definition at line 381 of file dp.h.

◆ AUD_CLK_CHG

#define AUD_CLK_CHG   (0x1 << 2)

Definition at line 301 of file dp.h.

◆ AUD_FIFO_FUNC_EN_N

#define AUD_FIFO_FUNC_EN_N   (0x1 << 4)

Definition at line 275 of file dp.h.

◆ AUD_FUNC_EN_N

#define AUD_FUNC_EN_N   (0x1 << 3)

Definition at line 276 of file dp.h.

◆ AUDIO_MODE_MASTER_MODE

#define AUDIO_MODE_MASTER_MODE   (0x0 << 8)

Definition at line 515 of file dp.h.

◆ AUDIO_MODE_SPDIF_MODE

#define AUDIO_MODE_SPDIF_MODE   (0x1 << 8)

Definition at line 514 of file dp.h.

◆ AUX_ADDR_15_8

#define AUX_ADDR_15_8 (   x)    (((x) >> 8) & 0xff)

Definition at line 366 of file dp.h.

◆ AUX_ADDR_19_16

#define AUX_ADDR_19_16 (   x)    (((x) >> 16) & 0x0f)

Definition at line 369 of file dp.h.

◆ AUX_ADDR_7_0

#define AUX_ADDR_7_0 (   x)    (((x) >> 0) & 0xff)

Definition at line 363 of file dp.h.

◆ AUX_BIT_PERIOD_EXPECTED_DELAY

#define AUX_BIT_PERIOD_EXPECTED_DELAY (   x)    (((x) & 0x7) << 8)

Definition at line 340 of file dp.h.

◆ AUX_BUSY

#define AUX_BUSY   (0x1 << 4)

Definition at line 385 of file dp.h.

◆ AUX_EN

#define AUX_EN   (0x1 << 0)

Definition at line 382 of file dp.h.

◆ AUX_ERR

#define AUX_ERR   (0x1 << 0)

Definition at line 328 of file dp.h.

◆ AUX_FUNC_EN_N [1/2]

#define AUX_FUNC_EN_N   (0x1 << 2)

Definition at line 312 of file dp.h.

◆ AUX_FUNC_EN_N [2/2]

#define AUX_FUNC_EN_N   (0x1 << 2)

Definition at line 312 of file dp.h.

◆ AUX_HW_RETRY_COUNT_SEL

#define AUX_HW_RETRY_COUNT_SEL (   x)    (((x) & 0x7) << 0)

Definition at line 346 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS

#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS   (0x2 << 3)

Definition at line 344 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS

#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS   (0x3 << 3)

Definition at line 345 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_600_MICROSECONDS

#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS   (0x0 << 3)

Definition at line 342 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_800_MICROSECONDS

#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS   (0x1 << 3)

Definition at line 343 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_MASK

#define AUX_HW_RETRY_INTERVAL_MASK   (0x3 << 3)

Definition at line 341 of file dp.h.

◆ AUX_LENGTH

#define AUX_LENGTH (   x)    (((x - 1) & 0xf) << 4)

Definition at line 372 of file dp.h.

◆ AUX_PD

#define AUX_PD   (0x1 << 4)

Definition at line 289 of file dp.h.

◆ AUX_RX_COMM_AUX_DEFER

#define AUX_RX_COMM_AUX_DEFER   (0x2 << 0)

Definition at line 390 of file dp.h.

◆ AUX_RX_COMM_I2C_DEFER

#define AUX_RX_COMM_I2C_DEFER   (0x2 << 2)

Definition at line 389 of file dp.h.

◆ AUX_STATUS_MASK

#define AUX_STATUS_MASK   (0xf << 0)

Definition at line 386 of file dp.h.

◆ AUX_TERMINAL_CTRL_102_OHM

#define AUX_TERMINAL_CTRL_102_OHM   (0x1 << 4)

Definition at line 242 of file dp.h.

◆ AUX_TERMINAL_CTRL_200_OHM

#define AUX_TERMINAL_CTRL_200_OHM   (0x0 << 4)

Definition at line 243 of file dp.h.

◆ AUX_TERMINAL_CTRL_52_OHM

#define AUX_TERMINAL_CTRL_52_OHM   (0x3 << 4)

Definition at line 240 of file dp.h.

◆ AUX_TERMINAL_CTRL_69_OHM

#define AUX_TERMINAL_CTRL_69_OHM   (0x2 << 4)

Definition at line 241 of file dp.h.

◆ AUX_TX_COMM_DP_TRANSACTION

#define AUX_TX_COMM_DP_TRANSACTION   (0x1 << 3)

Definition at line 374 of file dp.h.

◆ AUX_TX_COMM_I2C_TRANSACTION

#define AUX_TX_COMM_I2C_TRANSACTION   (0x0 << 3)

Definition at line 375 of file dp.h.

◆ AUX_TX_COMM_MASK

#define AUX_TX_COMM_MASK   (0xf << 0)

Definition at line 373 of file dp.h.

◆ AUX_TX_COMM_MOT

#define AUX_TX_COMM_MOT   (0x1 << 2)

Definition at line 376 of file dp.h.

◆ AUX_TX_COMM_READ

#define AUX_TX_COMM_READ   (0x1 << 0)

Definition at line 378 of file dp.h.

◆ AUX_TX_COMM_WRITE

#define AUX_TX_COMM_WRITE   (0x0 << 0)

Definition at line 377 of file dp.h.

◆ BIST_EN

#define BIST_EN   (0x1 << 3)

Definition at line 564 of file dp.h.

◆ BIST_TYPE_COLOR_BAR

#define BIST_TYPE_COLOR_BAR   (0x0 << 0)

Definition at line 569 of file dp.h.

◆ BIST_TYPE_MASK

#define BIST_TYPE_MASK   (0x3 << 0)

Definition at line 568 of file dp.h.

◆ BIST_TYPE_MOBILE_WHITE_BAR

#define BIST_TYPE_MOBILE_WHITE_BAR   (0x2 << 0)

Definition at line 571 of file dp.h.

◆ BIST_TYPE_WHITE_GRAY_BLACK_BAR

#define BIST_TYPE_WHITE_GRAY_BLACK_BAR   (0x1 << 0)

Definition at line 570 of file dp.h.

◆ BIST_WIDTH_BAR_32_PIXEL

#define BIST_WIDTH_BAR_32_PIXEL   (0x0 << 2)

Definition at line 566 of file dp.h.

◆ BIST_WIDTH_BAR_64_PIXEL

#define BIST_WIDTH_BAR_64_PIXEL   (0x1 << 2)

Definition at line 567 of file dp.h.

◆ BIST_WIDTH_MASK

#define BIST_WIDTH_MASK   (0x1 << 2)

Definition at line 565 of file dp.h.

◆ BUF_CLR

#define BUF_CLR   (0x1 << 7)

Definition at line 359 of file dp.h.

◆ BUF_DATA_COUNT

#define BUF_DATA_COUNT (   x)    (((x) & 0x1f) << 0)

Definition at line 360 of file dp.h.

◆ CH0_AMP_0_MV

#define CH0_AMP_0_MV   (0x3 << 0)

Definition at line 256 of file dp.h.

◆ CH0_PD

#define CH0_PD   (0x1 << 0)

Definition at line 293 of file dp.h.

◆ CH0_TEST

#define CH0_TEST   (0x1 << 0)

Definition at line 395 of file dp.h.

◆ CH1_AMP_0_MV

#define CH1_AMP_0_MV   (0x3 << 4)

Definition at line 255 of file dp.h.

◆ CH1_PD

#define CH1_PD   (0x1 << 1)

Definition at line 292 of file dp.h.

◆ CH1_TEST

#define CH1_TEST   (0x1 << 1)

Definition at line 394 of file dp.h.

◆ CH2_AMP_0_MV

#define CH2_AMP_0_MV   (0x3 << 8)

Definition at line 254 of file dp.h.

◆ CH2_PD

#define CH2_PD   (0x1 << 2)

Definition at line 291 of file dp.h.

◆ CH3_AMP_0_MV

#define CH3_AMP_0_MV   (0x3 << 12)

Definition at line 253 of file dp.h.

◆ CH3_PD

#define CH3_PD   (0x1 << 3)

Definition at line 290 of file dp.h.

◆ CHA_CRI

#define CHA_CRI (   x)    (((x) & 0xf) << 4)

Definition at line 579 of file dp.h.

◆ CHA_CTRL

#define CHA_CTRL   (0x1 << 0)

Definition at line 582 of file dp.h.

◆ CHA_STA

#define CHA_STA   (0x1 << 2)

Definition at line 580 of file dp.h.

◆ COMMON_INT_MASK_1

#define COMMON_INT_MASK_1   (0)

Definition at line 352 of file dp.h.

◆ COMMON_INT_MASK_2

#define COMMON_INT_MASK_2   (0)

Definition at line 353 of file dp.h.

◆ COMMON_INT_MASK_3

#define COMMON_INT_MASK_3   (0)

Definition at line 354 of file dp.h.

◆ COMMON_INT_MASK_4

#define COMMON_INT_MASK_4   (0)

Definition at line 355 of file dp.h.

◆ CPREG_BLEED

#define CPREG_BLEED   (0x1 << 4)

Definition at line 218 of file dp.h.

◆ CRC_FUNC_EN_N

#define CRC_FUNC_EN_N   (0x1 << 1)

Definition at line 278 of file dp.h.

◆ DEFER_COUNT

#define DEFER_COUNT (   x)    (((x) & 0x7f) << 0)

Definition at line 350 of file dp.h.

◆ DEFER_CTRL_EN

#define DEFER_CTRL_EN   (0x1 << 7)

Definition at line 349 of file dp.h.

◆ DET_CTRL

#define DET_CTRL   (0x1 << 0)

Definition at line 576 of file dp.h.

◆ DET_STA

#define DET_STA   (0x1 << 2)

Definition at line 574 of file dp.h.

◆ DP_LANE_STAT_CE_DONE

#define DP_LANE_STAT_CE_DONE   (0x01 << 1)

Definition at line 734 of file dp.h.

◆ DP_LANE_STAT_CR_DONE

#define DP_LANE_STAT_CR_DONE   (0x01 << 0)

Definition at line 733 of file dp.h.

◆ DP_LANE_STAT_SYM_LOCK

#define DP_LANE_STAT_SYM_LOCK   (0x01 << 2)

Definition at line 735 of file dp.h.

◆ DP_PLL_LOOP_BIT_DEFAULT

#define DP_PLL_LOOP_BIT_DEFAULT   (0x1 << 4)

Definition at line 261 of file dp.h.

◆ DP_PLL_PD

#define DP_PLL_PD   (0x1 << 7)

Definition at line 259 of file dp.h.

◆ DP_PLL_REF_BIT_1_1250V

#define DP_PLL_REF_BIT_1_1250V   (0x5 << 0)

Definition at line 262 of file dp.h.

◆ DP_PLL_REF_BIT_1_2500V

#define DP_PLL_REF_BIT_1_2500V   (0x7 << 0)

Definition at line 263 of file dp.h.

◆ DP_PLL_RESET

#define DP_PLL_RESET   (0x1 << 6)

Definition at line 260 of file dp.h.

◆ DP_TIMEOUT_LOOP_COUNT

#define DP_TIMEOUT_LOOP_COUNT   1000

Definition at line 1173 of file dp.h.

◆ DPCD_ADJUST_REQUEST_LANE0_1

#define DPCD_ADJUST_REQUEST_LANE0_1   (0x0206)

Definition at line 626 of file dp.h.

◆ DPCD_ADJUST_REQUEST_LANE2_3

#define DPCD_ADJUST_REQUEST_LANE2_3   (0x0207)

Definition at line 627 of file dp.h.

◆ DPCD_DOWNSTREAM_PORT_STATUS_CHANGED

#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED   (0x1 << 6)

Definition at line 717 of file dp.h.

◆ DPCD_DPCD_REV

#define DPCD_DPCD_REV   (0x0000)

Definition at line 617 of file dp.h.

◆ DPCD_ENHANCED_FRAME_EN

#define DPCD_ENHANCED_FRAME_EN   (0x1 << 7)

Definition at line 712 of file dp.h.

◆ DPCD_INTERLANE_ALIGN_DONE

#define DPCD_INTERLANE_ALIGN_DONE   (0x1 << 0)

Definition at line 718 of file dp.h.

◆ DPCD_LANE0_1_STATUS

#define DPCD_LANE0_1_STATUS   (0x0202)

Definition at line 624 of file dp.h.

◆ DPCD_LANE0_CHANNEL_EQ_DONE

#define DPCD_LANE0_CHANNEL_EQ_DONE   (0x1 << 1)

Definition at line 656 of file dp.h.

◆ DPCD_LANE0_CR_DONE

#define DPCD_LANE0_CR_DONE   (0x1 << 0)

Definition at line 657 of file dp.h.

◆ DPCD_LANE0_SYMBOL_LOCKED

#define DPCD_LANE0_SYMBOL_LOCKED   (0x1 << 2)

Definition at line 655 of file dp.h.

◆ DPCD_LANE1_CHANNEL_EQ_DONE

#define DPCD_LANE1_CHANNEL_EQ_DONE   (0x1 << 5)

Definition at line 653 of file dp.h.

◆ DPCD_LANE1_CR_DONE

#define DPCD_LANE1_CR_DONE   (0x1 << 4)

Definition at line 654 of file dp.h.

◆ DPCD_LANE1_SYMBOL_LOCKED

#define DPCD_LANE1_SYMBOL_LOCKED   (0x1 << 6)

Definition at line 652 of file dp.h.

◆ DPCD_LANE_COUNT_SET

#define DPCD_LANE_COUNT_SET   (0x0101)

Definition at line 621 of file dp.h.

◆ DPCD_LINK_BW_SET

#define DPCD_LINK_BW_SET   (0x0100)

Definition at line 620 of file dp.h.

◆ DPCD_LINK_STATUS_UPDATED

#define DPCD_LINK_STATUS_UPDATED   (0x1 << 7)

Definition at line 716 of file dp.h.

◆ DPCD_LN_ALIGN_UPDATED

#define DPCD_LN_ALIGN_UPDATED   (0x0204)

Definition at line 625 of file dp.h.

◆ DPCD_LN_COUNT_SET

#define DPCD_LN_COUNT_SET (   x)    ((x) & 0x1f)

Definition at line 713 of file dp.h.

◆ DPCD_MAX_LANE_COUNT

#define DPCD_MAX_LANE_COUNT   (0x0002)

Definition at line 619 of file dp.h.

◆ DPCD_MAX_LINK_RATE

#define DPCD_MAX_LINK_RATE   (0x0001)

Definition at line 618 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE0

#define DPCD_PRE_EMPHASIS_LANE0 (   x)    (((x) >> 2) & 0x3)

Definition at line 673 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE0_LEVEL_0

#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0   (0x0 << 2)

Definition at line 677 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE0_LEVEL_1

#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1   (0x1 << 2)

Definition at line 676 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE0_LEVEL_2

#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2   (0x2 << 2)

Definition at line 675 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE0_LEVEL_3

#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3   (0x3 << 2)

Definition at line 674 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE0_MASK

#define DPCD_PRE_EMPHASIS_LANE0_MASK   (0x3 << 2)

Definition at line 672 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE1

#define DPCD_PRE_EMPHASIS_LANE1 (   x)    (((x) >> 6) & 0x3)

Definition at line 661 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE1_LEVEL_0

#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0   (0x0 << 6)

Definition at line 665 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE1_LEVEL_1

#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1   (0x1 << 6)

Definition at line 664 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE1_LEVEL_2

#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2   (0x2 << 6)

Definition at line 663 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE1_LEVEL_3

#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3   (0x3 << 6)

Definition at line 662 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE1_MASK

#define DPCD_PRE_EMPHASIS_LANE1_MASK   (0x3 << 6)

Definition at line 660 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE2

#define DPCD_PRE_EMPHASIS_LANE2 (   x)    (((x) >> 6) & 0x3)

Definition at line 687 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE2_LEVEL_0

#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0   (0x0 << 6)

Definition at line 691 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE2_LEVEL_1

#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1   (0x1 << 6)

Definition at line 690 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE2_LEVEL_2

#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2   (0x2 << 6)

Definition at line 689 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE2_LEVEL_3

#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3   (0x3 << 6)

Definition at line 688 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE2_MASK

#define DPCD_PRE_EMPHASIS_LANE2_MASK   (0x3 << 6)

Definition at line 686 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE3

#define DPCD_PRE_EMPHASIS_LANE3 (   x)    (((x) >> 2) & 0x3)

Definition at line 699 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE3_LEVEL_0

#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0   (0x0 << 2)

Definition at line 703 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE3_LEVEL_1

#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1   (0x1 << 2)

Definition at line 702 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE3_LEVEL_2

#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2   (0x2 << 2)

Definition at line 701 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE3_LEVEL_3

#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3   (0x3 << 2)

Definition at line 700 of file dp.h.

◆ DPCD_PRE_EMPHASIS_LANE3_MASK

#define DPCD_PRE_EMPHASIS_LANE3_MASK   (0x3 << 2)

Definition at line 698 of file dp.h.

◆ DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0

#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0   (0x0 << 3)

Definition at line 724 of file dp.h.

◆ DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1

#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1   (0x1 << 3)

Definition at line 723 of file dp.h.

◆ DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2

#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2   (0x2 << 3)

Definition at line 722 of file dp.h.

◆ DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3

#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3   (0x3 << 3)

Definition at line 721 of file dp.h.

◆ DPCD_REQ_ADJ_EMPHASIS

#define DPCD_REQ_ADJ_EMPHASIS   (0x01)

Definition at line 731 of file dp.h.

◆ DPCD_REQ_ADJ_SWING

#define DPCD_REQ_ADJ_SWING   (0x00)

Definition at line 730 of file dp.h.

◆ DPCD_SCRAMBLING_DISABLED

#define DPCD_SCRAMBLING_DISABLED   (0x1 << 5)

Definition at line 610 of file dp.h.

◆ DPCD_SCRAMBLING_ENABLED

#define DPCD_SCRAMBLING_ENABLED   (0x0 << 5)

Definition at line 611 of file dp.h.

◆ DPCD_SET_POWER_STATE_D0

#define DPCD_SET_POWER_STATE_D0   (0x1 << 0)

Definition at line 640 of file dp.h.

◆ DPCD_SET_POWER_STATE_D4

#define DPCD_SET_POWER_STATE_D4   (0x2 << 0)

Definition at line 641 of file dp.h.

◆ DPCD_SINK_POWER_STATE

#define DPCD_SINK_POWER_STATE   (0x0600)

Definition at line 631 of file dp.h.

◆ DPCD_TEST_EDID_CHECKSUM

#define DPCD_TEST_EDID_CHECKSUM   (0x0261)

Definition at line 630 of file dp.h.

◆ DPCD_TEST_EDID_CHECKSUM_WRITE

#define DPCD_TEST_EDID_CHECKSUM_WRITE   (0x1 << 2)

Definition at line 637 of file dp.h.

◆ DPCD_TEST_EDID_READ

#define DPCD_TEST_EDID_READ   (0x1 << 2)

Definition at line 634 of file dp.h.

◆ DPCD_TEST_REQUEST

#define DPCD_TEST_REQUEST   (0x0218)

Definition at line 628 of file dp.h.

◆ DPCD_TEST_RESPONSE

#define DPCD_TEST_RESPONSE   (0x0260)

Definition at line 629 of file dp.h.

◆ DPCD_TRAINING_LANE0_SET

#define DPCD_TRAINING_LANE0_SET   (0x0103)

Definition at line 623 of file dp.h.

◆ DPCD_TRAINING_PATTERN_1

#define DPCD_TRAINING_PATTERN_1   (0x1 << 0)

Definition at line 613 of file dp.h.

◆ DPCD_TRAINING_PATTERN_2

#define DPCD_TRAINING_PATTERN_2   (0x2 << 0)

Definition at line 612 of file dp.h.

◆ DPCD_TRAINING_PATTERN_DISABLED

#define DPCD_TRAINING_PATTERN_DISABLED   (0x0 << 0)

Definition at line 614 of file dp.h.

◆ DPCD_TRAINING_PATTERN_SET

#define DPCD_TRAINING_PATTERN_SET   (0x0102)

Definition at line 622 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE0

#define DPCD_VOLTAGE_SWING_LANE0 (   x)    (((x) >> 0) & 0x3)

Definition at line 679 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE0_LEVEL_0

#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0   (0x0 << 0)

Definition at line 683 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE0_LEVEL_1

#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1   (0x1 << 0)

Definition at line 682 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE0_LEVEL_2

#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2   (0x2 << 0)

Definition at line 681 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE0_LEVEL_3

#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3   (0x3 << 0)

Definition at line 680 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE0_MASK

#define DPCD_VOLTAGE_SWING_LANE0_MASK   (0x3 << 0)

Definition at line 678 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE1

#define DPCD_VOLTAGE_SWING_LANE1 (   x)    (((x) >> 4) & 0x3)

Definition at line 667 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE1_LEVEL_0

#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0   (0x0 << 4)

Definition at line 671 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE1_LEVEL_1

#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1   (0x1 << 4)

Definition at line 670 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE1_LEVEL_2

#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2   (0x2 << 4)

Definition at line 669 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE1_LEVEL_3

#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3   (0x3 << 4)

Definition at line 668 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE1_MASK

#define DPCD_VOLTAGE_SWING_LANE1_MASK   (0x3 << 4)

Definition at line 666 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE2

#define DPCD_VOLTAGE_SWING_LANE2 (   x)    (((x) >> 4) & 0x3)

Definition at line 693 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE2_LEVEL_0

#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0   (0x0 << 4)

Definition at line 697 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE2_LEVEL_1

#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1   (0x1 << 4)

Definition at line 696 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE2_LEVEL_2

#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2   (0x2 << 4)

Definition at line 695 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE2_LEVEL_3

#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3   (0x3 << 4)

Definition at line 694 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE2_MASK

#define DPCD_VOLTAGE_SWING_LANE2_MASK   (0x3 << 4)

Definition at line 692 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE3

#define DPCD_VOLTAGE_SWING_LANE3 (   x)    (((x) >> 0) & 0x3)

Definition at line 705 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE3_LEVEL_0

#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0   (0x0 << 0)

Definition at line 709 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE3_LEVEL_1

#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1   (0x1 << 0)

Definition at line 708 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE3_LEVEL_2

#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2   (0x2 << 0)

Definition at line 707 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE3_LEVEL_3

#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3   (0x3 << 0)

Definition at line 706 of file dp.h.

◆ DPCD_VOLTAGE_SWING_LANE3_MASK

#define DPCD_VOLTAGE_SWING_LANE3_MASK   (0x3 << 0)

Definition at line 704 of file dp.h.

◆ DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0

#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0   (0x0 << 0)

Definition at line 728 of file dp.h.

◆ DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1

#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1   (0x1 << 0)

Definition at line 727 of file dp.h.

◆ DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2

#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2   (0x2 << 0)

Definition at line 726 of file dp.h.

◆ DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3

#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3   (0x3 << 0)

Definition at line 725 of file dp.h.

◆ DRIVE_CURRENT_SET_0_GET

#define DRIVE_CURRENT_SET_0_GET (   x)    (((x) >> 0) & 0x3)

Definition at line 441 of file dp.h.

◆ DRIVE_CURRENT_SET_0_LEVEL_0

#define DRIVE_CURRENT_SET_0_LEVEL_0   (0x0 << 0)

Definition at line 445 of file dp.h.

◆ DRIVE_CURRENT_SET_0_LEVEL_1

#define DRIVE_CURRENT_SET_0_LEVEL_1   (0x1 << 0)

Definition at line 444 of file dp.h.

◆ DRIVE_CURRENT_SET_0_LEVEL_2

#define DRIVE_CURRENT_SET_0_LEVEL_2   (0x2 << 0)

Definition at line 443 of file dp.h.

◆ DRIVE_CURRENT_SET_0_LEVEL_3

#define DRIVE_CURRENT_SET_0_LEVEL_3   (0x3 << 0)

Definition at line 442 of file dp.h.

◆ DRIVE_CURRENT_SET_0_MASK

#define DRIVE_CURRENT_SET_0_MASK   (0x3 << 0)

Definition at line 439 of file dp.h.

◆ DRIVE_CURRENT_SET_0_SET

#define DRIVE_CURRENT_SET_0_SET (   x)    (((x) & 0x3) << 0)

Definition at line 440 of file dp.h.

◆ DRIVE_CURRENT_SET_1_GET

#define DRIVE_CURRENT_SET_1_GET (   x)    (((x) >> 0) & 0x3)

Definition at line 460 of file dp.h.

◆ DRIVE_CURRENT_SET_1_LEVEL_0

#define DRIVE_CURRENT_SET_1_LEVEL_0   (0x0 << 0)

Definition at line 464 of file dp.h.

◆ DRIVE_CURRENT_SET_1_LEVEL_1

#define DRIVE_CURRENT_SET_1_LEVEL_1   (0x1 << 0)

Definition at line 463 of file dp.h.

◆ DRIVE_CURRENT_SET_1_LEVEL_2

#define DRIVE_CURRENT_SET_1_LEVEL_2   (0x2 << 0)

Definition at line 462 of file dp.h.

◆ DRIVE_CURRENT_SET_1_LEVEL_3

#define DRIVE_CURRENT_SET_1_LEVEL_3   (0x3 << 0)

Definition at line 461 of file dp.h.

◆ DRIVE_CURRENT_SET_1_MASK

#define DRIVE_CURRENT_SET_1_MASK   (0x3 << 0)

Definition at line 458 of file dp.h.

◆ DRIVE_CURRENT_SET_1_SET

#define DRIVE_CURRENT_SET_1_SET (   x)    (((x) & 0x3) << 0)

Definition at line 459 of file dp.h.

◆ DRIVE_CURRENT_SET_2_GET

#define DRIVE_CURRENT_SET_2_GET (   x)    (((x) >> 0) & 0x3)

Definition at line 479 of file dp.h.

◆ DRIVE_CURRENT_SET_2_LEVEL_0

#define DRIVE_CURRENT_SET_2_LEVEL_0   (0x0 << 0)

Definition at line 483 of file dp.h.

◆ DRIVE_CURRENT_SET_2_LEVEL_1

#define DRIVE_CURRENT_SET_2_LEVEL_1   (0x1 << 0)

Definition at line 482 of file dp.h.

◆ DRIVE_CURRENT_SET_2_LEVEL_2

#define DRIVE_CURRENT_SET_2_LEVEL_2   (0x2 << 0)

Definition at line 481 of file dp.h.

◆ DRIVE_CURRENT_SET_2_LEVEL_3

#define DRIVE_CURRENT_SET_2_LEVEL_3   (0x3 << 0)

Definition at line 480 of file dp.h.

◆ DRIVE_CURRENT_SET_2_MASK

#define DRIVE_CURRENT_SET_2_MASK   (0x3 << 0)

Definition at line 477 of file dp.h.

◆ DRIVE_CURRENT_SET_2_SET

#define DRIVE_CURRENT_SET_2_SET (   x)    (((x) & 0x3) << 0)

Definition at line 478 of file dp.h.

◆ DRIVE_CURRENT_SET_3_GET

#define DRIVE_CURRENT_SET_3_GET (   x)    (((x) >> 0) & 0x3)

Definition at line 498 of file dp.h.

◆ DRIVE_CURRENT_SET_3_LEVEL_0

#define DRIVE_CURRENT_SET_3_LEVEL_0   (0x0 << 0)

Definition at line 502 of file dp.h.

◆ DRIVE_CURRENT_SET_3_LEVEL_1

#define DRIVE_CURRENT_SET_3_LEVEL_1   (0x1 << 0)

Definition at line 501 of file dp.h.

◆ DRIVE_CURRENT_SET_3_LEVEL_2

#define DRIVE_CURRENT_SET_3_LEVEL_2   (0x2 << 0)

Definition at line 500 of file dp.h.

◆ DRIVE_CURRENT_SET_3_LEVEL_3

#define DRIVE_CURRENT_SET_3_LEVEL_3   (0x3 << 0)

Definition at line 499 of file dp.h.

◆ DRIVE_CURRENT_SET_3_MASK

#define DRIVE_CURRENT_SET_3_MASK   (0x3 << 0)

Definition at line 496 of file dp.h.

◆ DRIVE_CURRENT_SET_3_SET

#define DRIVE_CURRENT_SET_3_SET (   x)    (((x) & 0x3) << 0)

Definition at line 497 of file dp.h.

◆ DRIVE_DVDD_BIT_1_0000V

#define DRIVE_DVDD_BIT_1_0000V   (0x3 << 5)

Definition at line 225 of file dp.h.

◆ DRIVE_DVDD_BIT_1_0625V

#define DRIVE_DVDD_BIT_1_0625V   (0x4 << 5)

Definition at line 226 of file dp.h.

◆ DRIVE_DVDD_BIT_1_1250V

#define DRIVE_DVDD_BIT_1_1250V   (0x5 << 5)

Definition at line 227 of file dp.h.

◆ EDID_BLOCK_LENGTH

#define EDID_BLOCK_LENGTH   (0x80)

Definition at line 646 of file dp.h.

◆ EDID_CHECKSUM

#define EDID_CHECKSUM   (0x7f)

Definition at line 649 of file dp.h.

◆ EDID_EXTENSION_FLAG

#define EDID_EXTENSION_FLAG   (0x7e)

Definition at line 648 of file dp.h.

◆ EDID_HEADER_PATTERN

#define EDID_HEADER_PATTERN   (0x00)

Definition at line 647 of file dp.h.

◆ ENHANCED

#define ENHANCED   (0x1 << 3)

Definition at line 595 of file dp.h.

◆ EXYNOS5_LCD_IF_BASE_OFFSET

#define EXYNOS5_LCD_IF_BASE_OFFSET   0x20000

Definition at line 871 of file dp.h.

◆ EXYNOS_BUFFER_OFFSET

#define EXYNOS_BUFFER_OFFSET (   x)    (x * 2)

Definition at line 878 of file dp.h.

◆ EXYNOS_BUFFER_SIZE

#define EXYNOS_BUFFER_SIZE (   x)    (x)

Definition at line 879 of file dp.h.

◆ EXYNOS_DP_CLK_ENABLE

#define EXYNOS_DP_CLK_ENABLE   (1 << 1)

Definition at line 1170 of file dp.h.

◆ EXYNOS_DP_MIE_DISABLE

#define EXYNOS_DP_MIE_DISABLE   (0 << 0)

Definition at line 1169 of file dp.h.

◆ EXYNOS_DP_SUCCESS

#define EXYNOS_DP_SUCCESS   0

Definition at line 1177 of file dp.h.

◆ EXYNOS_DUALRGB_BYPASS_DUAL

#define EXYNOS_DUALRGB_BYPASS_DUAL   (0x01 << 0)

Definition at line 1143 of file dp.h.

◆ EXYNOS_DUALRGB_BYPASS_SINGLE

#define EXYNOS_DUALRGB_BYPASS_SINGLE   (0x00 << 0)

Definition at line 1142 of file dp.h.

◆ EXYNOS_DUALRGB_FRAMESPLIT

#define EXYNOS_DUALRGB_FRAMESPLIT   (0x1 << 2)

Definition at line 1147 of file dp.h.

◆ EXYNOS_DUALRGB_LINESPLIT

#define EXYNOS_DUALRGB_LINESPLIT   (0x0 << 2)

Definition at line 1146 of file dp.h.

◆ EXYNOS_DUALRGB_MAIN_CNT

#define EXYNOS_DUALRGB_MAIN_CNT (   x)    ((x & 0xfff) << 18)

Definition at line 1151 of file dp.h.

◆ EXYNOS_DUALRGB_MIE_DUAL

#define EXYNOS_DUALRGB_MIE_DUAL   (0x10 << 0)

Definition at line 1144 of file dp.h.

◆ EXYNOS_DUALRGB_MIE_SINGLE

#define EXYNOS_DUALRGB_MIE_SINGLE   (0x11 << 0)

Definition at line 1145 of file dp.h.

◆ EXYNOS_DUALRGB_SUB_CNT

#define EXYNOS_DUALRGB_SUB_CNT (   x)    ((x & 0xfff) << 4)

Definition at line 1148 of file dp.h.

◆ EXYNOS_DUALRGB_VDEN_EN_DISABLE

#define EXYNOS_DUALRGB_VDEN_EN_DISABLE   (0x0 << 16)

Definition at line 1149 of file dp.h.

◆ EXYNOS_DUALRGB_VDEN_EN_ENABLE

#define EXYNOS_DUALRGB_VDEN_EN_ENABLE   (0x1 << 16)

Definition at line 1150 of file dp.h.

◆ EXYNOS_I80IFEN_DISABLE

#define EXYNOS_I80IFEN_DISABLE   (0 << 0)

Definition at line 1160 of file dp.h.

◆ EXYNOS_I80IFEN_ENABLE

#define EXYNOS_I80IFEN_ENABLE   (1 << 0)

Definition at line 1161 of file dp.h.

◆ EXYNOS_I80SOFT_TRIG_EN

#define EXYNOS_I80SOFT_TRIG_EN   (1 << 0)

Definition at line 1164 of file dp.h.

◆ EXYNOS_I80START_TRIG

#define EXYNOS_I80START_TRIG   (1 << 1)

Definition at line 1165 of file dp.h.

◆ EXYNOS_I80STATUS_TRIG_DONE

#define EXYNOS_I80STATUS_TRIG_DONE   (1 << 2)

Definition at line 1166 of file dp.h.

◆ EXYNOS_KEYCON0_COMPKEY

#define EXYNOS_KEYCON0_COMPKEY (   x)    (((x) & 0xffffff) << 0)

Definition at line 1136 of file dp.h.

◆ EXYNOS_KEYCON0_DIRCON_MATCH_BG

#define EXYNOS_KEYCON0_DIRCON_MATCH_BG   (1 << 24)

Definition at line 1135 of file dp.h.

◆ EXYNOS_KEYCON0_DIRCON_MATCH_FG

#define EXYNOS_KEYCON0_DIRCON_MATCH_FG   (0 << 24)

Definition at line 1134 of file dp.h.

◆ EXYNOS_KEYCON0_KEY_DISABLE

#define EXYNOS_KEYCON0_KEY_DISABLE   (0 << 25)

Definition at line 1132 of file dp.h.

◆ EXYNOS_KEYCON0_KEY_ENABLE

#define EXYNOS_KEYCON0_KEY_ENABLE   (1 << 25)

Definition at line 1133 of file dp.h.

◆ EXYNOS_KEYCON0_KEYBLEN_DISABLE

#define EXYNOS_KEYCON0_KEYBLEN_DISABLE   (0 << 26)

Definition at line 1130 of file dp.h.

◆ EXYNOS_KEYCON0_KEYBLEN_ENABLE

#define EXYNOS_KEYCON0_KEYBLEN_ENABLE   (1 << 26)

Definition at line 1131 of file dp.h.

◆ EXYNOS_KEYCON1_COLVAL

#define EXYNOS_KEYCON1_COLVAL (   x)    (((x) & 0xffffff) << 0)

Definition at line 1139 of file dp.h.

◆ EXYNOS_LCD_CS_SETUP

#define EXYNOS_LCD_CS_SETUP (   x)    (((x) & 0xf) << 16)

Definition at line 1154 of file dp.h.

◆ EXYNOS_LCD_WR_ACT

#define EXYNOS_LCD_WR_ACT (   x)    (((x) & 0xf) << 8)

Definition at line 1156 of file dp.h.

◆ EXYNOS_LCD_WR_HOLD

#define EXYNOS_LCD_WR_HOLD (   x)    (((x) & 0xf) << 4)

Definition at line 1157 of file dp.h.

◆ EXYNOS_LCD_WR_SETUP

#define EXYNOS_LCD_WR_SETUP (   x)    (((x) & 0xf) << 12)

Definition at line 1155 of file dp.h.

◆ EXYNOS_MIE_CLK_ENABLE

#define EXYNOS_MIE_CLK_ENABLE   (3 << 0)

Definition at line 1171 of file dp.h.

◆ EXYNOS_PRTCON_PROTECT

#define EXYNOS_PRTCON_PROTECT   (1 << 11)

Definition at line 955 of file dp.h.

◆ EXYNOS_PRTCON_UPDATABLE

#define EXYNOS_PRTCON_UPDATABLE   (0 << 11)

Definition at line 954 of file dp.h.

◆ EXYNOS_RSPOL_HIGH

#define EXYNOS_RSPOL_HIGH   (1 << 2)

Definition at line 1159 of file dp.h.

◆ EXYNOS_RSPOL_LOW

#define EXYNOS_RSPOL_LOW   (0 << 2)

Definition at line 1158 of file dp.h.

◆ EXYNOS_VIDADDR_END_VBASEL

#define EXYNOS_VIDADDR_END_VBASEL (   x)    (((x) & 0xffffff) << 0)

Definition at line 1072 of file dp.h.

◆ EXYNOS_VIDADDR_OFFSIZE

#define EXYNOS_VIDADDR_OFFSIZE (   x)    (((x) & 0x1fff) << 13)

Definition at line 1075 of file dp.h.

◆ EXYNOS_VIDADDR_OFFSIZE_E

#define EXYNOS_VIDADDR_OFFSIZE_E (   x)    ((((x) & 0x2000) >> 13) << 27)

Definition at line 1077 of file dp.h.

◆ EXYNOS_VIDADDR_PAGEWIDTH

#define EXYNOS_VIDADDR_PAGEWIDTH (   x)    (((x) & 0x1fff) << 0)

Definition at line 1076 of file dp.h.

◆ EXYNOS_VIDADDR_PAGEWIDTH_E

#define EXYNOS_VIDADDR_PAGEWIDTH_E (   x)    ((((x) & 0x2000) >> 13) << 26)

Definition at line 1078 of file dp.h.

◆ EXYNOS_VIDADDR_START_VBANK

#define EXYNOS_VIDADDR_START_VBANK (   x)    (((x) & 0xff) << 24)

Definition at line 1068 of file dp.h.

◆ EXYNOS_VIDADDR_START_VBASEU

#define EXYNOS_VIDADDR_START_VBASEU (   x)    (((x) & 0xffffff) << 0)

Definition at line 1069 of file dp.h.

◆ EXYNOS_VIDCON0_CLKDIR_DIRECTED

#define EXYNOS_VIDCON0_CLKDIR_DIRECTED   (0 << 4)

Definition at line 912 of file dp.h.

◆ EXYNOS_VIDCON0_CLKDIR_DIVIDED

#define EXYNOS_VIDCON0_CLKDIR_DIVIDED   (1 << 4)

Definition at line 913 of file dp.h.

◆ EXYNOS_VIDCON0_CLKDIR_MASK

#define EXYNOS_VIDCON0_CLKDIR_MASK   (1 << 4)

Definition at line 914 of file dp.h.

◆ EXYNOS_VIDCON0_CLKSEL_HCLK

#define EXYNOS_VIDCON0_CLKSEL_HCLK   (0 << 2)

Definition at line 915 of file dp.h.

◆ EXYNOS_VIDCON0_CLKSEL_MASK

#define EXYNOS_VIDCON0_CLKSEL_MASK   (1 << 2)

Definition at line 917 of file dp.h.

◆ EXYNOS_VIDCON0_CLKSEL_SCLK

#define EXYNOS_VIDCON0_CLKSEL_SCLK   (1 << 2)

Definition at line 916 of file dp.h.

◆ EXYNOS_VIDCON0_CLKVAL_F

#define EXYNOS_VIDCON0_CLKVAL_F (   x)    (((x) & 0xff) << 6)

Definition at line 908 of file dp.h.

◆ EXYNOS_VIDCON0_CLKVALUP_ALWAYS

#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS   (0 << 16)

Definition at line 905 of file dp.h.

◆ EXYNOS_VIDCON0_CLKVALUP_MASK

#define EXYNOS_VIDCON0_CLKVALUP_MASK   (1 << 16)

Definition at line 907 of file dp.h.

◆ EXYNOS_VIDCON0_CLKVALUP_START_FRAME

#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME   (1 << 16)

Definition at line 906 of file dp.h.

◆ EXYNOS_VIDCON0_DSI_DISABLE

#define EXYNOS_VIDCON0_DSI_DISABLE   (0 << 30)

Definition at line 886 of file dp.h.

◆ EXYNOS_VIDCON0_DSI_ENABLE

#define EXYNOS_VIDCON0_DSI_ENABLE   (1 << 30)

Definition at line 887 of file dp.h.

◆ EXYNOS_VIDCON0_ENVID_DISABLE

#define EXYNOS_VIDCON0_ENVID_DISABLE   (0 << 1)

Definition at line 919 of file dp.h.

◆ EXYNOS_VIDCON0_ENVID_ENABLE

#define EXYNOS_VIDCON0_ENVID_ENABLE   (1 << 1)

Definition at line 918 of file dp.h.

◆ EXYNOS_VIDCON0_ENVID_F_DISABLE

#define EXYNOS_VIDCON0_ENVID_F_DISABLE   (0 << 0)

Definition at line 921 of file dp.h.

◆ EXYNOS_VIDCON0_ENVID_F_ENABLE

#define EXYNOS_VIDCON0_ENVID_F_ENABLE   (1 << 0)

Definition at line 920 of file dp.h.

◆ EXYNOS_VIDCON0_PNRMODE_BGR_P

#define EXYNOS_VIDCON0_PNRMODE_BGR_P   (1 << 17)

Definition at line 900 of file dp.h.

◆ EXYNOS_VIDCON0_PNRMODE_BGR_S

#define EXYNOS_VIDCON0_PNRMODE_BGR_S   (3 << 17)

Definition at line 902 of file dp.h.

◆ EXYNOS_VIDCON0_PNRMODE_MASK

#define EXYNOS_VIDCON0_PNRMODE_MASK   (3 << 17)

Definition at line 903 of file dp.h.

◆ EXYNOS_VIDCON0_PNRMODE_RGB_P

#define EXYNOS_VIDCON0_PNRMODE_RGB_P   (0 << 17)

Definition at line 899 of file dp.h.

◆ EXYNOS_VIDCON0_PNRMODE_RGB_S

#define EXYNOS_VIDCON0_PNRMODE_RGB_S   (2 << 17)

Definition at line 901 of file dp.h.

◆ EXYNOS_VIDCON0_PNRMODE_SHIFT

#define EXYNOS_VIDCON0_PNRMODE_SHIFT   (17)

Definition at line 904 of file dp.h.

◆ EXYNOS_VIDCON0_SCAN_INTERLACE

#define EXYNOS_VIDCON0_SCAN_INTERLACE   (1 << 29)

Definition at line 889 of file dp.h.

◆ EXYNOS_VIDCON0_SCAN_MASK

#define EXYNOS_VIDCON0_SCAN_MASK   (1 << 29)

Definition at line 890 of file dp.h.

◆ EXYNOS_VIDCON0_SCAN_PROGRESSIVE

#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE   (0 << 29)

Definition at line 888 of file dp.h.

◆ EXYNOS_VIDCON0_VCLKEN_FREERUN

#define EXYNOS_VIDCON0_VCLKEN_FREERUN   (1 << 5)

Definition at line 910 of file dp.h.

◆ EXYNOS_VIDCON0_VCLKEN_MASK

#define EXYNOS_VIDCON0_VCLKEN_MASK   (1 << 5)

Definition at line 911 of file dp.h.

◆ EXYNOS_VIDCON0_VCLKEN_NORMAL

#define EXYNOS_VIDCON0_VCLKEN_NORMAL   (0 << 5)

Definition at line 909 of file dp.h.

◆ EXYNOS_VIDCON0_VIDOUT_I80LDI0

#define EXYNOS_VIDCON0_VIDOUT_I80LDI0   (2 << 26)

Definition at line 893 of file dp.h.

◆ EXYNOS_VIDCON0_VIDOUT_I80LDI1

#define EXYNOS_VIDCON0_VIDOUT_I80LDI1   (3 << 26)

Definition at line 894 of file dp.h.

◆ EXYNOS_VIDCON0_VIDOUT_ITU

#define EXYNOS_VIDCON0_VIDOUT_ITU   (1 << 26)

Definition at line 892 of file dp.h.

◆ EXYNOS_VIDCON0_VIDOUT_MASK

#define EXYNOS_VIDCON0_VIDOUT_MASK   (7 << 26)

Definition at line 898 of file dp.h.

◆ EXYNOS_VIDCON0_VIDOUT_RGB

#define EXYNOS_VIDCON0_VIDOUT_RGB   (0 << 26)

Definition at line 891 of file dp.h.

◆ EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0

#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0   (6 << 26)

Definition at line 896 of file dp.h.

◆ EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1

#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1   (7 << 26)

Definition at line 897 of file dp.h.

◆ EXYNOS_VIDCON0_VIDOUT_WB_RGB

#define EXYNOS_VIDCON0_VIDOUT_WB_RGB   (4 << 26)

Definition at line 895 of file dp.h.

◆ EXYNOS_VIDCON1_IHSYNC_INVERT

#define EXYNOS_VIDCON1_IHSYNC_INVERT   (1 << 6)

Definition at line 927 of file dp.h.

◆ EXYNOS_VIDCON1_IHSYNC_NORMAL

#define EXYNOS_VIDCON1_IHSYNC_NORMAL   (0 << 6)

Definition at line 926 of file dp.h.

◆ EXYNOS_VIDCON1_IVCLK_FALLING_EDGE

#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE   (0 << 7)

Definition at line 924 of file dp.h.

◆ EXYNOS_VIDCON1_IVCLK_RISING_EDGE

#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE   (1 << 7)

Definition at line 925 of file dp.h.

◆ EXYNOS_VIDCON1_IVDEN_INVERT

#define EXYNOS_VIDCON1_IVDEN_INVERT   (1 << 4)

Definition at line 931 of file dp.h.

◆ EXYNOS_VIDCON1_IVDEN_NORMAL

#define EXYNOS_VIDCON1_IVDEN_NORMAL   (0 << 4)

Definition at line 930 of file dp.h.

◆ EXYNOS_VIDCON1_IVSYNC_INVERT

#define EXYNOS_VIDCON1_IVSYNC_INVERT   (1 << 5)

Definition at line 929 of file dp.h.

◆ EXYNOS_VIDCON1_IVSYNC_NORMAL

#define EXYNOS_VIDCON1_IVSYNC_NORMAL   (0 << 5)

Definition at line 928 of file dp.h.

◆ EXYNOS_VIDCON2_EN601_DISABLE

#define EXYNOS_VIDCON2_EN601_DISABLE   (0 << 23)

Definition at line 934 of file dp.h.

◆ EXYNOS_VIDCON2_EN601_ENABLE

#define EXYNOS_VIDCON2_EN601_ENABLE   (1 << 23)

Definition at line 935 of file dp.h.

◆ EXYNOS_VIDCON2_EN601_MASK

#define EXYNOS_VIDCON2_EN601_MASK   (1 << 23)

Definition at line 936 of file dp.h.

◆ EXYNOS_VIDCON2_ORGYUV_CBCRY

#define EXYNOS_VIDCON2_ORGYUV_CBCRY   (1 << 8)

Definition at line 947 of file dp.h.

◆ EXYNOS_VIDCON2_ORGYUV_MASK

#define EXYNOS_VIDCON2_ORGYUV_MASK   (1 << 8)

Definition at line 948 of file dp.h.

◆ EXYNOS_VIDCON2_ORGYUV_YCBCR

#define EXYNOS_VIDCON2_ORGYUV_YCBCR   (0 << 8)

Definition at line 946 of file dp.h.

◆ EXYNOS_VIDCON2_TVFORMATSEL_HW

#define EXYNOS_VIDCON2_TVFORMATSEL_HW   (0 << 14)

Definition at line 940 of file dp.h.

◆ EXYNOS_VIDCON2_TVFORMATSEL_MASK

#define EXYNOS_VIDCON2_TVFORMATSEL_MASK   (1 << 14)

Definition at line 942 of file dp.h.

◆ EXYNOS_VIDCON2_TVFORMATSEL_SW

#define EXYNOS_VIDCON2_TVFORMATSEL_SW   (1 << 14)

Definition at line 941 of file dp.h.

◆ EXYNOS_VIDCON2_TVFORMATSEL_YUV422

#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422   (1 << 12)

Definition at line 943 of file dp.h.

◆ EXYNOS_VIDCON2_TVFORMATSEL_YUV444

#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444   (2 << 12)

Definition at line 944 of file dp.h.

◆ EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK

#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK   (3 << 12)

Definition at line 945 of file dp.h.

◆ EXYNOS_VIDCON2_WB_DISABLE

#define EXYNOS_VIDCON2_WB_DISABLE   (0 << 15)

Definition at line 937 of file dp.h.

◆ EXYNOS_VIDCON2_WB_ENABLE

#define EXYNOS_VIDCON2_WB_ENABLE   (1 << 15)

Definition at line 938 of file dp.h.

◆ EXYNOS_VIDCON2_WB_MASK

#define EXYNOS_VIDCON2_WB_MASK   (1 << 15)

Definition at line 939 of file dp.h.

◆ EXYNOS_VIDCON2_YUVORD_CBCR

#define EXYNOS_VIDCON2_YUVORD_CBCR   (0 << 7)

Definition at line 949 of file dp.h.

◆ EXYNOS_VIDCON2_YUVORD_CRCB

#define EXYNOS_VIDCON2_YUVORD_CRCB   (1 << 7)

Definition at line 950 of file dp.h.

◆ EXYNOS_VIDCON2_YUVORD_MASK

#define EXYNOS_VIDCON2_YUVORD_MASK   (1 << 7)

Definition at line 951 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOLEVEL_25

#define EXYNOS_VIDINTCON0_FIFOLEVEL_25   (0 << 2)

Definition at line 1108 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOLEVEL_50

#define EXYNOS_VIDINTCON0_FIFOLEVEL_50   (1 << 2)

Definition at line 1109 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOLEVEL_75

#define EXYNOS_VIDINTCON0_FIFOLEVEL_75   (2 << 2)

Definition at line 1110 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY

#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY   (3 << 2)

Definition at line 1111 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOLEVEL_FULL

#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL   (4 << 2)

Definition at line 1112 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOLEVEL_MASK

#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK   (7 << 2)

Definition at line 1113 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOSEL_ALL

#define EXYNOS_VIDINTCON0_FIFOSEL_ALL   (0x73 << 5)

Definition at line 1106 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOSEL_MASK

#define EXYNOS_VIDINTCON0_FIFOSEL_MASK   (0x73 << 5)

Definition at line 1107 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOSEL_WIN0

#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0   (1 << 5)

Definition at line 1105 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOSEL_WIN1

#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1   (1 << 6)

Definition at line 1104 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOSEL_WIN2

#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2   (1 << 9)

Definition at line 1103 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOSEL_WIN3

#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3   (1 << 10)

Definition at line 1102 of file dp.h.

◆ EXYNOS_VIDINTCON0_FIFOSEL_WIN4

#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4   (1 << 11)

Definition at line 1101 of file dp.h.

◆ EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE

#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE   (2 << 15)

Definition at line 1092 of file dp.h.

◆ EXYNOS_VIDINTCON0_FRAMESEL0_BACK

#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK   (0 << 15)

Definition at line 1090 of file dp.h.

◆ EXYNOS_VIDINTCON0_FRAMESEL0_FRONT

#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT   (3 << 15)

Definition at line 1093 of file dp.h.

◆ EXYNOS_VIDINTCON0_FRAMESEL0_MASK

#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK   (3 << 15)

Definition at line 1094 of file dp.h.

◆ EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC

#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC   (1 << 15)

Definition at line 1091 of file dp.h.

◆ EXYNOS_VIDINTCON0_FRAMESEL1_BACK

#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK   (1 << 13)

Definition at line 1096 of file dp.h.

◆ EXYNOS_VIDINTCON0_FRAMESEL1_FRONT

#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT   (3 << 13)

Definition at line 1098 of file dp.h.

◆ EXYNOS_VIDINTCON0_FRAMESEL1_NONE

#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE   (0 << 13)

Definition at line 1095 of file dp.h.

◆ EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC

#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC   (2 << 13)

Definition at line 1097 of file dp.h.

◆ EXYNOS_VIDINTCON0_INT_DISABLE

#define EXYNOS_VIDINTCON0_INT_DISABLE   (0 << 0)

Definition at line 1116 of file dp.h.

◆ EXYNOS_VIDINTCON0_INT_ENABLE

#define EXYNOS_VIDINTCON0_INT_ENABLE   (1 << 0)

Definition at line 1117 of file dp.h.

◆ EXYNOS_VIDINTCON0_INT_MASK

#define EXYNOS_VIDINTCON0_INT_MASK   (1 << 0)

Definition at line 1118 of file dp.h.

◆ EXYNOS_VIDINTCON0_INTFIFO_DISABLE

#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE   (0 << 1)

Definition at line 1114 of file dp.h.

◆ EXYNOS_VIDINTCON0_INTFIFO_ENABLE

#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE   (1 << 1)

Definition at line 1115 of file dp.h.

◆ EXYNOS_VIDINTCON0_INTFRMEN_DISABLE

#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE   (0 << 12)

Definition at line 1099 of file dp.h.

◆ EXYNOS_VIDINTCON0_INTFRMEN_ENABLE

#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE   (1 << 12)

Definition at line 1100 of file dp.h.

◆ EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE

#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE   (0 << 17)

Definition at line 1088 of file dp.h.

◆ EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE

#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE   (1 << 17)

Definition at line 1089 of file dp.h.

◆ EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE

#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE   (0 << 19)

Definition at line 1084 of file dp.h.

◆ EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE

#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE   (1 << 19)

Definition at line 1085 of file dp.h.

◆ EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE

#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE   (0 << 18)

Definition at line 1086 of file dp.h.

◆ EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE

#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE   (1 << 18)

Definition at line 1087 of file dp.h.

◆ EXYNOS_VIDINTCON1_INTFIFOPEND

#define EXYNOS_VIDINTCON1_INTFIFOPEND   (1 << 0)

Definition at line 1124 of file dp.h.

◆ EXYNOS_VIDINTCON1_INTFRMPEND

#define EXYNOS_VIDINTCON1_INTFRMPEND   (1 << 1)

Definition at line 1123 of file dp.h.

◆ EXYNOS_VIDINTCON1_INTI80PEND

#define EXYNOS_VIDINTCON1_INTI80PEND   (1 << 2)

Definition at line 1122 of file dp.h.

◆ EXYNOS_VIDINTCON1_INTVPPEND

#define EXYNOS_VIDINTCON1_INTVPPEND   (1 << 5)

Definition at line 1121 of file dp.h.

◆ EXYNOS_VIDOSD

#define EXYNOS_VIDOSD (   x)    (x * 4)

Definition at line 877 of file dp.h.

◆ EXYNOS_VIDOSD_ALPHA0_B

#define EXYNOS_VIDOSD_ALPHA0_B (   x)    (((x) & 0xf) << 12)

Definition at line 1060 of file dp.h.

◆ EXYNOS_VIDOSD_ALPHA0_G

#define EXYNOS_VIDOSD_ALPHA0_G (   x)    (((x) & 0xf) << 16)

Definition at line 1059 of file dp.h.

◆ EXYNOS_VIDOSD_ALPHA0_R

#define EXYNOS_VIDOSD_ALPHA0_R (   x)    (((x) & 0xf) << 20)

Definition at line 1058 of file dp.h.

◆ EXYNOS_VIDOSD_ALPHA0_SHIFT

#define EXYNOS_VIDOSD_ALPHA0_SHIFT   (12)

Definition at line 1064 of file dp.h.

◆ EXYNOS_VIDOSD_ALPHA1_B

#define EXYNOS_VIDOSD_ALPHA1_B (   x)    (((x) & 0xf) << 0)

Definition at line 1063 of file dp.h.

◆ EXYNOS_VIDOSD_ALPHA1_G

#define EXYNOS_VIDOSD_ALPHA1_G (   x)    (((x) & 0xf) << 4)

Definition at line 1062 of file dp.h.

◆ EXYNOS_VIDOSD_ALPHA1_R

#define EXYNOS_VIDOSD_ALPHA1_R (   x)    (((x) & 0xf) << 8)

Definition at line 1061 of file dp.h.

◆ EXYNOS_VIDOSD_ALPHA1_SHIFT

#define EXYNOS_VIDOSD_ALPHA1_SHIFT   (0)

Definition at line 1065 of file dp.h.

◆ EXYNOS_VIDOSD_BOTTOM_Y

#define EXYNOS_VIDOSD_BOTTOM_Y (   x)    (((x) & 0x7ff) << 0)

Definition at line 1050 of file dp.h.

◆ EXYNOS_VIDOSD_BOTTOM_Y_E

#define EXYNOS_VIDOSD_BOTTOM_Y_E (   x)    (((x) & 0x1) << 22)

Definition at line 1052 of file dp.h.

◆ EXYNOS_VIDOSD_LEFT_X

#define EXYNOS_VIDOSD_LEFT_X (   x)    (((x) & 0x7ff) << 11)

Definition at line 1047 of file dp.h.

◆ EXYNOS_VIDOSD_RIGHT_X

#define EXYNOS_VIDOSD_RIGHT_X (   x)    (((x) & 0x7ff) << 11)

Definition at line 1049 of file dp.h.

◆ EXYNOS_VIDOSD_RIGHT_X_E

#define EXYNOS_VIDOSD_RIGHT_X_E (   x)    (((x) & 0x1) << 23)

Definition at line 1051 of file dp.h.

◆ EXYNOS_VIDOSD_SIZE

#define EXYNOS_VIDOSD_SIZE (   x)    (((x) & 0xffffff) << 0)

Definition at line 1055 of file dp.h.

◆ EXYNOS_VIDOSD_TOP_Y

#define EXYNOS_VIDOSD_TOP_Y (   x)    (((x) & 0x7ff) << 0)

Definition at line 1048 of file dp.h.

◆ EXYNOS_VIDTCON0_VBPD

#define EXYNOS_VIDTCON0_VBPD (   x)    (((x) & 0xff) << 16)

Definition at line 959 of file dp.h.

◆ EXYNOS_VIDTCON0_VBPDE

#define EXYNOS_VIDTCON0_VBPDE (   x)    (((x) & 0xff) << 24)

Definition at line 958 of file dp.h.

◆ EXYNOS_VIDTCON0_VFPD

#define EXYNOS_VIDTCON0_VFPD (   x)    (((x) & 0xff) << 8)

Definition at line 960 of file dp.h.

◆ EXYNOS_VIDTCON0_VSPW

#define EXYNOS_VIDTCON0_VSPW (   x)    (((x) & 0xff) << 0)

Definition at line 961 of file dp.h.

◆ EXYNOS_VIDTCON1_HBPD

#define EXYNOS_VIDTCON1_HBPD (   x)    (((x) & 0xff) << 16)

Definition at line 965 of file dp.h.

◆ EXYNOS_VIDTCON1_HFPD

#define EXYNOS_VIDTCON1_HFPD (   x)    (((x) & 0xff) << 8)

Definition at line 966 of file dp.h.

◆ EXYNOS_VIDTCON1_HSPW

#define EXYNOS_VIDTCON1_HSPW (   x)    (((x) & 0xff) << 0)

Definition at line 967 of file dp.h.

◆ EXYNOS_VIDTCON1_VFPDE

#define EXYNOS_VIDTCON1_VFPDE (   x)    (((x) & 0xff) << 24)

Definition at line 964 of file dp.h.

◆ EXYNOS_VIDTCON2_HOZVAL

#define EXYNOS_VIDTCON2_HOZVAL (   x)    (((x) & 0x7ff) << 0)

Definition at line 971 of file dp.h.

◆ EXYNOS_VIDTCON2_HOZVAL_E

#define EXYNOS_VIDTCON2_HOZVAL_E (   x)    ((((x) & 0x800) >> 11) << 22)

Definition at line 973 of file dp.h.

◆ EXYNOS_VIDTCON2_LINEVAL

#define EXYNOS_VIDTCON2_LINEVAL (   x)    (((x) & 0x7ff) << 11)

Definition at line 970 of file dp.h.

◆ EXYNOS_VIDTCON2_LINEVAL_E

#define EXYNOS_VIDTCON2_LINEVAL_E (   x)    ((((x) & 0x800) >> 11) << 23)

Definition at line 972 of file dp.h.

◆ EXYNOS_WINCON

#define EXYNOS_WINCON (   x)    (x)

Definition at line 876 of file dp.h.

◆ EXYNOS_WINCON1_LOCALSEL_FIMC1

#define EXYNOS_WINCON1_LOCALSEL_FIMC1   (0 << 23)

Definition at line 1035 of file dp.h.

◆ EXYNOS_WINCON1_LOCALSEL_MASK

#define EXYNOS_WINCON1_LOCALSEL_MASK   (1 << 23)

Definition at line 1037 of file dp.h.

◆ EXYNOS_WINCON1_LOCALSEL_VP

#define EXYNOS_WINCON1_LOCALSEL_VP   (1 << 23)

Definition at line 1036 of file dp.h.

◆ EXYNOS_WINCON1_VP_DISABLE

#define EXYNOS_WINCON1_VP_DISABLE   (0 << 24)

Definition at line 1033 of file dp.h.

◆ EXYNOS_WINCON1_VP_ENABLE

#define EXYNOS_WINCON1_VP_ENABLE   (1 << 24)

Definition at line 1034 of file dp.h.

◆ EXYNOS_WINCON_ALPHA0_SEL

#define EXYNOS_WINCON_ALPHA0_SEL   (0 << 1)

Definition at line 1026 of file dp.h.

◆ EXYNOS_WINCON_ALPHA1_SEL

#define EXYNOS_WINCON_ALPHA1_SEL   (1 << 1)

Definition at line 1027 of file dp.h.

◆ EXYNOS_WINCON_ALPHA_MULTI_DISABLE

#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE   (0 << 7)

Definition at line 1005 of file dp.h.

◆ EXYNOS_WINCON_ALPHA_MULTI_ENABLE

#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE   (1 << 7)

Definition at line 1006 of file dp.h.

◆ EXYNOS_WINCON_ALPHA_SEL_MASK

#define EXYNOS_WINCON_ALPHA_SEL_MASK   (1 << 1)

Definition at line 1028 of file dp.h.

◆ EXYNOS_WINCON_BITSWP_DISABLE

#define EXYNOS_WINCON_BITSWP_DISABLE   (0 << 18)

Definition at line 986 of file dp.h.

◆ EXYNOS_WINCON_BITSWP_ENABLE

#define EXYNOS_WINCON_BITSWP_ENABLE   (1 << 18)

Definition at line 987 of file dp.h.

◆ EXYNOS_WINCON_BITSWP_SHIFT

#define EXYNOS_WINCON_BITSWP_SHIFT   (18)

Definition at line 988 of file dp.h.

◆ EXYNOS_WINCON_BLD_MASK

#define EXYNOS_WINCON_BLD_MASK   (1 << 6)

Definition at line 1009 of file dp.h.

◆ EXYNOS_WINCON_BLD_PIXEL

#define EXYNOS_WINCON_BLD_PIXEL   (1 << 6)

Definition at line 1008 of file dp.h.

◆ EXYNOS_WINCON_BLD_PLANE

#define EXYNOS_WINCON_BLD_PLANE   (0 << 6)

Definition at line 1007 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_15BPP_555

#define EXYNOS_WINCON_BPPMODE_15BPP_555   (0xf << 2)

Definition at line 1023 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_16BPP_565

#define EXYNOS_WINCON_BPPMODE_16BPP_565   (5 << 2)

Definition at line 1015 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_16BPP_A444

#define EXYNOS_WINCON_BPPMODE_16BPP_A444   (0xe << 2)

Definition at line 1022 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_16BPP_A555

#define EXYNOS_WINCON_BPPMODE_16BPP_A555   (6 << 2)

Definition at line 1016 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_18BPP_666

#define EXYNOS_WINCON_BPPMODE_18BPP_666   (8 << 2)

Definition at line 1017 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_18BPP_A665

#define EXYNOS_WINCON_BPPMODE_18BPP_A665   (9 << 2)

Definition at line 1018 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_1BPP

#define EXYNOS_WINCON_BPPMODE_1BPP   (0 << 2)

Definition at line 1010 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_24BPP_888

#define EXYNOS_WINCON_BPPMODE_24BPP_888   (0xb << 2)

Definition at line 1019 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_24BPP_A887

#define EXYNOS_WINCON_BPPMODE_24BPP_A887   (0xc << 2)

Definition at line 1020 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_2BPP

#define EXYNOS_WINCON_BPPMODE_2BPP   (1 << 2)

Definition at line 1011 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_32BPP

#define EXYNOS_WINCON_BPPMODE_32BPP   (0xd << 2)

Definition at line 1021 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_4BPP

#define EXYNOS_WINCON_BPPMODE_4BPP   (2 << 2)

Definition at line 1012 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_8BPP

#define EXYNOS_WINCON_BPPMODE_8BPP   (4 << 2)

Definition at line 1014 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_8BPP_PAL

#define EXYNOS_WINCON_BPPMODE_8BPP_PAL   (3 << 2)

Definition at line 1013 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_MASK

#define EXYNOS_WINCON_BPPMODE_MASK   (0xf << 2)

Definition at line 1024 of file dp.h.

◆ EXYNOS_WINCON_BPPMODE_SHIFT

#define EXYNOS_WINCON_BPPMODE_SHIFT   (2)

Definition at line 1025 of file dp.h.

◆ EXYNOS_WINCON_BUFAUTO_DISABLE

#define EXYNOS_WINCON_BUFAUTO_DISABLE   (0 << 19)

Definition at line 983 of file dp.h.

◆ EXYNOS_WINCON_BUFAUTO_ENABLE

#define EXYNOS_WINCON_BUFAUTO_ENABLE   (1 << 19)

Definition at line 984 of file dp.h.

◆ EXYNOS_WINCON_BUFAUTO_MASK

#define EXYNOS_WINCON_BUFAUTO_MASK   (1 << 19)

Definition at line 985 of file dp.h.

◆ EXYNOS_WINCON_BUFSEL_0

#define EXYNOS_WINCON_BUFSEL_0   (0 << 20)

Definition at line 979 of file dp.h.

◆ EXYNOS_WINCON_BUFSEL_1

#define EXYNOS_WINCON_BUFSEL_1   (1 << 20)

Definition at line 980 of file dp.h.

◆ EXYNOS_WINCON_BUFSEL_MASK

#define EXYNOS_WINCON_BUFSEL_MASK   (1 << 20)

Definition at line 981 of file dp.h.

◆ EXYNOS_WINCON_BUFSEL_SHIFT

#define EXYNOS_WINCON_BUFSEL_SHIFT   (20)

Definition at line 982 of file dp.h.

◆ EXYNOS_WINCON_BURSTLEN_16WORD

#define EXYNOS_WINCON_BURSTLEN_16WORD   (0 << 9)

Definition at line 1001 of file dp.h.

◆ EXYNOS_WINCON_BURSTLEN_4WORD

#define EXYNOS_WINCON_BURSTLEN_4WORD   (2 << 9)

Definition at line 1003 of file dp.h.

◆ EXYNOS_WINCON_BURSTLEN_8WORD

#define EXYNOS_WINCON_BURSTLEN_8WORD   (1 << 9)

Definition at line 1002 of file dp.h.

◆ EXYNOS_WINCON_BURSTLEN_MASK

#define EXYNOS_WINCON_BURSTLEN_MASK   (3 << 9)

Definition at line 1004 of file dp.h.

◆ EXYNOS_WINCON_BYTESWP_DISABLE

#define EXYNOS_WINCON_BYTESWP_DISABLE   (0 << 17)

Definition at line 989 of file dp.h.

◆ EXYNOS_WINCON_BYTESWP_ENABLE

#define EXYNOS_WINCON_BYTESWP_ENABLE   (1 << 17)

Definition at line 990 of file dp.h.

◆ EXYNOS_WINCON_BYTESWP_SHIFT

#define EXYNOS_WINCON_BYTESWP_SHIFT   (17)

Definition at line 991 of file dp.h.

◆ EXYNOS_WINCON_DATAPATH_DMA

#define EXYNOS_WINCON_DATAPATH_DMA   (0 << 22)

Definition at line 976 of file dp.h.

◆ EXYNOS_WINCON_DATAPATH_LOCAL

#define EXYNOS_WINCON_DATAPATH_LOCAL   (1 << 22)

Definition at line 977 of file dp.h.

◆ EXYNOS_WINCON_DATAPATH_MASK

#define EXYNOS_WINCON_DATAPATH_MASK   (1 << 22)

Definition at line 978 of file dp.h.

◆ EXYNOS_WINCON_ENWIN_DISABLE

#define EXYNOS_WINCON_ENWIN_DISABLE   (0 << 0)

Definition at line 1029 of file dp.h.

◆ EXYNOS_WINCON_ENWIN_ENABLE

#define EXYNOS_WINCON_ENWIN_ENABLE   (1 << 0)

Definition at line 1030 of file dp.h.

◆ EXYNOS_WINCON_HAWSWP_DISABLE

#define EXYNOS_WINCON_HAWSWP_DISABLE   (0 << 16)

Definition at line 992 of file dp.h.

◆ EXYNOS_WINCON_HAWSWP_ENABLE

#define EXYNOS_WINCON_HAWSWP_ENABLE   (1 << 16)

Definition at line 993 of file dp.h.

◆ EXYNOS_WINCON_HAWSWP_SHIFT

#define EXYNOS_WINCON_HAWSWP_SHIFT   (16)

Definition at line 994 of file dp.h.

◆ EXYNOS_WINCON_INRGB_MASK

#define EXYNOS_WINCON_INRGB_MASK   (1 << 13)

Definition at line 1000 of file dp.h.

◆ EXYNOS_WINCON_INRGB_RGB

#define EXYNOS_WINCON_INRGB_RGB   (0 << 13)

Definition at line 998 of file dp.h.

◆ EXYNOS_WINCON_INRGB_YUV

#define EXYNOS_WINCON_INRGB_YUV   (1 << 13)

Definition at line 999 of file dp.h.

◆ EXYNOS_WINCON_WSWP_DISABLE

#define EXYNOS_WINCON_WSWP_DISABLE   (0 << 15)

Definition at line 995 of file dp.h.

◆ EXYNOS_WINCON_WSWP_ENABLE

#define EXYNOS_WINCON_WSWP_ENABLE   (1 << 15)

Definition at line 996 of file dp.h.

◆ EXYNOS_WINCON_WSWP_SHIFT

#define EXYNOS_WINCON_WSWP_SHIFT   (15)

Definition at line 997 of file dp.h.

◆ EXYNOS_WINMAP_COLOR

#define EXYNOS_WINMAP_COLOR (   x)    ((x) & 0xffffff)

Definition at line 1081 of file dp.h.

◆ EXYNOS_WINMAP_ENABLE

#define EXYNOS_WINMAP_ENABLE   (1 << 24)

Definition at line 1127 of file dp.h.

◆ EXYNOS_WINSHMAP_CH_DISABLE

#define EXYNOS_WINSHMAP_CH_DISABLE (   x)    (1 << (x))

Definition at line 1042 of file dp.h.

◆ EXYNOS_WINSHMAP_CH_ENABLE

#define EXYNOS_WINSHMAP_CH_ENABLE (   x)    (1 << (x))

Definition at line 1041 of file dp.h.

◆ EXYNOS_WINSHMAP_LOCAL_DISABLE

#define EXYNOS_WINSHMAP_LOCAL_DISABLE (   x)    (0x20 << (x))

Definition at line 1044 of file dp.h.

◆ EXYNOS_WINSHMAP_LOCAL_ENABLE

#define EXYNOS_WINSHMAP_LOCAL_ENABLE (   x)    (0x20 << (x))

Definition at line 1043 of file dp.h.

◆ EXYNOS_WINSHMAP_PROTECT

#define EXYNOS_WINSHMAP_PROTECT (   x)    (((x) & 0x1f) << 10)

Definition at line 1040 of file dp.h.

◆ F_HPD [1/2]

#define F_HPD   (0x1 << 5)

Definition at line 586 of file dp.h.

◆ F_HPD [2/2]

#define F_HPD   (0x1 << 5)

Definition at line 586 of file dp.h.

◆ F_PLL_LOCK

#define F_PLL_LOCK   (0x1 << 3)

Definition at line 307 of file dp.h.

◆ F_VALID [1/2]

#define F_VALID   (0x1 << 1)

Definition at line 590 of file dp.h.

◆ F_VALID [2/2]

#define F_VALID   (0x1 << 1)

Definition at line 590 of file dp.h.

◆ FIX_M_AUD

#define FIX_M_AUD   (0x1 << 4)

Definition at line 594 of file dp.h.

◆ FIX_M_VID

#define FIX_M_VID   (0x1 << 2)

Definition at line 596 of file dp.h.

◆ FORCE_CHA

#define FORCE_CHA   (0x1 << 1)

Definition at line 581 of file dp.h.

◆ FORCE_DET

#define FORCE_DET   (0x1 << 1)

Definition at line 575 of file dp.h.

◆ FORMAT_SEL

#define FORMAT_SEL   (0x1 << 4)

Definition at line 505 of file dp.h.

◆ H_B_PORCH_CFG_H

#define H_B_PORCH_CFG_H (   x)    ((((x) >> 8)) & 0xff)

Definition at line 426 of file dp.h.

◆ H_B_PORCH_CFG_L

#define H_B_PORCH_CFG_L (   x)    ((x) & 0xff)

Definition at line 425 of file dp.h.

◆ H_F_PORCH_CFG_H

#define H_F_PORCH_CFG_H (   x)    ((((x) >> 8)) & 0xff)

Definition at line 422 of file dp.h.

◆ H_F_PORCH_CFG_L

#define H_F_PORCH_CFG_L (   x)    ((x) & 0xff)

Definition at line 421 of file dp.h.

◆ H_S_POLARITY_CFG_SHIFT

#define H_S_POLARITY_CFG_SHIFT   (0)

Definition at line 511 of file dp.h.

◆ H_SYNC_PORCH_CFG_H

#define H_SYNC_PORCH_CFG_H (   x)    ((((x) >> 8)) & 0xff)

Definition at line 424 of file dp.h.

◆ H_SYNC_PORCH_CFG_L

#define H_SYNC_PORCH_CFG_L (   x)    ((x) & 0xff)

Definition at line 423 of file dp.h.

◆ HDCP_FUNC_EN_N

#define HDCP_FUNC_EN_N   (0x1 << 2)

Definition at line 277 of file dp.h.

◆ HDCP_RDY [1/2]

#define HDCP_RDY   (0x1 << 3)

Definition at line 588 of file dp.h.

◆ HDCP_RDY [2/2]

#define HDCP_RDY   (0x1 << 3)

Definition at line 588 of file dp.h.

◆ HDCP_VIDEO_MUTE

#define HDCP_VIDEO_MUTE   (0x1 << 6)

Definition at line 525 of file dp.h.

◆ HOTPLUG_CHG

#define HOTPLUG_CHG   (0x1 << 2)

Definition at line 320 of file dp.h.

◆ HPD_CTRL [1/2]

#define HPD_CTRL   (0x1 << 4)

Definition at line 587 of file dp.h.

◆ HPD_CTRL [2/2]

#define HPD_CTRL   (0x1 << 4)

Definition at line 587 of file dp.h.

◆ HPD_LOST

#define HPD_LOST   (0x1 << 1)

Definition at line 321 of file dp.h.

◆ HPD_STATUS [1/2]

#define HPD_STATUS   (0x1 << 6)

Definition at line 585 of file dp.h.

◆ HPD_STATUS [2/2]

#define HPD_STATUS   (0x1 << 6)

Definition at line 585 of file dp.h.

◆ HSYNC_POLARITY_CFG

#define HSYNC_POLARITY_CFG   (0x1 << 0)

Definition at line 510 of file dp.h.

◆ HW_LINK_TRAINING_PATTERN

#define HW_LINK_TRAINING_PATTERN   (0x1 << 8)

Definition at line 399 of file dp.h.

◆ HW_TRAINING_FINISH

#define HW_TRAINING_FINISH   (0x1 << 5)

Definition at line 326 of file dp.h.

◆ I2C_E_EDID_DEVICE_ADDR

#define I2C_E_EDID_DEVICE_ADDR   (0x30)

Definition at line 645 of file dp.h.

◆ I2C_EDID_DEVICE_ADDR

#define I2C_EDID_DEVICE_ADDR   (0x50)

Definition at line 644 of file dp.h.

◆ IN_BPC_10_BITS

#define IN_BPC_10_BITS   (0x2 << 4)

Definition at line 535 of file dp.h.

◆ IN_BPC_12_BITS

#define IN_BPC_12_BITS   (0x3 << 4)

Definition at line 534 of file dp.h.

◆ IN_BPC_6_BITS

#define IN_BPC_6_BITS   (0x0 << 4)

Definition at line 537 of file dp.h.

◆ IN_BPC_8_BITS

#define IN_BPC_8_BITS   (0x1 << 4)

Definition at line 536 of file dp.h.

◆ IN_BPC_MASK

#define IN_BPC_MASK   (0x7 << 4)

Definition at line 532 of file dp.h.

◆ IN_BPC_SHIFT

#define IN_BPC_SHIFT   (4)

Definition at line 533 of file dp.h.

◆ IN_COLOR_F_MASK

#define IN_COLOR_F_MASK   (0x3 << 0)

Definition at line 538 of file dp.h.

◆ IN_COLOR_F_RGB

#define IN_COLOR_F_RGB   (0x0 << 0)

Definition at line 542 of file dp.h.

◆ IN_COLOR_F_SHIFT

#define IN_COLOR_F_SHIFT   (0)

Definition at line 539 of file dp.h.

◆ IN_COLOR_F_YCBCR422

#define IN_COLOR_F_YCBCR422   (0x1 << 0)

Definition at line 541 of file dp.h.

◆ IN_COLOR_F_YCBCR444

#define IN_COLOR_F_YCBCR444   (0x2 << 0)

Definition at line 540 of file dp.h.

◆ IN_D_RANGE_CEA

#define IN_D_RANGE_CEA   (0x1 << 7)

Definition at line 530 of file dp.h.

◆ IN_D_RANGE_MASK

#define IN_D_RANGE_MASK   (0x1 << 7)

Definition at line 528 of file dp.h.

◆ IN_D_RANGE_SHIFT

#define IN_D_RANGE_SHIFT   (7)

Definition at line 529 of file dp.h.

◆ IN_D_RANGE_VESA

#define IN_D_RANGE_VESA   (0x0 << 7)

Definition at line 531 of file dp.h.

◆ IN_YC_COEFFI_ITU601

#define IN_YC_COEFFI_ITU601   (0x0 << 7)

Definition at line 548 of file dp.h.

◆ IN_YC_COEFFI_ITU709

#define IN_YC_COEFFI_ITU709   (0x1 << 7)

Definition at line 547 of file dp.h.

◆ IN_YC_COEFFI_MASK

#define IN_YC_COEFFI_MASK   (0x1 << 7)

Definition at line 545 of file dp.h.

◆ IN_YC_COEFFI_SHIFT

#define IN_YC_COEFFI_SHIFT   (7)

Definition at line 546 of file dp.h.

◆ INT_HPD

#define INT_HPD   (0x1 << 6)

Definition at line 325 of file dp.h.

◆ INT_POL

#define INT_POL   (0x1 << 0)

Definition at line 267 of file dp.h.

◆ INT_STA_MASK

#define INT_STA_MASK   (0)

Definition at line 356 of file dp.h.

◆ INTERACE_SCAN_CFG

#define INTERACE_SCAN_CFG   (0x1 << 2)

Definition at line 506 of file dp.h.

◆ INTERACE_SCAN_CFG_SHIFT

#define INTERACE_SCAN_CFG_SHIFT   (2)

Definition at line 507 of file dp.h.

◆ LINK_QUAL_PATTERN_SET_D10_2

#define LINK_QUAL_PATTERN_SET_D10_2   (0x1 << 2)

Definition at line 404 of file dp.h.

◆ LINK_QUAL_PATTERN_SET_DISABLE

#define LINK_QUAL_PATTERN_SET_DISABLE   (0x0 << 2)

Definition at line 405 of file dp.h.

◆ LINK_QUAL_PATTERN_SET_MASK

#define LINK_QUAL_PATTERN_SET_MASK   (0x3 << 2)

Definition at line 402 of file dp.h.

◆ LINK_QUAL_PATTERN_SET_PRBS7

#define LINK_QUAL_PATTERN_SET_PRBS7   (0x3 << 2)

Definition at line 403 of file dp.h.

◆ LS_CLK_DOMAIN_FUNC_EN_N [1/2]

#define LS_CLK_DOMAIN_FUNC_EN_N   (0x1 << 0)

Definition at line 314 of file dp.h.

◆ LS_CLK_DOMAIN_FUNC_EN_N [2/2]

#define LS_CLK_DOMAIN_FUNC_EN_N   (0x1 << 0)

Definition at line 314 of file dp.h.

◆ M_VID0_CFG

#define M_VID0_CFG (   x)    ((x) & 0xff)

Definition at line 600 of file dp.h.

◆ M_VID1_CFG

#define M_VID1_CFG (   x)    (((x) >> 8) & 0xff)

Definition at line 601 of file dp.h.

◆ M_VID2_CFG

#define M_VID2_CFG (   x)    (((x) >> 16) & 0xff)

Definition at line 602 of file dp.h.

◆ M_VID_UPDATE_CTRL

#define M_VID_UPDATE_CTRL   (0x3 << 0)

Definition at line 597 of file dp.h.

◆ MACRO_RST

#define MACRO_RST   (0x1 << 5)

Definition at line 393 of file dp.h.

◆ MASTER_VID_FUNC_EN_N

#define MASTER_VID_FUNC_EN_N   (0x1 << 7)

Definition at line 273 of file dp.h.

◆ MASTER_VIDEO_INTERLACE_EN

#define MASTER_VIDEO_INTERLACE_EN   (0x1 << 4)

Definition at line 516 of file dp.h.

◆ MAX_CR_LOOP

#define MAX_CR_LOOP   5

Definition at line 1174 of file dp.h.

◆ MAX_DRIVE_CURRENT_REACH_0

#define MAX_DRIVE_CURRENT_REACH_0   (0x1 << 2)

Definition at line 438 of file dp.h.

◆ MAX_DRIVE_CURRENT_REACH_1

#define MAX_DRIVE_CURRENT_REACH_1   (0x1 << 2)

Definition at line 457 of file dp.h.

◆ MAX_DRIVE_CURRENT_REACH_2

#define MAX_DRIVE_CURRENT_REACH_2   (0x1 << 2)

Definition at line 476 of file dp.h.

◆ MAX_DRIVE_CURRENT_REACH_3

#define MAX_DRIVE_CURRENT_REACH_3   (0x1 << 2)

Definition at line 495 of file dp.h.

◆ MAX_EQ_LOOP

#define MAX_EQ_LOOP   4

Definition at line 1175 of file dp.h.

◆ MAX_PRE_EMPHASIS_REACH_0

#define MAX_PRE_EMPHASIS_REACH_0   (0x1 << 5)

Definition at line 429 of file dp.h.

◆ MAX_PRE_EMPHASIS_REACH_1

#define MAX_PRE_EMPHASIS_REACH_1   (0x1 << 5)

Definition at line 448 of file dp.h.

◆ MAX_PRE_EMPHASIS_REACH_2

#define MAX_PRE_EMPHASIS_REACH_2   (0x1 << 5)

Definition at line 467 of file dp.h.

◆ MAX_PRE_EMPHASIS_REACH_3

#define MAX_PRE_EMPHASIS_REACH_3   (0x1 << 5)

Definition at line 486 of file dp.h.

◆ N_VID0_CFG

#define N_VID0_CFG (   x)    ((x) & 0xff)

Definition at line 605 of file dp.h.

◆ N_VID1_CFG

#define N_VID1_CFG (   x)    (((x) >> 8) & 0xff)

Definition at line 606 of file dp.h.

◆ N_VID2_CFG

#define N_VID2_CFG (   x)    (((x) >> 16) & 0xff)

Definition at line 607 of file dp.h.

◆ PD_RING_OSC

#define PD_RING_OSC   (0x1 << 6)

Definition at line 239 of file dp.h.

◆ PHY_PD

#define PHY_PD   (0x1 << 5)

Definition at line 288 of file dp.h.

◆ PLL_LOCK

#define PLL_LOCK   (0x1 << 4)

Definition at line 306 of file dp.h.

◆ PLL_LOCK_CHG

#define PLL_LOCK_CHG   (0x1 << 6)

Definition at line 297 of file dp.h.

◆ PLL_LOCK_CTRL

#define PLL_LOCK_CTRL   (0x1 << 2)

Definition at line 308 of file dp.h.

◆ PLUG

#define PLUG   (0x1 << 0)

Definition at line 322 of file dp.h.

◆ PRE_EMPHASIS_SET_0_GET

#define PRE_EMPHASIS_SET_0_GET (   x)    (((x) >> 3) & 0x3)

Definition at line 431 of file dp.h.

◆ PRE_EMPHASIS_SET_0_LEVEL_0

#define PRE_EMPHASIS_SET_0_LEVEL_0   (0x0 << 3)

Definition at line 437 of file dp.h.

◆ PRE_EMPHASIS_SET_0_LEVEL_1

#define PRE_EMPHASIS_SET_0_LEVEL_1   (0x1 << 3)

Definition at line 436 of file dp.h.

◆ PRE_EMPHASIS_SET_0_LEVEL_2

#define PRE_EMPHASIS_SET_0_LEVEL_2   (0x2 << 3)

Definition at line 435 of file dp.h.

◆ PRE_EMPHASIS_SET_0_LEVEL_3

#define PRE_EMPHASIS_SET_0_LEVEL_3   (0x3 << 3)

Definition at line 434 of file dp.h.

◆ PRE_EMPHASIS_SET_0_MASK

#define PRE_EMPHASIS_SET_0_MASK   (0x3 << 3)

Definition at line 432 of file dp.h.

◆ PRE_EMPHASIS_SET_0_SET

#define PRE_EMPHASIS_SET_0_SET (   x)    (((x) & 0x3) << 3)

Definition at line 430 of file dp.h.

◆ PRE_EMPHASIS_SET_0_SHIFT

#define PRE_EMPHASIS_SET_0_SHIFT   (3)

Definition at line 433 of file dp.h.

◆ PRE_EMPHASIS_SET_1_GET

#define PRE_EMPHASIS_SET_1_GET (   x)    (((x) >> 3) & 0x3)

Definition at line 450 of file dp.h.

◆ PRE_EMPHASIS_SET_1_LEVEL_0

#define PRE_EMPHASIS_SET_1_LEVEL_0   (0x0 << 3)

Definition at line 456 of file dp.h.

◆ PRE_EMPHASIS_SET_1_LEVEL_1

#define PRE_EMPHASIS_SET_1_LEVEL_1   (0x1 << 3)

Definition at line 455 of file dp.h.

◆ PRE_EMPHASIS_SET_1_LEVEL_2

#define PRE_EMPHASIS_SET_1_LEVEL_2   (0x2 << 3)

Definition at line 454 of file dp.h.

◆ PRE_EMPHASIS_SET_1_LEVEL_3

#define PRE_EMPHASIS_SET_1_LEVEL_3   (0x3 << 3)

Definition at line 453 of file dp.h.

◆ PRE_EMPHASIS_SET_1_MASK

#define PRE_EMPHASIS_SET_1_MASK   (0x3 << 3)

Definition at line 451 of file dp.h.

◆ PRE_EMPHASIS_SET_1_SET

#define PRE_EMPHASIS_SET_1_SET (   x)    (((x) & 0x3) << 3)

Definition at line 449 of file dp.h.

◆ PRE_EMPHASIS_SET_1_SHIFT

#define PRE_EMPHASIS_SET_1_SHIFT   (3)

Definition at line 452 of file dp.h.

◆ PRE_EMPHASIS_SET_2_GET

#define PRE_EMPHASIS_SET_2_GET (   x)    (((x) >> 3) & 0x3)

Definition at line 469 of file dp.h.

◆ PRE_EMPHASIS_SET_2_LEVEL_0

#define PRE_EMPHASIS_SET_2_LEVEL_0   (0x0 << 3)

Definition at line 475 of file dp.h.

◆ PRE_EMPHASIS_SET_2_LEVEL_1

#define PRE_EMPHASIS_SET_2_LEVEL_1   (0x1 << 3)

Definition at line 474 of file dp.h.

◆ PRE_EMPHASIS_SET_2_LEVEL_2

#define PRE_EMPHASIS_SET_2_LEVEL_2   (0x2 << 3)

Definition at line 473 of file dp.h.

◆ PRE_EMPHASIS_SET_2_LEVEL_3

#define PRE_EMPHASIS_SET_2_LEVEL_3   (0x3 << 3)

Definition at line 472 of file dp.h.

◆ PRE_EMPHASIS_SET_2_MASK

#define PRE_EMPHASIS_SET_2_MASK   (0x3 << 3)

Definition at line 470 of file dp.h.

◆ PRE_EMPHASIS_SET_2_SET

#define PRE_EMPHASIS_SET_2_SET (   x)    (((x) & 0x3) << 3)

Definition at line 468 of file dp.h.

◆ PRE_EMPHASIS_SET_2_SHIFT

#define PRE_EMPHASIS_SET_2_SHIFT   (3)

Definition at line 471 of file dp.h.

◆ PRE_EMPHASIS_SET_3_GET

#define PRE_EMPHASIS_SET_3_GET (   x)    (((x) >> 3) & 0x3)

Definition at line 488 of file dp.h.

◆ PRE_EMPHASIS_SET_3_LEVEL_0

#define PRE_EMPHASIS_SET_3_LEVEL_0   (0x0 << 3)

Definition at line 494 of file dp.h.

◆ PRE_EMPHASIS_SET_3_LEVEL_1

#define PRE_EMPHASIS_SET_3_LEVEL_1   (0x1 << 3)

Definition at line 493 of file dp.h.

◆ PRE_EMPHASIS_SET_3_LEVEL_2

#define PRE_EMPHASIS_SET_3_LEVEL_2   (0x2 << 3)

Definition at line 492 of file dp.h.

◆ PRE_EMPHASIS_SET_3_LEVEL_3

#define PRE_EMPHASIS_SET_3_LEVEL_3   (0x3 << 3)

Definition at line 491 of file dp.h.

◆ PRE_EMPHASIS_SET_3_MASK

#define PRE_EMPHASIS_SET_3_MASK   (0x3 << 3)

Definition at line 489 of file dp.h.

◆ PRE_EMPHASIS_SET_3_SET

#define PRE_EMPHASIS_SET_3_SET (   x)    (((x) & 0x3) << 3)

Definition at line 487 of file dp.h.

◆ PRE_EMPHASIS_SET_3_SHIFT

#define PRE_EMPHASIS_SET_3_SHIFT   (3)

Definition at line 490 of file dp.h.

◆ PSR_ACTIVE

#define PSR_ACTIVE   (0x1 << 7)

Definition at line 317 of file dp.h.

◆ PSR_INACTIVE

#define PSR_INACTIVE   (0x1 << 6)

Definition at line 318 of file dp.h.

◆ RESET_DP_TX

#define RESET_DP_TX   (0x01 << 0)

Definition at line 270 of file dp.h.

◆ RPLY_RECEIV

#define RPLY_RECEIV   (0x1 << 1)

Definition at line 327 of file dp.h.

◆ SCRAMBLER_TYPE

#define SCRAMBLER_TYPE   (0x1 << 9)

Definition at line 398 of file dp.h.

◆ SCRAMBLING_DISABLE

#define SCRAMBLING_DISABLE   (0x1 << 5)

Definition at line 400 of file dp.h.

◆ SCRAMBLING_ENABLE

#define SCRAMBLING_ENABLE   (0x0 << 5)

Definition at line 401 of file dp.h.

◆ SEL_24M

#define SEL_24M   (0x1 << 3)

Definition at line 219 of file dp.h.

◆ SEL_BG_INTERNAL_RESISTOR

#define SEL_BG_INTERNAL_RESISTOR   (0x1 << 6)

Definition at line 209 of file dp.h.

◆ SEL_BG_NEW_BANDGAP

#define SEL_BG_NEW_BANDGAP   (0x0 << 6)

Definition at line 208 of file dp.h.

◆ SEL_CURRENT_DEFAULT

#define SEL_CURRENT_DEFAULT   (0x0 << 3)

Definition at line 228 of file dp.h.

◆ SERDES_FIFO_FUNC_EN_N [1/2]

#define SERDES_FIFO_FUNC_EN_N   (0x1 << 1)

Definition at line 313 of file dp.h.

◆ SERDES_FIFO_FUNC_EN_N [2/2]

#define SERDES_FIFO_FUNC_EN_N   (0x1 << 1)

Definition at line 313 of file dp.h.

◆ SLAVE_VID_FUNC_EN_N

#define SLAVE_VID_FUNC_EN_N   (0x1 << 5)

Definition at line 274 of file dp.h.

◆ SOFT_INT_CTRL

#define SOFT_INT_CTRL   (0x1 << 2)

Definition at line 266 of file dp.h.

◆ SPDIF_BI_PHASE_ERR

#define SPDIF_BI_PHASE_ERR   (0x1 << 5)

Definition at line 319 of file dp.h.

◆ SPDIF_ERR

#define SPDIF_ERR   (0x1 << 5)

Definition at line 298 of file dp.h.

◆ SPDIF_UNSTBL

#define SPDIF_UNSTBL   (0x1 << 4)

Definition at line 299 of file dp.h.

◆ SSC_FUNC_EN_N [1/2]

#define SSC_FUNC_EN_N   (0x1 << 7)

Definition at line 311 of file dp.h.

◆ SSC_FUNC_EN_N [2/2]

#define SSC_FUNC_EN_N   (0x1 << 7)

Definition at line 311 of file dp.h.

◆ STRM_VALID [1/2]

#define STRM_VALID   (0x1 << 2)

Definition at line 589 of file dp.h.

◆ STRM_VALID [2/2]

#define STRM_VALID   (0x1 << 2)

Definition at line 589 of file dp.h.

◆ SW_FUNC_EN_N

#define SW_FUNC_EN_N   (0x1 << 0)

Definition at line 279 of file dp.h.

◆ SW_INT

#define SW_INT   (0x1 << 0)

Definition at line 303 of file dp.h.

◆ SW_TRAINING_PATTERN_SET_MASK

#define SW_TRAINING_PATTERN_SET_MASK   (0x3 << 0)

Definition at line 406 of file dp.h.

◆ SW_TRAINING_PATTERN_SET_NORMAL

#define SW_TRAINING_PATTERN_SET_NORMAL   (0x0 << 0)

Definition at line 409 of file dp.h.

◆ SW_TRAINING_PATTERN_SET_PTN1

#define SW_TRAINING_PATTERN_SET_PTN1   (0x1 << 0)

Definition at line 408 of file dp.h.

◆ SW_TRAINING_PATTERN_SET_PTN2

#define SW_TRAINING_PATTERN_SET_PTN2   (0x2 << 0)

Definition at line 407 of file dp.h.

◆ SWING_A_30PER_G_INCREASE

#define SWING_A_30PER_G_INCREASE   (0x1 << 3)

Definition at line 214 of file dp.h.

◆ SWING_A_30PER_G_NORMAL

#define SWING_A_30PER_G_NORMAL   (0x0 << 3)

Definition at line 215 of file dp.h.

◆ TEST_PATTERN_GEN_DIS

#define TEST_PATTERN_GEN_DIS   (0x0 << 0)

Definition at line 556 of file dp.h.

◆ TEST_PATTERN_GEN_EN

#define TEST_PATTERN_GEN_EN   (0x1 << 0)

Definition at line 555 of file dp.h.

◆ TEST_PATTERN_MODE_BALCK_WHITE_V_LINES

#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES   (0x2 << 0)

Definition at line 560 of file dp.h.

◆ TEST_PATTERN_MODE_COLOR_RAMP

#define TEST_PATTERN_MODE_COLOR_RAMP   (0x1 << 0)

Definition at line 561 of file dp.h.

◆ TEST_PATTERN_MODE_COLOR_SQUARE

#define TEST_PATTERN_MODE_COLOR_SQUARE   (0x3 << 0)

Definition at line 559 of file dp.h.

◆ TOTAL_LINE_CFG_H

#define TOTAL_LINE_CFG_H (   x)    ((((x) >> 8)) & 0xff)

Definition at line 413 of file dp.h.

◆ TOTAL_LINE_CFG_L

#define TOTAL_LINE_CFG_L (   x)    ((x) & 0xff)

Definition at line 412 of file dp.h.

◆ TOTAL_PIXEL_CFG_H

#define TOTAL_PIXEL_CFG_H (   x)    ((((x) >> 8)) & 0xff)

Definition at line 417 of file dp.h.

◆ TOTAL_PIXEL_CFG_L

#define TOTAL_PIXEL_CFG_L (   x)    ((x) & 0xff)

Definition at line 416 of file dp.h.

◆ TX_CUR1_1X

#define TX_CUR1_1X   (0x0 << 2)

Definition at line 244 of file dp.h.

◆ TX_CUR1_2X

#define TX_CUR1_2X   (0x1 << 2)

Definition at line 245 of file dp.h.

◆ TX_CUR1_3X

#define TX_CUR1_3X   (0x2 << 2)

Definition at line 246 of file dp.h.

◆ TX_CUR_1_MA

#define TX_CUR_1_MA   (0x0 << 0)

Definition at line 247 of file dp.h.

◆ TX_CUR_2_MA

#define TX_CUR_2_MA   (0x1 << 0)

Definition at line 248 of file dp.h.

◆ TX_CUR_3_MA

#define TX_CUR_3_MA   (0x2 << 0)

Definition at line 249 of file dp.h.

◆ TX_CUR_4_MA

#define TX_CUR_4_MA   (0x3 << 0)

Definition at line 250 of file dp.h.

◆ TX_DVDD_BIT_1_0000V

#define TX_DVDD_BIT_1_0000V   (0x3 << 0)

Definition at line 220 of file dp.h.

◆ TX_DVDD_BIT_1_0625V

#define TX_DVDD_BIT_1_0625V   (0x4 << 0)

Definition at line 221 of file dp.h.

◆ TX_DVDD_BIT_1_1250V

#define TX_DVDD_BIT_1_1250V   (0x5 << 0)

Definition at line 222 of file dp.h.

◆ TX_TERMINAL_CTRL_45_OHM

#define TX_TERMINAL_CTRL_45_OHM   (0x3 << 4)

Definition at line 213 of file dp.h.

◆ TX_TERMINAL_CTRL_50_OHM

#define TX_TERMINAL_CTRL_50_OHM   (0x2 << 4)

Definition at line 212 of file dp.h.

◆ TX_TERMINAL_CTRL_61_OHM

#define TX_TERMINAL_CTRL_61_OHM   (0x1 << 4)

Definition at line 211 of file dp.h.

◆ TX_TERMINAL_CTRL_73_OHM

#define TX_TERMINAL_CTRL_73_OHM   (0x0 << 4)

Definition at line 210 of file dp.h.

◆ V_S_POLARITY_CFG_SHIFT

#define V_S_POLARITY_CFG_SHIFT   (1)

Definition at line 509 of file dp.h.

◆ VALID_CTRL [1/2]

#define VALID_CTRL   (0x1 << 0)

Definition at line 591 of file dp.h.

◆ VALID_CTRL [2/2]

#define VALID_CTRL   (0x1 << 0)

Definition at line 591 of file dp.h.

◆ VCO_BIT_000_MICRO

#define VCO_BIT_000_MICRO   (0x0 << 0)

Definition at line 229 of file dp.h.

◆ VCO_BIT_200_MICRO

#define VCO_BIT_200_MICRO   (0x1 << 0)

Definition at line 230 of file dp.h.

◆ VCO_BIT_300_MICRO

#define VCO_BIT_300_MICRO   (0x2 << 0)

Definition at line 231 of file dp.h.

◆ VCO_BIT_400_MICRO

#define VCO_BIT_400_MICRO   (0x3 << 0)

Definition at line 232 of file dp.h.

◆ VCO_BIT_500_MICRO

#define VCO_BIT_500_MICRO   (0x4 << 0)

Definition at line 233 of file dp.h.

◆ VCO_BIT_600_MICRO

#define VCO_BIT_600_MICRO   (0x5 << 0)

Definition at line 234 of file dp.h.

◆ VCO_BIT_700_MICRO

#define VCO_BIT_700_MICRO   (0x6 << 0)

Definition at line 235 of file dp.h.

◆ VCO_BIT_900_MICRO

#define VCO_BIT_900_MICRO   (0x7 << 0)

Definition at line 236 of file dp.h.

◆ VID_CHK_UPDATE_TYPE_0

#define VID_CHK_UPDATE_TYPE_0   (0x0 << 4)

Definition at line 552 of file dp.h.

◆ VID_CHK_UPDATE_TYPE_1

#define VID_CHK_UPDATE_TYPE_1   (0x1 << 4)

Definition at line 551 of file dp.h.

◆ VID_CHK_UPDATE_TYPE_MASK

#define VID_CHK_UPDATE_TYPE_MASK   (0x1 << 4)

Definition at line 549 of file dp.h.

◆ VID_CHK_UPDATE_TYPE_SHIFT

#define VID_CHK_UPDATE_TYPE_SHIFT   (4)

Definition at line 550 of file dp.h.

◆ VID_CLK_CHG

#define VID_CLK_CHG   (0x1 << 1)

Definition at line 302 of file dp.h.

◆ VID_FORMAT_CHG

#define VID_FORMAT_CHG   (0x1 << 3)

Definition at line 300 of file dp.h.

◆ VIDEO_BIST_MASK

#define VIDEO_BIST_MASK   (0x1 << 3)

Definition at line 205 of file dp.h.

◆ VIDEO_EN

#define VIDEO_EN   (0x1 << 7)

Definition at line 524 of file dp.h.

◆ VIDEO_EN_MASK

#define VIDEO_EN_MASK   (0x01 << 7)

Definition at line 201 of file dp.h.

◆ VIDEO_MASTER_CLK_SEL

#define VIDEO_MASTER_CLK_SEL   (0x1 << 2)

Definition at line 517 of file dp.h.

◆ VIDEO_MASTER_MODE_EN

#define VIDEO_MASTER_MODE_EN   (0x1 << 1)

Definition at line 518 of file dp.h.

◆ VIDEO_MODE_MASK

#define VIDEO_MODE_MASK   (0x1 << 0)

Definition at line 519 of file dp.h.

◆ VIDEO_MODE_MASTER_MODE

#define VIDEO_MODE_MASTER_MODE   (0x0 << 0)

Definition at line 521 of file dp.h.

◆ VIDEO_MODE_SLAVE_MODE

#define VIDEO_MODE_SLAVE_MODE   (0x1 << 0)

Definition at line 520 of file dp.h.

◆ VIDEO_MUTE_MASK

#define VIDEO_MUTE_MASK   (0x01 << 6)

Definition at line 202 of file dp.h.

◆ VSYNC_DET

#define VSYNC_DET   (0x1 << 7)

Definition at line 296 of file dp.h.

◆ VSYNC_POLARITY_CFG

#define VSYNC_POLARITY_CFG   (0x1 << 1)

Definition at line 508 of file dp.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
DP_DISABLE 
DP_ENABLE 

Definition at line 1179 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
COLOR_RGB 
COLOR_YCBCR422 
COLOR_YCBCR444 

Definition at line 1247 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
VESA 
CEA 

Definition at line 1253 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
COLOR_YCBCR601 
COLOR_YCBCR709 

Definition at line 1258 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
COLOR_6 
COLOR_8 
COLOR_10 
COLOR_12 

Definition at line 1263 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
DP_LANE_BW_1_62 
DP_LANE_BW_2_70 

Definition at line 1270 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
DP_LANE_CNT_1 
DP_LANE_CNT_2 
DP_LANE_CNT_4 

Definition at line 1275 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
DP_DPCD_REV_10 
DP_DPCD_REV_11 

Definition at line 1281 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
DP_LT_NONE 
DP_LT_START 
DP_LT_CR 
DP_LT_ET 
DP_LT_FINISHED 
DP_LT_FAIL 

Definition at line 1286 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
PRE_EMPHASIS_LEVEL_0 
PRE_EMPHASIS_LEVEL_1 
PRE_EMPHASIS_LEVEL_2 
PRE_EMPHASIS_LEVEL_3 

Definition at line 1295 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
PRBS7 
D10_2 
TRAINING_PTN1 
TRAINING_PTN2 
DP_NONE 

Definition at line 1302 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
VOLTAGE_LEVEL_0 
VOLTAGE_LEVEL_1 
VOLTAGE_LEVEL_2 
VOLTAGE_LEVEL_3 

Definition at line 1310 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
CALCULATED_M 
REGISTER_M 

Definition at line 1331 of file dp.h.

◆ anonymous enum

anonymous enum
Enumerator
VIDEO_TIMING_FROM_CAPTURE 
VIDEO_TIMING_FROM_REGISTER 

Definition at line 1336 of file dp.h.

◆ analog_power_block

enum analog_power_block
Enumerator
AUX_BLOCK 
CH0_BLOCK 
CH1_BLOCK 
CH2_BLOCK 
CH3_BLOCK 
ANALOG_TOTAL 
POWER_ALL 
AUX_BLOCK 
CH0_BLOCK 
CH1_BLOCK 
CH2_BLOCK 
CH3_BLOCK 
ANALOG_TOTAL 
POWER_ALL 

Definition at line 1232 of file dp.h.

◆ pattern_type

enum pattern_type
Enumerator
NO_PATTERN 
COLOR_RAMP 
BALCK_WHITE_V_LINES 
COLOR_SQUARE 
INVALID_PATTERN 
COLORBAR_32 
COLORBAR_64 
WHITE_GRAY_BALCKBAR_32 
WHITE_GRAY_BALCKBAR_64 
MOBILE_WHITEBAR_32 
MOBILE_WHITEBAR_64 

Definition at line 1317 of file dp.h.

◆ pll_status

enum pll_status
Enumerator
DP_PLL_UNLOCKED 
DP_PLL_LOCKED 
PLL_UNLOCKED 
PLL_LOCKED 
PLL_UNLOCKED 
PLL_LOCKED 

Definition at line 1242 of file dp.h.

Function Documentation

◆ check_member()

check_member ( exynos_dp  ,
phy_ctrl  ,
0x924   
)

◆ dp_phy_control()

void dp_phy_control ( unsigned int  enable)

Definition at line 1141 of file dp_lowlevel.c.

References exynos5_power::dptx_phy_control, EXYNOS_DP_PHY_ENABLE, exynos_power, lread32, and lwrite32.

Referenced by exynos_init_dp().

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◆ exynos_dp_config_interrupt()

void exynos_dp_config_interrupt ( void  )

Definition at line 368 of file dp_lowlevel.c.

References exynos_dp::common_int_mask1, exynos_dp::common_int_mask2, exynos_dp::common_int_mask3, exynos_dp::common_int_mask4, COMMON_INT_MASK_1, COMMON_INT_MASK_2, COMMON_INT_MASK_3, COMMON_INT_MASK_4, dp_regs, exynos_dp::int_sta_mask, INT_STA_MASK, and lwrite32.

◆ exynos_dp_config_video_bist()

int exynos_dp_config_video_bist ( struct edp_device_info *  edp_info)

◆ exynos_dp_config_video_slave_mode()

void exynos_dp_config_video_slave_mode ( struct edp_video_info *  video_info)

Definition at line 985 of file dp_lowlevel.c.

References AUDIO_MODE_SPDIF_MODE, BIOS_SPEW, dp_regs, exynos_dp::func_en1, H_S_POLARITY_CFG_SHIFT, video_info::h_sync_polarity, HSYNC_POLARITY_CFG, INTERACE_SCAN_CFG, INTERACE_SCAN_CFG_SHIFT, video_info::interlaced, lread32, lwrite32, MASTER_VID_FUNC_EN_N, printk, SLAVE_VID_FUNC_EN_N, exynos_dp::soc_general_ctl, V_S_POLARITY_CFG_SHIFT, video_info::v_sync_polarity, exynos_dp::video_ctl10, VIDEO_MODE_SLAVE_MODE, and VSYNC_POLARITY_CFG.

Referenced by exynos_dp_config_video().

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◆ exynos_dp_detect_hpd()

unsigned int exynos_dp_detect_hpd ( void  )

Definition at line 400 of file dp_lowlevel.c.

References DP_TIMEOUT_LOOP_COUNT, exynos_dp_get_plug_in_status(), EXYNOS_DP_SUCCESS, and mdelay().

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◆ exynos_dp_disable_video_bist()

void exynos_dp_disable_video_bist ( void  )

Definition at line 54 of file dp_lowlevel.c.

References dp_regs, lread32, lwrite32, VIDEO_BIST_MASK, and exynos_dp::video_ctl4.

Referenced by exynos_dp_config_video(), and exynos_dp_reset().

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◆ exynos_dp_enable_enhanced_mode()

void exynos_dp_enable_enhanced_mode ( u8  enable)

Definition at line 946 of file dp_lowlevel.c.

References dp_regs, ENHANCED, lread32, lwrite32, and exynos_dp::sys_ctl4.

Referenced by exynos_dp_set_enhanced_mode(), and exynos_init_dp().

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◆ exynos_dp_enable_scrambling()

void exynos_dp_enable_scrambling ( unsigned int  enable)

Definition at line 959 of file dp_lowlevel.c.

References dp_regs, lread32, lwrite32, SCRAMBLING_DISABLE, and exynos_dp::training_ptn_set.

Referenced by exynos_dp_enable_scramble().

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◆ exynos_dp_enable_sw_func()

void exynos_dp_enable_sw_func ( unsigned int  enable)

Definition at line 175 of file dp_lowlevel.c.

References dp_regs, exynos_dp::func_en1, lread32, lwrite32, and SW_FUNC_EN_N.

Referenced by exynos_dp_init_dp().

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◆ exynos_dp_enable_video_master()

void exynos_dp_enable_video_master ( unsigned int  enable)

Definition at line 1099 of file dp_lowlevel.c.

References dp_regs, lread32, lwrite32, exynos_dp::soc_general_ctl, VIDEO_MASTER_MODE_EN, VIDEO_MODE_MASK, VIDEO_MODE_MASTER_MODE, and VIDEO_MODE_SLAVE_MODE.

Referenced by exynos_dp_config_video().

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◆ exynos_dp_enable_video_mute()

void exynos_dp_enable_video_mute ( unsigned int  enable)

Definition at line 62 of file dp_lowlevel.c.

References dp_regs, lread32, lwrite32, exynos_dp::video_ctl1, and VIDEO_MUTE_MASK.

Referenced by exynos_dp_config_video(), and exynos_dp_reset().

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◆ exynos_dp_get_lane_count()

unsigned int exynos_dp_get_lane_count ( void  )

Definition at line 861 of file dp_lowlevel.c.

References dp_regs, exynos_dp::lane_count_set, and lread32.

Referenced by exynos_dp_process_equalizer_training().

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◆ exynos_dp_get_lanex_pre_emphasis()

u8 exynos_dp_get_lanex_pre_emphasis ( u8  lanecnt)

Definition at line 870 of file dp_lowlevel.c.

References DP_LANE_CNT_4, dp_regs, exynos_dp::ln0_link_training_ctl, exynos_dp::ln1_link_training_ctl, exynos_dp::ln2_link_training_ctl, exynos_dp::ln3_link_training_ctl, and lread32.

Referenced by exynos_dp_process_clock_recovery().

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◆ exynos_dp_get_link_bandwidth()

u8 exynos_dp_get_link_bandwidth ( void  )

Definition at line 839 of file dp_lowlevel.c.

References dp_regs, exynos_dp::link_bw_set, and lread32.

Referenced by exynos_dp_process_equalizer_training().

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◆ exynos_dp_get_pll_lock_status()

unsigned int exynos_dp_get_pll_lock_status ( void  )

Definition at line 241 of file dp_lowlevel.c.

References exynos_dp::debug_ctl, dp_regs, lread32, PLL_LOCK, PLL_LOCKED, and PLL_UNLOCKED.

Referenced by exynos_dp_config_video(), and exynos_dp_init_analog_func().

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◆ exynos_dp_get_plug_in_status()

unsigned int exynos_dp_get_plug_in_status ( void  )

Definition at line 389 of file dp_lowlevel.c.

References dp_regs, HPD_STATUS, lread32, and exynos_dp::sys_ctl3.

Referenced by exynos_dp_detect_hpd().

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◆ exynos_dp_init_analog_func()

int exynos_dp_init_analog_func ( void  )

Definition at line 266 of file dp_lowlevel.c.

References AUX_FUNC_EN_N, BIOS_DEBUG, BIOS_ERR, exynos_dp::common_int_sta1, exynos_dp::debug_ctl, DP_DISABLE, DP_ENABLE, DP_PLL_RESET, dp_regs, exynos_dp_get_pll_lock_status(), exynos_dp_set_analog_power_down(), exynos_dp_set_pll_power(), EXYNOS_DP_SUCCESS, F_PLL_LOCK, exynos_dp::func_en2, lread32, LS_CLK_DOMAIN_FUNC_EN_N, lwrite32, mdelay(), exynos_dp::pll_ctl, PLL_LOCK_CHG, PLL_LOCK_CTRL, PLL_UNLOCKED, POWER_ALL, printk, and SERDES_FIFO_FUNC_EN_N.

Referenced by exynos_dp_init_dp().

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◆ exynos_dp_init_aux()

void exynos_dp_init_aux ( void  )

Definition at line 343 of file dp_lowlevel.c.

References AUX_BIT_PERIOD_EXPECTED_DELAY, exynos_dp::aux_ch_defer_ctl, AUX_ERR, AUX_FUNC_EN_N, AUX_HW_RETRY_COUNT_SEL, exynos_dp::aux_hw_retry_ctl, AUX_HW_RETRY_INTERVAL_600_MICROSECONDS, DEFER_COUNT, DEFER_CTRL_EN, dp_regs, exynos_dp_reset_aux(), exynos_dp::func_en2, exynos_dp::int_sta, lread32, lwrite32, and RPLY_RECEIV.

Referenced by exynos_dp_init_dp().

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◆ exynos_dp_init_hpd()

void exynos_dp_init_hpd ( void  )

Definition at line 317 of file dp_lowlevel.c.

References exynos_dp::common_int_sta4, dp_regs, F_HPD, HOTPLUG_CHG, HPD_CTRL, HPD_LOST, INT_HPD, exynos_dp::int_sta, lread32, lwrite32, PLUG, and exynos_dp::sys_ctl3.

Referenced by exynos_dp_init_dp().

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◆ exynos_dp_init_video()

int exynos_dp_init_video ( void  )

Definition at line 971 of file dp_lowlevel.c.

References exynos_dp::common_int_sta1, DET_CTRL, dp_regs, lwrite32, exynos_dp::sys_ctl1, VID_CLK_CHG, VID_FORMAT_CHG, and VSYNC_DET.

Referenced by exynos_init_dp().

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◆ exynos_dp_is_slave_video_stream_clock_on()

unsigned int exynos_dp_is_slave_video_stream_clock_on ( void  )

Definition at line 1039 of file dp_lowlevel.c.

References BIOS_DEBUG, DET_STA, dp_regs, EXYNOS_DP_SUCCESS, lread32, lwrite32, printk, and exynos_dp::sys_ctl1.

Referenced by exynos_dp_config_video().

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◆ exynos_dp_is_video_stream_on()

unsigned int exynos_dp_is_video_stream_on ( void  )

Definition at line 1125 of file dp_lowlevel.c.

References dp_regs, EXYNOS_DP_SUCCESS, lread32, lwrite32, STRM_VALID, and exynos_dp::sys_ctl3.

Referenced by exynos_dp_config_video().

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◆ exynos_dp_read_byte_from_dpcd()

unsigned int exynos_dp_read_byte_from_dpcd ( u32  reg_addr,
u8 *  data 
)

Definition at line 502 of file dp_lowlevel.c.

References AUX_ADDR_15_8, exynos_dp::aux_addr_15_8, AUX_ADDR_19_16, exynos_dp::aux_addr_19_16, AUX_ADDR_7_0, exynos_dp::aux_addr_7_0, exynos_dp::aux_ch_ctl1, AUX_TX_COMM_DP_TRANSACTION, AUX_TX_COMM_READ, BIOS_DEBUG, BUF_CLR, exynos_dp::buf_data0, exynos_dp::buffer_data_ctl, dp_regs, exynos_dp_start_aux_transaction(), EXYNOS_DP_SUCCESS, lread32, lwrite32, and printk.

Referenced by exynos_dp_enable_rx_to_enhanced_mode(), exynos_dp_enable_scramble(), exynos_dp_process_equalizer_training(), exynos_dp_read_dpcd_adj_req(), and exynos_dp_read_edid().

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◆ exynos_dp_read_byte_from_i2c()

int exynos_dp_read_byte_from_i2c ( u32  device_addr,
u32  reg_addr,
unsigned int *  data 
)

Definition at line 703 of file dp_lowlevel.c.

References exynos_dp::aux_ch_ctl1, AUX_TX_COMM_I2C_TRANSACTION, AUX_TX_COMM_READ, BIOS_DEBUG, BUF_CLR, exynos_dp::buf_data0, exynos_dp::buffer_data_ctl, dp_regs, exynos_dp_select_i2c_device(), exynos_dp_start_aux_transaction(), EXYNOS_DP_SUCCESS, lread32, lwrite32, and printk.

Referenced by exynos_dp_read_edid().

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◆ exynos_dp_read_bytes_from_dpcd()

u32 exynos_dp_read_bytes_from_dpcd ( unsigned int  reg_addr,
unsigned int  count,
u8  data[] 
)

Definition at line 605 of file dp_lowlevel.c.

References AUX_ADDR_15_8, exynos_dp::aux_addr_15_8, AUX_ADDR_19_16, exynos_dp::aux_addr_19_16, AUX_ADDR_7_0, exynos_dp::aux_addr_7_0, exynos_dp::aux_ch_ctl1, AUX_LENGTH, AUX_TX_COMM_DP_TRANSACTION, AUX_TX_COMM_READ, BIOS_ERR, BUF_CLR, exynos_dp::buf_data0, exynos_dp::buffer_data_ctl, count, dp_regs, exynos_dp_start_aux_transaction(), EXYNOS_DP_SUCCESS, lread32, lwrite32, and printk.

Referenced by exynos_dp_handle_edid(), and exynos_dp_read_dpcd_lane_stat().

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◆ exynos_dp_read_bytes_from_i2c()

int exynos_dp_read_bytes_from_i2c ( u32  device_addr,
u32  reg_addr,
unsigned int  count,
u8  edid[] 
)

Definition at line 745 of file dp_lowlevel.c.

References ADDR_ONLY, exynos_dp::aux_ch_ctl1, exynos_dp::aux_ch_ctl2, AUX_LENGTH, exynos_dp::aux_rx_comm, AUX_RX_COMM_AUX_DEFER, AUX_RX_COMM_I2C_DEFER, AUX_TX_COMM_I2C_TRANSACTION, AUX_TX_COMM_READ, BIOS_ERR, BUF_CLR, exynos_dp::buf_data0, exynos_dp::buffer_data_ctl, count, dp_regs, exynos_dp_select_i2c_device(), exynos_dp_start_aux_transaction(), EXYNOS_DP_SUCCESS, lread32, lwrite32, and printk.

Referenced by exynos_dp_read_edid().

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◆ exynos_dp_reset()

void exynos_dp_reset ( void  )

Definition at line 150 of file dp_lowlevel.c.

References AUD_FIFO_FUNC_EN_N, AUD_FUNC_EN_N, DP_DISABLE, dp_regs, exynos_dp_disable_video_bist(), exynos_dp_enable_video_input(), exynos_dp_enable_video_mute(), exynos_dp_init_analog_param(), exynos_dp_init_interrupt(), exynos_dp::func_en1, exynos_dp::func_en2, HDCP_FUNC_EN_N, lwrite32, MASTER_VID_FUNC_EN_N, mdelay(), RESET_DP_TX, SLAVE_VID_FUNC_EN_N, SW_FUNC_EN_N, and exynos_dp::tx_sw_reset.

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◆ exynos_dp_reset_macro()

void exynos_dp_reset_macro ( void  )

Definition at line 813 of file dp_lowlevel.c.

References dp_regs, lread32, lwrite32, MACRO_RST, exynos_dp::phy_test, and udelay().

Referenced by exynos_dp_init_training().

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◆ exynos_dp_select_i2c_device()

int exynos_dp_select_i2c_device ( u32  device_addr,
u32  reg_addr 
)

Definition at line 671 of file dp_lowlevel.c.

References exynos_dp::aux_addr_15_8, exynos_dp::aux_addr_19_16, exynos_dp::aux_addr_7_0, exynos_dp::aux_ch_ctl1, AUX_TX_COMM_I2C_TRANSACTION, AUX_TX_COMM_MOT, AUX_TX_COMM_WRITE, BIOS_DEBUG, exynos_dp::buf_data0, dp_regs, exynos_dp_start_aux_transaction(), lwrite32, and printk.

Referenced by exynos_dp_read_byte_from_i2c(), and exynos_dp_read_bytes_from_i2c().

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◆ exynos_dp_set_analog_power_down()

unsigned int exynos_dp_set_analog_power_down ( unsigned int  block,
u32  enable 
)

Definition at line 188 of file dp_lowlevel.c.

References ANALOG_TOTAL, AUX_BLOCK, AUX_PD, BIOS_ERR, CH0_BLOCK, CH0_PD, CH1_BLOCK, CH1_PD, CH2_BLOCK, CH2_PD, CH3_BLOCK, CH3_PD, dp_regs, lread32, lwrite32, exynos_dp::phy_pd, PHY_PD, POWER_ALL, and printk.

Referenced by exynos_dp_init_analog_func(), exynos_dp_init_training(), and exynos_dp_sw_link_training().

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◆ exynos_dp_set_base_addr()

void exynos_dp_set_base_addr ( void  )

◆ exynos_dp_set_lane_count()

void exynos_dp_set_lane_count ( u8  count)

Definition at line 850 of file dp_lowlevel.c.

References count, DP_LANE_CNT_1, DP_LANE_CNT_2, DP_LANE_CNT_4, dp_regs, exynos_dp::lane_count_set, and lwrite32.

Referenced by exynos_dp_link_start(), and exynos_init_dp().

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◆ exynos_dp_set_lane_pre_emphasis()

void exynos_dp_set_lane_pre_emphasis ( unsigned int  level,
u8  lanecnt 
)

Definition at line 895 of file dp_lowlevel.c.

References DP_LANE_CNT_4, dp_regs, exynos_dp::ln0_link_training_ctl, exynos_dp::ln1_link_training_ctl, exynos_dp::ln2_link_training_ctl, exynos_dp::ln3_link_training_ctl, lwrite32, PRE_EMPHASIS_SET_0_SHIFT, PRE_EMPHASIS_SET_1_SHIFT, PRE_EMPHASIS_SET_2_SHIFT, and PRE_EMPHASIS_SET_3_SHIFT.

Referenced by exynos_dp_link_start().

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◆ exynos_dp_set_lanex_pre_emphasis()

void exynos_dp_set_lanex_pre_emphasis ( u8  request_val,
u8  lanecnt 
)

Definition at line 882 of file dp_lowlevel.c.

References DP_LANE_CNT_4, dp_regs, exynos_dp::ln0_link_training_ctl, exynos_dp::ln1_link_training_ctl, exynos_dp::ln2_link_training_ctl, exynos_dp::ln3_link_training_ctl, and lwrite32.

Referenced by exynos_dp_process_clock_recovery(), and exynos_dp_process_equalizer_training().

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◆ exynos_dp_set_link_bandwidth()

void exynos_dp_set_link_bandwidth ( u8  bwtype)

Definition at line 828 of file dp_lowlevel.c.

References DP_LANE_BW_1_62, DP_LANE_BW_2_70, dp_regs, exynos_dp::link_bw_set, and lwrite32.

Referenced by exynos_dp_link_start(), and exynos_init_dp().

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◆ exynos_dp_set_training_pattern()

void exynos_dp_set_training_pattern ( unsigned int  pattern)

Definition at line 918 of file dp_lowlevel.c.

References D10_2, DP_NONE, dp_regs, LINK_QUAL_PATTERN_SET_D10_2, LINK_QUAL_PATTERN_SET_DISABLE, LINK_QUAL_PATTERN_SET_PRBS7, lwrite32, pattern, PRBS7, SCRAMBLING_DISABLE, SCRAMBLING_ENABLE, SW_TRAINING_PATTERN_SET_NORMAL, SW_TRAINING_PATTERN_SET_PTN1, SW_TRAINING_PATTERN_SET_PTN2, TRAINING_PTN1, TRAINING_PTN2, and exynos_dp::training_ptn_set.

Referenced by exynos_dp_link_start(), exynos_dp_process_clock_recovery(), and exynos_dp_training_pattern_dis().

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◆ exynos_dp_set_video_color_format()

void exynos_dp_set_video_color_format ( struct edp_video_info *  video_info)

Definition at line 1019 of file dp_lowlevel.c.

References video_info::color_depth, video_info::color_space, dp_regs, video_info::dynamic_range, IN_BPC_SHIFT, IN_COLOR_F_SHIFT, IN_D_RANGE_SHIFT, IN_YC_COEFFI_ITU601, IN_YC_COEFFI_ITU709, IN_YC_COEFFI_MASK, lread32, lwrite32, exynos_dp::video_ctl2, exynos_dp::video_ctl3, and video_info::ycbcr_coeff.

Referenced by exynos_dp_config_video().

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◆ exynos_dp_set_video_cr_mn()

void exynos_dp_set_video_cr_mn ( unsigned int  type,
unsigned int  m_value,
unsigned int  n_value 
)

Definition at line 1057 of file dp_lowlevel.c.

References dp_regs, FIX_M_VID, lread32, lwrite32, exynos_dp::m_vid0, M_VID0_CFG, exynos_dp::m_vid1, M_VID1_CFG, exynos_dp::m_vid2, M_VID2_CFG, exynos_dp::n_vid0, N_VID0_CFG, exynos_dp::n_vid1, N_VID1_CFG, exynos_dp::n_vid2, N_VID2_CFG, REGISTER_M, exynos_dp::sys_ctl4, and type.

Referenced by exynos_dp_config_video().

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◆ exynos_dp_set_video_timing_mode()

void exynos_dp_set_video_timing_mode ( unsigned int  type)

Definition at line 1086 of file dp_lowlevel.c.

References dp_regs, FORMAT_SEL, lread32, lwrite32, type, exynos_dp::video_ctl10, and VIDEO_TIMING_FROM_CAPTURE.

Referenced by exynos_dp_config_video().

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◆ exynos_dp_start_aux_transaction()

unsigned int exynos_dp_start_aux_transaction ( void  )

Definition at line 416 of file dp_lowlevel.c.

References exynos_dp::aux_ch_ctl2, exynos_dp::aux_ch_sta, AUX_EN, AUX_ERR, AUX_STATUS_MASK, BIOS_DEBUG, BIOS_ERR, dp_regs, EXYNOS_DP_SUCCESS, exynos_dp::int_sta, lread32, lwrite32, mdelay(), printk, and RPLY_RECEIV.

Referenced by exynos_dp_read_byte_from_dpcd(), exynos_dp_read_byte_from_i2c(), exynos_dp_read_bytes_from_dpcd(), exynos_dp_read_bytes_from_i2c(), exynos_dp_select_i2c_device(), exynos_dp_write_byte_to_dpcd(), and exynos_dp_write_bytes_to_dpcd().

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◆ exynos_dp_start_video()

void exynos_dp_start_video ( void  )

Definition at line 1115 of file dp_lowlevel.c.

References dp_regs, lread32, lwrite32, exynos_dp::video_ctl1, and VIDEO_EN.

Referenced by exynos_dp_config_video().

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◆ exynos_dp_write_byte_to_dpcd()

unsigned int exynos_dp_write_byte_to_dpcd ( u32  reg_addr,
u8  data 
)

Definition at line 464 of file dp_lowlevel.c.

References AUX_ADDR_15_8, exynos_dp::aux_addr_15_8, AUX_ADDR_19_16, exynos_dp::aux_addr_19_16, AUX_ADDR_7_0, exynos_dp::aux_addr_7_0, exynos_dp::aux_ch_ctl1, AUX_TX_COMM_DP_TRANSACTION, AUX_TX_COMM_WRITE, BIOS_ERR, BUF_CLR, exynos_dp::buf_data0, exynos_dp::buffer_data_ctl, dp_regs, exynos_dp_start_aux_transaction(), EXYNOS_DP_SUCCESS, lwrite32, and printk.

Referenced by exynos_dp_enable_rx_to_enhanced_mode(), exynos_dp_enable_scramble(), exynos_dp_link_start(), exynos_dp_read_edid(), and exynos_dp_training_pattern_dis().

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◆ exynos_dp_write_bytes_to_dpcd()

unsigned int exynos_dp_write_bytes_to_dpcd ( u32  reg_addr,
unsigned int  count,
u8  data[] 
)

Definition at line 540 of file dp_lowlevel.c.

References AUX_ADDR_15_8, exynos_dp::aux_addr_15_8, AUX_ADDR_19_16, exynos_dp::aux_addr_19_16, AUX_ADDR_7_0, exynos_dp::aux_addr_7_0, exynos_dp::aux_ch_ctl1, AUX_LENGTH, AUX_TX_COMM_DP_TRANSACTION, AUX_TX_COMM_WRITE, BIOS_ERR, BUF_CLR, exynos_dp::buf_data0, exynos_dp::buffer_data_ctl, count, dp_regs, exynos_dp_start_aux_transaction(), EXYNOS_DP_SUCCESS, lwrite32, and printk.

Referenced by exynos_dp_link_start(), exynos_dp_process_clock_recovery(), and exynos_dp_process_equalizer_training().

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◆ exynos_init_dp()

int exynos_init_dp ( struct edp_device_info *  edp_info)

Definition at line 841 of file dp.c.

References BIOS_DEBUG, BIOS_ERR, DP_ENABLE, dp_phy_control(), exynos_dp_config_video(), exynos_dp_enable_enhanced_mode(), exynos_dp_enable_rx_to_enhanced_mode(), exynos_dp_enable_scramble(), exynos_dp_handle_edid(), exynos_dp_init_dp(), exynos_dp_init_video(), exynos_dp_set_lane_count(), exynos_dp_set_link_bandwidth(), exynos_dp_set_link_train(), EXYNOS_DP_SUCCESS, edp_device_info::lane_bw, edp_device_info::lane_cnt, and printk.

Referenced by mainboard_init().

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◆ exynos_set_dp_platform_data()

void exynos_set_dp_platform_data ( struct exynos_dp_platform_data *  pd)

Variable Documentation

◆ exynos_dp0

struct exynos_dp* const exynos_dp0 = (void *)EXYNOS5_DP0_BASE
static

Definition at line 197 of file dp.h.

◆ exynos_dp1

struct exynos_dp* const exynos_dp1 = (void *)EXYNOS5_DP1_BASE
static

Definition at line 198 of file dp.h.