#include <soc/cpu.h>

Include dependency graph for dp.h:

Data Structures
struct	exynos5_dp

Macros
#define	RESET_DP_TX (1 << 0)

#define	MASTER_VID_FUNC_EN_N (1 << 7)

#define	SLAVE_VID_FUNC_EN_N (1 << 5)

#define	AUD_FIFO_FUNC_EN_N (1 << 4)

#define	AUD_FUNC_EN_N (1 << 3)

#define	HDCP_FUNC_EN_N (1 << 2)

#define	CRC_FUNC_EN_N (1 << 1)

#define	SW_FUNC_EN_N (1 << 0)

#define	SSC_FUNC_EN_N (1 << 7)

#define	AUX_FUNC_EN_N (1 << 2)

#define	SERDES_FIFO_FUNC_EN_N (1 << 1)

#define	LS_CLK_DOMAIN_FUNC_EN_N (1 << 0)

#define	VIDEO_EN (1 << 7)

#define	HDCP_VIDEO_MUTE (1 << 6)

#define	IN_D_RANGE_MASK (1 << 7)

#define	IN_D_RANGE_SHIFT (7)

#define	IN_D_RANGE_CEA (1 << 7)

#define	IN_D_RANGE_VESA (0 << 7)

#define	IN_BPC_MASK (7 << 4)

#define	IN_BPC_SHIFT (4)

#define	IN_BPC_12_BITS (3 << 4)

#define	IN_BPC_10_BITS (2 << 4)

#define	IN_BPC_8_BITS (1 << 4)

#define	IN_BPC_6_BITS (0 << 4)

#define	IN_COLOR_F_MASK (3 << 0)

#define	IN_COLOR_F_SHIFT (0)

#define	IN_COLOR_F_YCBCR444 (2 << 0)

#define	IN_COLOR_F_YCBCR422 (1 << 0)

#define	IN_COLOR_F_RGB (0 << 0)

#define	IN_YC_COEFFI_MASK (1 << 7)

#define	IN_YC_COEFFI_SHIFT (7)

#define	IN_YC_COEFFI_ITU709 (1 << 7)

#define	IN_YC_COEFFI_ITU601 (0 << 7)

#define	VID_CHK_UPDATE_TYPE_MASK (1 << 4)

#define	VID_CHK_UPDATE_TYPE_SHIFT (4)

#define	VID_CHK_UPDATE_TYPE_1 (1 << 4)

#define	VID_CHK_UPDATE_TYPE_0 (0 << 4)

#define	FORMAT_SEL (1 << 4)

#define	INTERACE_SCAN_CFG (1 << 2)

#define	VSYNC_POLARITY_CFG (1 << 1)

#define	HSYNC_POLARITY_CFG (1 << 0)

#define	LANE3_MAP_LOGIC_LANE_0 (0 << 6)

#define	LANE3_MAP_LOGIC_LANE_1 (1 << 6)

#define	LANE3_MAP_LOGIC_LANE_2 (2 << 6)

#define	LANE3_MAP_LOGIC_LANE_3 (3 << 6)

#define	LANE2_MAP_LOGIC_LANE_0 (0 << 4)

#define	LANE2_MAP_LOGIC_LANE_1 (1 << 4)

#define	LANE2_MAP_LOGIC_LANE_2 (2 << 4)

#define	LANE2_MAP_LOGIC_LANE_3 (3 << 4)

#define	LANE1_MAP_LOGIC_LANE_0 (0 << 2)

#define	LANE1_MAP_LOGIC_LANE_1 (1 << 2)

#define	LANE1_MAP_LOGIC_LANE_2 (2 << 2)

#define	LANE1_MAP_LOGIC_LANE_3 (3 << 2)

#define	LANE0_MAP_LOGIC_LANE_0 (0 << 0)

#define	LANE0_MAP_LOGIC_LANE_1 (1 << 0)

#define	LANE0_MAP_LOGIC_LANE_2 (2 << 0)

#define	LANE0_MAP_LOGIC_LANE_3 (3 << 0)

#define	AUX_BIT_PERIOD_SHIFT 8

#define	AUX_BIT_PERIOD_MASK 7

#define	AUX_HW_RETRY_INTERVAL_SHIFT 3

#define	AUX_HW_RETRY_INTERVAL_600_US 0

#define	AUX_HW_RETRY_INTERVAL_800_US 1

#define	AUX_HW_RETRY_INTERVAL_1000_US 2

#define	AUX_HW_RETRY_INTERVAL_1800_US 3

#define	AUX_HW_RETRY_COUNT_SHIFT 0

#define	AUX_HW_RETRY_COUNT_MASK 7

#define	VSYNC_DET (1 << 7)

#define	PLL_LOCK_CHG (1 << 6)

#define	SPDIF_ERR (1 << 5)

#define	SPDIF_UNSTBL (1 << 4)

#define	VID_FORMAT_CHG (1 << 3)

#define	AUD_CLK_CHG (1 << 2)

#define	VID_CLK_CHG (1 << 1)

#define	SW_INT (1 << 0)

#define	ENC_EN_CHG (1 << 6)

#define	HW_BKSV_RDY (1 << 3)

#define	HW_SHA_DONE (1 << 2)

#define	HW_AUTH_STATE_CHG (1 << 1)

#define	HW_AUTH_DONE (1 << 0)

#define	AFIFO_UNDER (1 << 7)

#define	AFIFO_OVER (1 << 6)

#define	R0_CHK_FLAG (1 << 5)

#define	PSR_ACTIVE (1 << 7)

#define	PSR_INACTIVE (1 << 6)

#define	SPDIF_BI_PHASE_ERR (1 << 5)

#define	HOTPLUG_CHG (1 << 2)

#define	HPD_LOST (1 << 1)

#define	PLUG (1 << 0)

#define	INT_HPD (1 << 6)

#define	HW_TRAINING_FINISH (1 << 5)

#define	RPLY_RECEIV (1 << 1)

#define	AUX_ERR (1 << 0)

#define	INT_POL0 (1 << 0)

#define	INT_POL1 (1 << 1)

#define	SOFT_INT_CTRL (1 << 2)

#define	DET_STA (1 << 2)

#define	FORCE_DET (1 << 1)

#define	DET_CTRL (1 << 0)

#define	CHA_CRI_SHIFT 4

#define	CHA_CRI_MASK 0xf

#define	CHA_STA (1 << 2)

#define	FORCE_CHA (1 << 1)

#define	CHA_CTRL (1 << 0)

#define	HPD_STATUS (1 << 6)

#define	F_HPD (1 << 5)

#define	HPD_CTRL (1 << 4)

#define	HDCP_RDY (1 << 3)

#define	STRM_VALID (1 << 2)

#define	F_VALID (1 << 1)

#define	VALID_CTRL (1 << 0)

#define	FIX_M_AUD (1 << 4)

#define	ENHANCED (1 << 3)

#define	FIX_M_VID (1 << 2)

#define	M_VID_UPDATE_CTRL (3 << 0)

#define	SCRAMBLER_TYPE (1 << 9)

#define	HW_LINK_TRAINING_PATTERN (1 << 8)

#define	SCRAMBLING_DISABLE (1 << 5)

#define	SCRAMBLING_ENABLE (0 << 5)

#define	LINK_QUAL_PATTERN_SET_MASK (3 << 2)

#define	LINK_QUAL_PATTERN_SET_PRBS7 (3 << 2)

#define	LINK_QUAL_PATTERN_SET_D10_2 (1 << 2)

#define	LINK_QUAL_PATTERN_SET_DISABLE (0 << 2)

#define	SW_TRAINING_PATTERN_SET_MASK (3 << 0)

#define	SW_TRAINING_PATTERN_SET_PTN2 (2 << 0)

#define	SW_TRAINING_PATTERN_SET_PTN1 (1 << 0)

#define	SW_TRAINING_PATTERN_SET_NORMAL (0 << 0)

#define	PRE_EMPHASIS_SET_SHIFT (3)

#define	PLL_LOCK (1 << 4)

#define	F_PLL_LOCK (1 << 3)

#define	PLL_LOCK_CTRL (1 << 2)

#define	PN_INV (1 << 0)

#define	M_VID_0_VALUE_SHIFT 0

#define	M_VID_1_VALUE_SHIFT 8

#define	M_VID_2_VALUE_SHIFT 16

#define	N_VID_0_VALUE_SHIFT 0

#define	N_VID_1_VALUE_SHIFT 8

#define	N_VID_2_VALUE_SHIFT 16

#define	DP_PLL_PD (1 << 7)

#define	DP_PLL_RESET (1 << 6)

#define	DP_PLL_LOOP_BIT_DEFAULT (1 << 4)

#define	DP_PLL_REF_BIT_1_1250V (5 << 0)

#define	DP_PLL_REF_BIT_1_2500V (7 << 0)

#define	DP_PHY_PD (1 << 5)

#define	AUX_PD (1 << 4)

#define	CH3_PD (1 << 3)

#define	CH2_PD (1 << 2)

#define	CH1_PD (1 << 1)

#define	CH0_PD (1 << 0)

#define	MACRO_RST (1 << 5)

#define	CH1_TEST (1 << 1)

#define	CH0_TEST (1 << 0)

#define	AUX_BUSY (1 << 4)

#define	AUX_STATUS_MASK (0xf << 0)

#define	DEFER_CTRL_EN (1 << 7)

#define	DEFER_COUNT_SHIFT 0

#define	DEFER_COUNT_MASK 0x7f

#define	AUX_RX_COMM_I2C_DEFER (2 << 2)

#define	AUX_RX_COMM_AUX_DEFER (2 << 0)

#define	BUF_CLR (1 << 7)

#define	MAX_AUX_RETRY_COUNT 10

#define	AUX_LENGTH_SHIFT 4

#define	AUX_LENGTH_MASK 0xf

#define	AUX_TX_COMM_MASK (0xf << 0)

#define	AUX_TX_COMM_DP_TRANSACTION (1 << 3)

#define	AUX_TX_COMM_I2C_TRANSACTION (0 << 3)

#define	AUX_TX_COMM_MOT (1 << 2)

#define	AUX_TX_COMM_WRITE (0 << 0)

#define	AUX_TX_COMM_READ (1 << 0)

#define	AUX_ADDR_7_0_SHIFT 0

#define	AUX_ADDR_7_0_MASK 0xff

#define	AUX_ADDR_15_8_SHIFT 8

#define	AUX_ADDR_15_8_MASK 0xff

#define	AUX_ADDR_19_16_SHIFT 16

#define	AUX_ADDR_19_16_MASK 0x0f

#define	ADDR_ONLY (1 << 1)

#define	AUX_EN (1 << 0)

#define	AUDIO_MODE_SPDIF_MODE (1 << 8)

#define	AUDIO_MODE_MASTER_MODE (0 << 8)

#define	MASTER_VIDEO_INTERLACE_EN (1 << 4)

#define	VIDEO_MASTER_CLK_SEL (1 << 2)

#define	VIDEO_MASTER_MODE_EN (1 << 1)

#define	VIDEO_MODE_MASK (1 << 0)

#define	VIDEO_MODE_SLAVE_MODE (1 << 0)

#define	VIDEO_MODE_MASTER_MODE (0 << 0)

#define	HW_TRAINING_ERROR_CODE (7<<4)

#define	HW_TRAINING_EN (1<<0)

#define	I2C_EDID_DEVICE_ADDR 0x50

#define	I2C_E_EDID_DEVICE_ADDR 0x30

#define	EDID_BLOCK_LENGTH 0x80

#define	EDID_HEADER_PATTERN 0x00

#define	EDID_EXTENSION_FLAG 0x7e

#define	EDID_CHECKSUM 0x7f

#define	DPCD_ADDR_DPCD_REV 0x0000

#define	DPCD_ADDR_MAX_LINK_RATE 0x0001

#define	DPCD_ADDR_MAX_LANE_COUNT 0x0002

#define	DPCD_ADDR_LINK_BW_SET 0x0100

#define	DPCD_ADDR_LANE_COUNT_SET 0x0101

#define	DPCD_ADDR_TRAINING_PATTERN_SET 0x0102

#define	DPCD_ADDR_TRAINING_LANE0_SET 0x0103

#define	DPCD_ADDR_LANE0_1_STATUS 0x0202

#define	DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204

#define	DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206

#define	DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207

#define	DPCD_ADDR_TEST_REQUEST 0x0218

#define	DPCD_ADDR_TEST_RESPONSE 0x0260

#define	DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261

#define	DPCD_ADDR_SINK_POWER_STATE 0x0600

#define	DPCD_MAX_LANE_COUNT_MASK 0x1f

#define	DPCD_ENHANCED_FRAME_EN (1 << 7)

#define	DPCD_LANE_COUNT_SET_MASK 0x1f

#define	DPCD_SCRAMBLING_DISABLED (1 << 5)

#define	DPCD_SCRAMBLING_ENABLED (0 << 5)

#define	DPCD_TRAINING_PATTERN_2 (2 << 0)

#define	DPCD_TRAINING_PATTERN_1 (1 << 0)

#define	DPCD_TRAINING_PATTERN_DISABLED (0 << 0)

#define	DPCD_LANE_SYMBOL_LOCKED (1 << 2)

#define	DPCD_LANE_CHANNEL_EQ_DONE (1 << 1)

#define	DPCD_LANE_CR_DONE (1 << 0)

#define	DPCD_CHANNEL_EQ_BITS

#define	DPCD_LINK_STATUS_UPDATED (1 << 7)

#define	DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)

#define	DPCD_INTERLANE_ALIGN_DONE (1 << 0)

#define	DPCD_TEST_EDID_READ (1 << 2)

#define	DPCD_TEST_EDID_CHECKSUM_WRITE (1 << 2)

#define	DPCD_SET_POWER_STATE_D0 (1 << 0)

#define	DPCD_SET_POWER_STATE_D4 (2 << 0)

Functions
	check_member (exynos5_dp, soc_general_ctl, 0x800)

void	clock_init_dp_clock (void)

Variables
static struct exynos5_dp *const	exynos_dp0 = (void *)EXYNOS5_DP0_BASE

static struct exynos5_dp *const	exynos_dp1 = (void *)EXYNOS5_DP1_BASE

Macro Definition Documentation

◆ ADDR_ONLY

#define ADDR_ONLY (1 << 1)

Definition at line 404 of file dp.h.

◆ AFIFO_OVER

#define AFIFO_OVER (1 << 6)

Definition at line 259 of file dp.h.

◆ AFIFO_UNDER

#define AFIFO_UNDER (1 << 7)

Definition at line 258 of file dp.h.

◆ AUD_CLK_CHG

#define AUD_CLK_CHG (1 << 2)

Definition at line 246 of file dp.h.

◆ AUD_FIFO_FUNC_EN_N

#define AUD_FIFO_FUNC_EN_N (1 << 4)

Definition at line 161 of file dp.h.

◆ AUD_FUNC_EN_N

#define AUD_FUNC_EN_N (1 << 3)

Definition at line 162 of file dp.h.

◆ AUDIO_MODE_MASTER_MODE

#define AUDIO_MODE_MASTER_MODE (0 << 8)

Definition at line 409 of file dp.h.

◆ AUDIO_MODE_SPDIF_MODE

#define AUDIO_MODE_SPDIF_MODE (1 << 8)

Definition at line 408 of file dp.h.

◆ AUX_ADDR_15_8_MASK

#define AUX_ADDR_15_8_MASK 0xff

Definition at line 397 of file dp.h.

◆ AUX_ADDR_15_8_SHIFT

#define AUX_ADDR_15_8_SHIFT 8

Definition at line 396 of file dp.h.

◆ AUX_ADDR_19_16_MASK

#define AUX_ADDR_19_16_MASK 0x0f

Definition at line 401 of file dp.h.

◆ AUX_ADDR_19_16_SHIFT

#define AUX_ADDR_19_16_SHIFT 16

Definition at line 400 of file dp.h.

◆ AUX_ADDR_7_0_MASK

#define AUX_ADDR_7_0_MASK 0xff

Definition at line 393 of file dp.h.

◆ AUX_ADDR_7_0_SHIFT

#define AUX_ADDR_7_0_SHIFT 0

Definition at line 392 of file dp.h.

◆ AUX_BIT_PERIOD_MASK

#define AUX_BIT_PERIOD_MASK 7

Definition at line 230 of file dp.h.

◆ AUX_BIT_PERIOD_SHIFT

#define AUX_BIT_PERIOD_SHIFT 8

Definition at line 229 of file dp.h.

◆ AUX_BUSY

#define AUX_BUSY (1 << 4)

Definition at line 362 of file dp.h.

◆ AUX_EN

#define AUX_EN (1 << 0)

Definition at line 405 of file dp.h.

◆ AUX_ERR

#define AUX_ERR (1 << 0)

Definition at line 274 of file dp.h.

◆ AUX_FUNC_EN_N

#define AUX_FUNC_EN_N (1 << 2)

Definition at line 169 of file dp.h.

◆ AUX_HW_RETRY_COUNT_MASK

#define AUX_HW_RETRY_COUNT_MASK 7

Definition at line 238 of file dp.h.

◆ AUX_HW_RETRY_COUNT_SHIFT

#define AUX_HW_RETRY_COUNT_SHIFT 0

Definition at line 237 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_1000_US

#define AUX_HW_RETRY_INTERVAL_1000_US 2

Definition at line 235 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_1800_US

#define AUX_HW_RETRY_INTERVAL_1800_US 3

Definition at line 236 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_600_US

#define AUX_HW_RETRY_INTERVAL_600_US 0

Definition at line 233 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_800_US

#define AUX_HW_RETRY_INTERVAL_800_US 1

Definition at line 234 of file dp.h.

◆ AUX_HW_RETRY_INTERVAL_SHIFT

#define AUX_HW_RETRY_INTERVAL_SHIFT 3

Definition at line 232 of file dp.h.

◆ AUX_LENGTH_MASK

#define AUX_LENGTH_MASK 0xf

Definition at line 382 of file dp.h.

◆ AUX_LENGTH_SHIFT

#define AUX_LENGTH_SHIFT 4

Definition at line 381 of file dp.h.

◆ AUX_PD

#define AUX_PD (1 << 4)

Definition at line 350 of file dp.h.

◆ AUX_RX_COMM_AUX_DEFER

#define AUX_RX_COMM_AUX_DEFER (2 << 0)

Definition at line 372 of file dp.h.

◆ AUX_RX_COMM_I2C_DEFER

#define AUX_RX_COMM_I2C_DEFER (2 << 2)

Definition at line 371 of file dp.h.

◆ AUX_STATUS_MASK

#define AUX_STATUS_MASK (0xf << 0)

Definition at line 363 of file dp.h.

◆ AUX_TX_COMM_DP_TRANSACTION

#define AUX_TX_COMM_DP_TRANSACTION (1 << 3)

Definition at line 385 of file dp.h.

◆ AUX_TX_COMM_I2C_TRANSACTION

#define AUX_TX_COMM_I2C_TRANSACTION (0 << 3)

Definition at line 386 of file dp.h.

◆ AUX_TX_COMM_MASK

#define AUX_TX_COMM_MASK (0xf << 0)

Definition at line 384 of file dp.h.

◆ AUX_TX_COMM_MOT

#define AUX_TX_COMM_MOT (1 << 2)

Definition at line 387 of file dp.h.

◆ AUX_TX_COMM_READ

#define AUX_TX_COMM_READ (1 << 0)

Definition at line 389 of file dp.h.

◆ AUX_TX_COMM_WRITE

#define AUX_TX_COMM_WRITE (0 << 0)

Definition at line 388 of file dp.h.

◆ BUF_CLR

#define BUF_CLR (1 << 7)

Definition at line 375 of file dp.h.

◆ CH0_PD

#define CH0_PD (1 << 0)

Definition at line 354 of file dp.h.

◆ CH0_TEST

#define CH0_TEST (1 << 0)

Definition at line 359 of file dp.h.

◆ CH1_PD

#define CH1_PD (1 << 1)

Definition at line 353 of file dp.h.

◆ CH1_TEST

#define CH1_TEST (1 << 1)

Definition at line 358 of file dp.h.

◆ CH2_PD

#define CH2_PD (1 << 2)

Definition at line 352 of file dp.h.

◆ CH3_PD

#define CH3_PD (1 << 3)

Definition at line 351 of file dp.h.

◆ CHA_CRI_MASK

#define CHA_CRI_MASK 0xf

Definition at line 288 of file dp.h.

◆ CHA_CRI_SHIFT

#define CHA_CRI_SHIFT 4

Definition at line 287 of file dp.h.

◆ CHA_CTRL

#define CHA_CTRL (1 << 0)

Definition at line 291 of file dp.h.

◆ CHA_STA

#define CHA_STA (1 << 2)

Definition at line 289 of file dp.h.

◆ CRC_FUNC_EN_N

#define CRC_FUNC_EN_N (1 << 1)

Definition at line 164 of file dp.h.

◆ DEFER_COUNT_MASK

#define DEFER_COUNT_MASK 0x7f

Definition at line 368 of file dp.h.

◆ DEFER_COUNT_SHIFT

#define DEFER_COUNT_SHIFT 0

Definition at line 367 of file dp.h.

◆ DEFER_CTRL_EN

#define DEFER_CTRL_EN (1 << 7)

Definition at line 366 of file dp.h.

◆ DET_CTRL

#define DET_CTRL (1 << 0)

Definition at line 284 of file dp.h.

◆ DET_STA

#define DET_STA (1 << 2)

Definition at line 282 of file dp.h.

◆ DP_PHY_PD

#define DP_PHY_PD (1 << 5)

Definition at line 349 of file dp.h.

◆ DP_PLL_LOOP_BIT_DEFAULT

#define DP_PLL_LOOP_BIT_DEFAULT (1 << 4)

Definition at line 344 of file dp.h.

◆ DP_PLL_PD

#define DP_PLL_PD (1 << 7)

Definition at line 342 of file dp.h.

◆ DP_PLL_REF_BIT_1_1250V

#define DP_PLL_REF_BIT_1_1250V (5 << 0)

Definition at line 345 of file dp.h.

◆ DP_PLL_REF_BIT_1_2500V

#define DP_PLL_REF_BIT_1_2500V (7 << 0)

Definition at line 346 of file dp.h.

◆ DP_PLL_RESET

#define DP_PLL_RESET (1 << 6)

Definition at line 343 of file dp.h.

◆ DPCD_ADDR_ADJUST_REQUEST_LANE0_1

#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206

Definition at line 439 of file dp.h.

◆ DPCD_ADDR_ADJUST_REQUEST_LANE2_3

#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207

Definition at line 440 of file dp.h.

◆ DPCD_ADDR_DPCD_REV

#define DPCD_ADDR_DPCD_REV 0x0000

Definition at line 430 of file dp.h.

◆ DPCD_ADDR_LANE0_1_STATUS

#define DPCD_ADDR_LANE0_1_STATUS 0x0202

Definition at line 437 of file dp.h.

◆ DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED

#define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204

Definition at line 438 of file dp.h.

◆ DPCD_ADDR_LANE_COUNT_SET

#define DPCD_ADDR_LANE_COUNT_SET 0x0101

Definition at line 434 of file dp.h.

◆ DPCD_ADDR_LINK_BW_SET

#define DPCD_ADDR_LINK_BW_SET 0x0100

Definition at line 433 of file dp.h.

◆ DPCD_ADDR_MAX_LANE_COUNT

#define DPCD_ADDR_MAX_LANE_COUNT 0x0002

Definition at line 432 of file dp.h.

◆ DPCD_ADDR_MAX_LINK_RATE

#define DPCD_ADDR_MAX_LINK_RATE 0x0001

Definition at line 431 of file dp.h.

◆ DPCD_ADDR_SINK_POWER_STATE

#define DPCD_ADDR_SINK_POWER_STATE 0x0600

Definition at line 444 of file dp.h.

◆ DPCD_ADDR_TEST_EDID_CHECKSUM

#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261

Definition at line 443 of file dp.h.

◆ DPCD_ADDR_TEST_REQUEST

#define DPCD_ADDR_TEST_REQUEST 0x0218

Definition at line 441 of file dp.h.

◆ DPCD_ADDR_TEST_RESPONSE

#define DPCD_ADDR_TEST_RESPONSE 0x0260

Definition at line 442 of file dp.h.

◆ DPCD_ADDR_TRAINING_LANE0_SET

#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103

Definition at line 436 of file dp.h.

◆ DPCD_ADDR_TRAINING_PATTERN_SET

#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102

Definition at line 435 of file dp.h.

◆ DPCD_CHANNEL_EQ_BITS

#define DPCD_CHANNEL_EQ_BITS

Value:

                                                 (DPCD_LANE_CR_DONE | \
                                                 DPCD_LANE_CHANNEL_EQ_DONE | \
                                                 DPCD_LANE_SYMBOL_LOCKED)

Definition at line 464 of file dp.h.

◆ DPCD_DOWNSTREAM_PORT_STATUS_CHANGED

#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)

Definition at line 470 of file dp.h.

◆ DPCD_ENHANCED_FRAME_EN

#define DPCD_ENHANCED_FRAME_EN (1 << 7)

Definition at line 450 of file dp.h.

◆ DPCD_INTERLANE_ALIGN_DONE

#define DPCD_INTERLANE_ALIGN_DONE (1 << 0)

Definition at line 471 of file dp.h.

◆ DPCD_LANE_CHANNEL_EQ_DONE

#define DPCD_LANE_CHANNEL_EQ_DONE (1 << 1)

Definition at line 462 of file dp.h.

◆ DPCD_LANE_COUNT_SET_MASK

#define DPCD_LANE_COUNT_SET_MASK 0x1f

Definition at line 451 of file dp.h.

◆ DPCD_LANE_CR_DONE

#define DPCD_LANE_CR_DONE (1 << 0)

Definition at line 463 of file dp.h.

◆ DPCD_LANE_SYMBOL_LOCKED

#define DPCD_LANE_SYMBOL_LOCKED (1 << 2)

Definition at line 461 of file dp.h.

◆ DPCD_LINK_STATUS_UPDATED

#define DPCD_LINK_STATUS_UPDATED (1 << 7)

Definition at line 469 of file dp.h.

◆ DPCD_MAX_LANE_COUNT_MASK

#define DPCD_MAX_LANE_COUNT_MASK 0x1f

Definition at line 447 of file dp.h.

◆ DPCD_SCRAMBLING_DISABLED

#define DPCD_SCRAMBLING_DISABLED (1 << 5)

Definition at line 454 of file dp.h.

◆ DPCD_SCRAMBLING_ENABLED

#define DPCD_SCRAMBLING_ENABLED (0 << 5)

Definition at line 455 of file dp.h.

◆ DPCD_SET_POWER_STATE_D0

#define DPCD_SET_POWER_STATE_D0 (1 << 0)

Definition at line 480 of file dp.h.

◆ DPCD_SET_POWER_STATE_D4

#define DPCD_SET_POWER_STATE_D4 (2 << 0)

Definition at line 481 of file dp.h.

◆ DPCD_TEST_EDID_CHECKSUM_WRITE

#define DPCD_TEST_EDID_CHECKSUM_WRITE (1 << 2)

Definition at line 477 of file dp.h.

◆ DPCD_TEST_EDID_READ

#define DPCD_TEST_EDID_READ (1 << 2)

Definition at line 474 of file dp.h.

◆ DPCD_TRAINING_PATTERN_1

#define DPCD_TRAINING_PATTERN_1 (1 << 0)

Definition at line 457 of file dp.h.

◆ DPCD_TRAINING_PATTERN_2

#define DPCD_TRAINING_PATTERN_2 (2 << 0)

Definition at line 456 of file dp.h.

◆ DPCD_TRAINING_PATTERN_DISABLED

#define DPCD_TRAINING_PATTERN_DISABLED (0 << 0)

Definition at line 458 of file dp.h.

◆ EDID_BLOCK_LENGTH

#define EDID_BLOCK_LENGTH 0x80

Definition at line 424 of file dp.h.

◆ EDID_CHECKSUM

#define EDID_CHECKSUM 0x7f

Definition at line 427 of file dp.h.

◆ EDID_EXTENSION_FLAG

#define EDID_EXTENSION_FLAG 0x7e

Definition at line 426 of file dp.h.

◆ EDID_HEADER_PATTERN

#define EDID_HEADER_PATTERN 0x00

Definition at line 425 of file dp.h.

◆ ENC_EN_CHG

#define ENC_EN_CHG (1 << 6)

Definition at line 251 of file dp.h.

◆ ENHANCED

#define ENHANCED (1 << 3)

Definition at line 304 of file dp.h.

◆ F_HPD

#define F_HPD (1 << 5)

Definition at line 295 of file dp.h.

◆ F_PLL_LOCK

#define F_PLL_LOCK (1 << 3)

Definition at line 327 of file dp.h.

◆ F_VALID

#define F_VALID (1 << 1)

Definition at line 299 of file dp.h.

◆ FIX_M_AUD

#define FIX_M_AUD (1 << 4)

Definition at line 303 of file dp.h.

◆ FIX_M_VID

#define FIX_M_VID (1 << 2)

Definition at line 305 of file dp.h.

◆ FORCE_CHA

#define FORCE_CHA (1 << 1)

Definition at line 290 of file dp.h.

◆ FORCE_DET

#define FORCE_DET (1 << 1)

Definition at line 283 of file dp.h.

◆ FORMAT_SEL

#define FORMAT_SEL (1 << 4)

Definition at line 205 of file dp.h.

◆ HDCP_FUNC_EN_N

#define HDCP_FUNC_EN_N (1 << 2)

Definition at line 163 of file dp.h.

◆ HDCP_RDY

#define HDCP_RDY (1 << 3)

Definition at line 297 of file dp.h.

◆ HDCP_VIDEO_MUTE

#define HDCP_VIDEO_MUTE (1 << 6)

Definition at line 175 of file dp.h.

◆ HOTPLUG_CHG

#define HOTPLUG_CHG (1 << 2)

Definition at line 266 of file dp.h.

◆ HPD_CTRL

#define HPD_CTRL (1 << 4)

Definition at line 296 of file dp.h.

◆ HPD_LOST

#define HPD_LOST (1 << 1)

Definition at line 267 of file dp.h.

◆ HPD_STATUS

#define HPD_STATUS (1 << 6)

Definition at line 294 of file dp.h.

◆ HSYNC_POLARITY_CFG

#define HSYNC_POLARITY_CFG (1 << 0)

Definition at line 208 of file dp.h.

◆ HW_AUTH_DONE

#define HW_AUTH_DONE (1 << 0)

Definition at line 255 of file dp.h.

◆ HW_AUTH_STATE_CHG

#define HW_AUTH_STATE_CHG (1 << 1)

Definition at line 254 of file dp.h.

◆ HW_BKSV_RDY

#define HW_BKSV_RDY (1 << 3)

Definition at line 252 of file dp.h.

◆ HW_LINK_TRAINING_PATTERN

#define HW_LINK_TRAINING_PATTERN (1 << 8)

Definition at line 310 of file dp.h.

◆ HW_SHA_DONE

#define HW_SHA_DONE (1 << 2)

Definition at line 253 of file dp.h.

◆ HW_TRAINING_EN

#define HW_TRAINING_EN (1<<0)

Definition at line 418 of file dp.h.

◆ HW_TRAINING_ERROR_CODE

#define HW_TRAINING_ERROR_CODE (7<<4)

Definition at line 417 of file dp.h.

◆ HW_TRAINING_FINISH

#define HW_TRAINING_FINISH (1 << 5)

Definition at line 272 of file dp.h.

◆ I2C_E_EDID_DEVICE_ADDR

#define I2C_E_EDID_DEVICE_ADDR 0x30

Definition at line 422 of file dp.h.

◆ I2C_EDID_DEVICE_ADDR

#define I2C_EDID_DEVICE_ADDR 0x50

Definition at line 421 of file dp.h.

◆ IN_BPC_10_BITS

#define IN_BPC_10_BITS (2 << 4)

Definition at line 185 of file dp.h.

◆ IN_BPC_12_BITS

#define IN_BPC_12_BITS (3 << 4)

Definition at line 184 of file dp.h.

◆ IN_BPC_6_BITS

#define IN_BPC_6_BITS (0 << 4)

Definition at line 187 of file dp.h.

◆ IN_BPC_8_BITS

#define IN_BPC_8_BITS (1 << 4)

Definition at line 186 of file dp.h.

◆ IN_BPC_MASK

#define IN_BPC_MASK (7 << 4)

Definition at line 182 of file dp.h.

◆ IN_BPC_SHIFT

#define IN_BPC_SHIFT (4)

Definition at line 183 of file dp.h.

◆ IN_COLOR_F_MASK

#define IN_COLOR_F_MASK (3 << 0)

Definition at line 188 of file dp.h.

◆ IN_COLOR_F_RGB

#define IN_COLOR_F_RGB (0 << 0)

Definition at line 192 of file dp.h.

◆ IN_COLOR_F_SHIFT

#define IN_COLOR_F_SHIFT (0)

Definition at line 189 of file dp.h.

◆ IN_COLOR_F_YCBCR422

#define IN_COLOR_F_YCBCR422 (1 << 0)

Definition at line 191 of file dp.h.

◆ IN_COLOR_F_YCBCR444

#define IN_COLOR_F_YCBCR444 (2 << 0)

Definition at line 190 of file dp.h.

◆ IN_D_RANGE_CEA

#define IN_D_RANGE_CEA (1 << 7)

Definition at line 180 of file dp.h.

◆ IN_D_RANGE_MASK

#define IN_D_RANGE_MASK (1 << 7)

Definition at line 178 of file dp.h.

◆ IN_D_RANGE_SHIFT

#define IN_D_RANGE_SHIFT (7)

Definition at line 179 of file dp.h.

◆ IN_D_RANGE_VESA

#define IN_D_RANGE_VESA (0 << 7)

Definition at line 181 of file dp.h.

◆ IN_YC_COEFFI_ITU601

#define IN_YC_COEFFI_ITU601 (0 << 7)

Definition at line 198 of file dp.h.

◆ IN_YC_COEFFI_ITU709

#define IN_YC_COEFFI_ITU709 (1 << 7)

Definition at line 197 of file dp.h.

◆ IN_YC_COEFFI_MASK

#define IN_YC_COEFFI_MASK (1 << 7)

Definition at line 195 of file dp.h.

◆ IN_YC_COEFFI_SHIFT

#define IN_YC_COEFFI_SHIFT (7)

Definition at line 196 of file dp.h.

◆ INT_HPD

#define INT_HPD (1 << 6)

Definition at line 271 of file dp.h.

◆ INT_POL0

#define INT_POL0 (1 << 0)

Definition at line 277 of file dp.h.

◆ INT_POL1

#define INT_POL1 (1 << 1)

Definition at line 278 of file dp.h.

◆ INTERACE_SCAN_CFG

#define INTERACE_SCAN_CFG (1 << 2)

Definition at line 206 of file dp.h.

◆ LANE0_MAP_LOGIC_LANE_0

#define LANE0_MAP_LOGIC_LANE_0 (0 << 0)

Definition at line 223 of file dp.h.

◆ LANE0_MAP_LOGIC_LANE_1

#define LANE0_MAP_LOGIC_LANE_1 (1 << 0)

Definition at line 224 of file dp.h.

◆ LANE0_MAP_LOGIC_LANE_2

#define LANE0_MAP_LOGIC_LANE_2 (2 << 0)

Definition at line 225 of file dp.h.

◆ LANE0_MAP_LOGIC_LANE_3

#define LANE0_MAP_LOGIC_LANE_3 (3 << 0)

Definition at line 226 of file dp.h.

◆ LANE1_MAP_LOGIC_LANE_0

#define LANE1_MAP_LOGIC_LANE_0 (0 << 2)

Definition at line 219 of file dp.h.

◆ LANE1_MAP_LOGIC_LANE_1

#define LANE1_MAP_LOGIC_LANE_1 (1 << 2)

Definition at line 220 of file dp.h.

◆ LANE1_MAP_LOGIC_LANE_2

#define LANE1_MAP_LOGIC_LANE_2 (2 << 2)

Definition at line 221 of file dp.h.

◆ LANE1_MAP_LOGIC_LANE_3

#define LANE1_MAP_LOGIC_LANE_3 (3 << 2)

Definition at line 222 of file dp.h.

◆ LANE2_MAP_LOGIC_LANE_0

#define LANE2_MAP_LOGIC_LANE_0 (0 << 4)

Definition at line 215 of file dp.h.

◆ LANE2_MAP_LOGIC_LANE_1

#define LANE2_MAP_LOGIC_LANE_1 (1 << 4)

Definition at line 216 of file dp.h.

◆ LANE2_MAP_LOGIC_LANE_2

#define LANE2_MAP_LOGIC_LANE_2 (2 << 4)

Definition at line 217 of file dp.h.

◆ LANE2_MAP_LOGIC_LANE_3

#define LANE2_MAP_LOGIC_LANE_3 (3 << 4)

Definition at line 218 of file dp.h.

◆ LANE3_MAP_LOGIC_LANE_0

#define LANE3_MAP_LOGIC_LANE_0 (0 << 6)

Definition at line 211 of file dp.h.

◆ LANE3_MAP_LOGIC_LANE_1

#define LANE3_MAP_LOGIC_LANE_1 (1 << 6)

Definition at line 212 of file dp.h.

◆ LANE3_MAP_LOGIC_LANE_2

#define LANE3_MAP_LOGIC_LANE_2 (2 << 6)

Definition at line 213 of file dp.h.

◆ LANE3_MAP_LOGIC_LANE_3

#define LANE3_MAP_LOGIC_LANE_3 (3 << 6)

Definition at line 214 of file dp.h.

◆ LINK_QUAL_PATTERN_SET_D10_2

#define LINK_QUAL_PATTERN_SET_D10_2 (1 << 2)

Definition at line 315 of file dp.h.

◆ LINK_QUAL_PATTERN_SET_DISABLE

#define LINK_QUAL_PATTERN_SET_DISABLE (0 << 2)

Definition at line 316 of file dp.h.

◆ LINK_QUAL_PATTERN_SET_MASK

#define LINK_QUAL_PATTERN_SET_MASK (3 << 2)

Definition at line 313 of file dp.h.

◆ LINK_QUAL_PATTERN_SET_PRBS7

#define LINK_QUAL_PATTERN_SET_PRBS7 (3 << 2)

Definition at line 314 of file dp.h.

◆ LS_CLK_DOMAIN_FUNC_EN_N

#define LS_CLK_DOMAIN_FUNC_EN_N (1 << 0)

Definition at line 171 of file dp.h.

◆ M_VID_0_VALUE_SHIFT

#define M_VID_0_VALUE_SHIFT 0

Definition at line 332 of file dp.h.

◆ M_VID_1_VALUE_SHIFT

#define M_VID_1_VALUE_SHIFT 8

Definition at line 333 of file dp.h.

◆ M_VID_2_VALUE_SHIFT

#define M_VID_2_VALUE_SHIFT 16

Definition at line 334 of file dp.h.

◆ M_VID_UPDATE_CTRL

#define M_VID_UPDATE_CTRL (3 << 0)

Definition at line 306 of file dp.h.

◆ MACRO_RST

#define MACRO_RST (1 << 5)

Definition at line 357 of file dp.h.

◆ MASTER_VID_FUNC_EN_N

#define MASTER_VID_FUNC_EN_N (1 << 7)

Definition at line 159 of file dp.h.

◆ MASTER_VIDEO_INTERLACE_EN

#define MASTER_VIDEO_INTERLACE_EN (1 << 4)

Definition at line 410 of file dp.h.

◆ MAX_AUX_RETRY_COUNT

#define MAX_AUX_RETRY_COUNT 10

Definition at line 378 of file dp.h.

◆ N_VID_0_VALUE_SHIFT

#define N_VID_0_VALUE_SHIFT 0

Definition at line 337 of file dp.h.

◆ N_VID_1_VALUE_SHIFT

#define N_VID_1_VALUE_SHIFT 8

Definition at line 338 of file dp.h.

◆ N_VID_2_VALUE_SHIFT

#define N_VID_2_VALUE_SHIFT 16

Definition at line 339 of file dp.h.

◆ PLL_LOCK

#define PLL_LOCK (1 << 4)

Definition at line 326 of file dp.h.

◆ PLL_LOCK_CHG

#define PLL_LOCK_CHG (1 << 6)

Definition at line 242 of file dp.h.

◆ PLL_LOCK_CTRL

#define PLL_LOCK_CTRL (1 << 2)

Definition at line 328 of file dp.h.

◆ PLUG

#define PLUG (1 << 0)

Definition at line 268 of file dp.h.

◆ PN_INV

#define PN_INV (1 << 0)

Definition at line 329 of file dp.h.

◆ PRE_EMPHASIS_SET_SHIFT

#define PRE_EMPHASIS_SET_SHIFT (3)

Definition at line 323 of file dp.h.

◆ PSR_ACTIVE

#define PSR_ACTIVE (1 << 7)

Definition at line 263 of file dp.h.

◆ PSR_INACTIVE

#define PSR_INACTIVE (1 << 6)

Definition at line 264 of file dp.h.

◆ R0_CHK_FLAG

#define R0_CHK_FLAG (1 << 5)

Definition at line 260 of file dp.h.

◆ RESET_DP_TX

#define RESET_DP_TX (1 << 0)

Definition at line 156 of file dp.h.

◆ RPLY_RECEIV

#define RPLY_RECEIV (1 << 1)

Definition at line 273 of file dp.h.

◆ SCRAMBLER_TYPE

#define SCRAMBLER_TYPE (1 << 9)

Definition at line 309 of file dp.h.

◆ SCRAMBLING_DISABLE

#define SCRAMBLING_DISABLE (1 << 5)

Definition at line 311 of file dp.h.

◆ SCRAMBLING_ENABLE

#define SCRAMBLING_ENABLE (0 << 5)

Definition at line 312 of file dp.h.

◆ SERDES_FIFO_FUNC_EN_N

#define SERDES_FIFO_FUNC_EN_N (1 << 1)

Definition at line 170 of file dp.h.

◆ SLAVE_VID_FUNC_EN_N

#define SLAVE_VID_FUNC_EN_N (1 << 5)

Definition at line 160 of file dp.h.

◆ SOFT_INT_CTRL

#define SOFT_INT_CTRL (1 << 2)

Definition at line 279 of file dp.h.

◆ SPDIF_BI_PHASE_ERR

#define SPDIF_BI_PHASE_ERR (1 << 5)

Definition at line 265 of file dp.h.

◆ SPDIF_ERR

#define SPDIF_ERR (1 << 5)

Definition at line 243 of file dp.h.

◆ SPDIF_UNSTBL

#define SPDIF_UNSTBL (1 << 4)

Definition at line 244 of file dp.h.

◆ SSC_FUNC_EN_N

#define SSC_FUNC_EN_N (1 << 7)

Definition at line 168 of file dp.h.

◆ STRM_VALID

#define STRM_VALID (1 << 2)

Definition at line 298 of file dp.h.

◆ SW_FUNC_EN_N

#define SW_FUNC_EN_N (1 << 0)

Definition at line 165 of file dp.h.

◆ SW_INT

#define SW_INT (1 << 0)

Definition at line 248 of file dp.h.

◆ SW_TRAINING_PATTERN_SET_MASK

#define SW_TRAINING_PATTERN_SET_MASK (3 << 0)

Definition at line 317 of file dp.h.

◆ SW_TRAINING_PATTERN_SET_NORMAL

#define SW_TRAINING_PATTERN_SET_NORMAL (0 << 0)

Definition at line 320 of file dp.h.

◆ SW_TRAINING_PATTERN_SET_PTN1

#define SW_TRAINING_PATTERN_SET_PTN1 (1 << 0)

Definition at line 319 of file dp.h.

◆ SW_TRAINING_PATTERN_SET_PTN2

#define SW_TRAINING_PATTERN_SET_PTN2 (2 << 0)

Definition at line 318 of file dp.h.

◆ VALID_CTRL

#define VALID_CTRL (1 << 0)

Definition at line 300 of file dp.h.

◆ VID_CHK_UPDATE_TYPE_0

#define VID_CHK_UPDATE_TYPE_0 (0 << 4)

Definition at line 202 of file dp.h.

◆ VID_CHK_UPDATE_TYPE_1

#define VID_CHK_UPDATE_TYPE_1 (1 << 4)

Definition at line 201 of file dp.h.

◆ VID_CHK_UPDATE_TYPE_MASK

#define VID_CHK_UPDATE_TYPE_MASK (1 << 4)

Definition at line 199 of file dp.h.

◆ VID_CHK_UPDATE_TYPE_SHIFT

#define VID_CHK_UPDATE_TYPE_SHIFT (4)

Definition at line 200 of file dp.h.

◆ VID_CLK_CHG

#define VID_CLK_CHG (1 << 1)

Definition at line 247 of file dp.h.

◆ VID_FORMAT_CHG

#define VID_FORMAT_CHG (1 << 3)

Definition at line 245 of file dp.h.

◆ VIDEO_EN

#define VIDEO_EN (1 << 7)

Definition at line 174 of file dp.h.

◆ VIDEO_MASTER_CLK_SEL

#define VIDEO_MASTER_CLK_SEL (1 << 2)

Definition at line 411 of file dp.h.

◆ VIDEO_MASTER_MODE_EN

#define VIDEO_MASTER_MODE_EN (1 << 1)

Definition at line 412 of file dp.h.

◆ VIDEO_MODE_MASK

#define VIDEO_MODE_MASK (1 << 0)

Definition at line 413 of file dp.h.

◆ VIDEO_MODE_MASTER_MODE

#define VIDEO_MODE_MASTER_MODE (0 << 0)

Definition at line 415 of file dp.h.

◆ VIDEO_MODE_SLAVE_MODE

#define VIDEO_MODE_SLAVE_MODE (1 << 0)

Definition at line 414 of file dp.h.

◆ VSYNC_DET

#define VSYNC_DET (1 << 7)

Definition at line 241 of file dp.h.

◆ VSYNC_POLARITY_CFG

#define VSYNC_POLARITY_CFG (1 << 1)

Definition at line 207 of file dp.h.

Function Documentation

◆ check_member()

check_member	(	exynos5_dp	,
		soc_general_ctl	,
		0x800
	)

◆ clock_init_dp_clock()

void clock_init_dp_clock ( void )

Definition at line 417 of file clock_init.c.

References CLK_DIV_DISP1_0_FIMD1, CLK_GATE_DP1_ALLOW, exynos5_clock::div_disp1_0, exynos_clock, exynos5_clock::gate_ip_disp1, and setbits32.

Referenced by dp_controller_init().

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Variable Documentation

◆ exynos_dp0

struct exynos5_dp* const exynos_dp0 = (void *)EXYNOS5_DP0_BASE

static

Definition at line 152 of file dp.h.

◆ exynos_dp1

struct exynos5_dp* const exynos_dp1 = (void *)EXYNOS5_DP1_BASE