coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smihandler.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <acpi/acpi.h>
4 #include <arch/io.h>
5 #include <console/console.h>
6 #include <cpu/x86/smm.h>
7 #include <soc/nvs.h>
13 #include <elog.h>
14 
15 /* Include EC functions */
16 #include <ec/google/chromeec/ec.h>
17 #include "ec.h"
18 
19 /* Codec enable: GPIO45 */
20 #define GPIO_PP3300_CODEC_EN 45
21 /* GPIO46 controls the WLAN_DISABLE_L signal. */
22 #define GPIO_WLAN_DISABLE_L 46
23 #define GPIO_LTE_DISABLE_L 59
24 
25 static u8 mainboard_smi_ec(void)
26 {
28  u32 pm1_cnt;
29 
30  /* Log this event */
31  if (cmd)
33 
34  switch (cmd) {
36  printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
37 
38  /* Go to S5 */
39  pm1_cnt = inl(get_pmbase() + PM1_CNT);
40  pm1_cnt |= (0xf << 10);
41  outl(pm1_cnt, get_pmbase() + PM1_CNT);
42  break;
43  }
44 
45  return cmd;
46 }
47 
48 /* gpi_sts is GPIO 47:32 */
49 void mainboard_smi_gpi(u32 gpi_sts)
50 {
51  if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
52  /* Process all pending events */
53  while (mainboard_smi_ec() != 0);
54  }
55 }
56 
57 void mainboard_smi_sleep(u8 slp_typ)
58 {
59  /* Disable USB charging if required */
60  switch (slp_typ) {
61  case ACPI_S3:
62  if (gnvs->s3u0 == 0)
65  if (gnvs->s3u1 == 0)
68 
69  /* Prevent leak from standby rail to WLAN rail in S3. */
72  /* Disable LTE */
74 
75  /* Enable wake events */
77  break;
78  case ACPI_S4:
79  case ACPI_S5:
80  if (gnvs->s5u0 == 0)
83  if (gnvs->s5u1 == 0)
86 
87  /* Prevent leak from standby rail to WLAN rail in S5. */
90  /* Disable LTE */
92 
93  /* Enable wake events */
95  break;
96  }
97 
98  /* Disable SCI and SMI events */
101 
102  /* Clear pending events that may trigger immediate wake */
104  ;
105 }
106 
108 {
109  switch (apmc) {
110  case APM_CNT_ACPI_ENABLE:
112  /* Clear all pending events */
114  ;
116  break;
119  /* Clear all pending events */
121  ;
123  break;
124  }
125  return 0;
126 }
#define PM1_CNT
Definition: pm.h:27
#define ELOG_TYPE_EC_EVENT
Definition: elog.h:90
#define printk(level,...)
Definition: stdlib.h:16
void __weak mainboard_smi_sleep(u8 slp_typ)
Definition: smihandler.c:210
int __weak mainboard_smi_apmc(u8 data)
Definition: smihandler.c:209
void __weak mainboard_smi_gpi(u32 gpi_sts)
Definition: smihandler.c:208
u32 inl(u16 port)
void outl(u32 val, u16 port)
int google_chromeec_set_wake_mask(uint64_t mask)
Definition: ec.c:1131
int google_chromeec_set_smi_mask(uint64_t mask)
Definition: ec.c:1125
int google_chromeec_set_usb_charge_mode(uint8_t port_id, enum usb_charge_mode mode)
Definition: ec.c:1143
int google_chromeec_set_sci_mask(uint64_t mask)
Definition: ec.c:1119
enum host_event_code google_chromeec_get_event(void)
Definition: ec_i2c.c:242
@ EC_HOST_EVENT_NONE
Definition: ec_commands.h:654
@ EC_HOST_EVENT_LID_CLOSED
Definition: ec_commands.h:655
@ USB_CHARGE_MODE_DISABLED
Definition: ec_commands.h:3240
@ ACPI_S5
Definition: acpi.h:1385
@ ACPI_S4
Definition: acpi.h:1384
@ ACPI_S3
Definition: acpi.h:1383
#define APM_CNT_ACPI_DISABLE
Definition: smm.h:21
#define APM_CNT_ACPI_ENABLE
Definition: smm.h:22
static int elog_gsmi_add_event_byte(u8 event_type, u8 data)
Definition: elog.h:46
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
#define MAINBOARD_EC_S5_WAKE_EVENTS
Definition: ec.h:32
#define MAINBOARD_EC_SCI_EVENTS
Definition: ec.h:12
#define MAINBOARD_EC_SMI_EVENTS
Definition: ec.h:28
#define EC_SMI_GPI
Definition: ec.h:10
#define MAINBOARD_EC_S3_WAKE_EVENTS
Definition: ec.h:37
static u8 mainboard_smi_ec(void)
Definition: smihandler.c:25
#define GPIO_PP3300_CODEC_EN
Definition: smihandler.c:20
#define GPIO_LTE_DISABLE_L
Definition: smihandler.c:23
#define GPIO_WLAN_DISABLE_L
Definition: smihandler.c:22
struct global_nvs * gnvs
void set_gpio(int gpio_num, int value)
Definition: gpio.c:125
u16 get_pmbase(void)
Definition: smihandler.c:20
uint32_t u32
Definition: stdint.h:51
uint8_t u8
Definition: stdint.h:45
u8 s5u1
Definition: nvs.h:33
u8 s3u0
Definition: nvs.h:34
u8 s3u1
Definition: nvs.h:35
u8 s5u0
Definition: nvs.h:32