3 #define __SIMPLE_DEVICE__
12 #include <soc/iomap.h>
14 #include <soc/pci_devs.h>
17 #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))
112 memset(ep_mask, 0,
sizeof(ep_mask));
#define HPTC_ADDR_ENABLE_BIT
void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
void * memset(void *dstpp, int c, size_t len)
#define PCH_P2SB_EPMASK(mask_number)
union p2sb_bdf p2sb_get_ioapic_bdf(void)
static const struct pci_driver pmc __pci_driver
void p2sb_set_ioapic_bdf(union p2sb_bdf bdf)
static const struct device_operations device_ops
void p2sb_disable_sideband_access(void)
union p2sb_bdf p2sb_get_hpet_bdf(void)
void p2sb_set_hpet_bdf(union p2sb_bdf bdf)
static const unsigned short pci_device_ids[]
void p2sb_enable_bar(void)
void p2sb_configure_hpet(void)
static void p2sb_lock_endpoints(void)
static void read_resources(struct device *dev)
static void p2sb_configure_endpoints(int epmask_id, uint32_t mask)
static void noop_set_resources(struct device *dev)
#define mmio_resource(dev, idx, basek, sizek)
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val)
bool p2sb_dev_is_hidden(pci_devfn_t dev)
void p2sb_dev_unhide(pci_devfn_t dev)
void p2sb_dev_enable_bar(pci_devfn_t dev, uint64_t bar)
void p2sb_dev_hide(pci_devfn_t dev)
#define PCI_BASE_ADDRESS_0
struct pci_operations pci_dev_ops_pci
Default device operation for PCI devices.
#define PCI_DID_INTEL_EHL_P2SB
#define PCI_DID_INTEL_SKL_LP_P2SB
#define PCI_DID_INTEL_GLK_P2SB
#define PCI_DID_INTEL_CNL_P2SB
#define PCI_DID_INTEL_ADP_M_P2SB
#define PCI_DID_INTEL_CMP_P2SB
#define PCI_DID_INTEL_APL_P2SB
#define PCI_DID_INTEL_LWB_P2SB_SUPER
#define PCI_DID_INTEL_KBL_P2SB
#define PCI_DID_INTEL_TGL_P2SB
#define PCI_DID_INTEL_LWB_P2SB
#define PCI_DID_INTEL_ADP_P_P2SB
#define PCI_DID_INTEL_ADP_S_P2SB
#define PCI_DID_INTEL_SKL_P2SB
#define PCI_DID_INTEL_CNP_H_P2SB
#define PCI_DID_INTEL_MTL_SOC_P2SB
#define PCI_DID_INTEL_TGL_H_P2SB
#define PCI_DID_INTEL_JSP_P2SB
#define PCI_DID_INTEL_ICL_P2SB
#define PCI_DID_INTEL_CMP_H_P2SB
static struct tegra_pmc_regs * pmc
void(* read_resources)(struct device *dev)
typedef void(X86APIP X86EMU_intrFuncs)(int num)