dmc_init_ddr3.c File Reference

#include <device/mmio.h>
#include <delay.h>
#include <soc/clk.h>
#include <soc/dmc.h>
#include <soc/power.h>
#include <soc/setup.h>

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Macros
#define	TIMEOUT   10000

Functions
int	ddr3_mem_ctrl_init (struct mem_timings *mem, int interleave_size, int reset)

Macro Definition Documentation

TIMEOUT

#define TIMEOUT   10000

Definition at line 11 of file dmc_init_ddr3.c.

Function Documentation

ddr3_mem_ctrl_init()

int ddr3_mem_ctrl_init	(	struct mem_timings *	mem,
		int	interleave_size,
		int	reset
	)

Definition at line 15 of file dmc_init_ddr3.c.

References mem_timings::aref_en, exynos5_clock::bpll_con1, BPLL_SEL_MASK, BYPASS_EN, CA_ADR_DRVR_DS_OFFSET, CA_CK_DRVR_DS_OFFSET, CA_CKE_DRVR_DS_OFFSET, CA_CS_DRVR_DS_OFFSET, exynos5_dmc::cgcontrol, chip, mem_timings::chips_per_channel, mem_timings::chips_to_configure, clrbits32, exynos5_dmc::concontrol, mem_timings::concontrol, CONCONTROL_AREF_EN_SHIFT, CONCONTROL_DFI_INIT_START_SHIFT, CONCONTROL_RD_FETCH_SHIFT, mem_timings::ctrl_bstlen, CTRL_DLL_ON, CTRL_GATEDURADJ_MASK, CTRL_LOCK_COARSE_MASK, mem_timings::ctrl_rdlat, CTRL_RDLVL_GATE_DISABLE, CTRL_RDLVL_GATE_ENABLE, CTRL_SHGATE, DA_0_DS_OFFSET, DA_1_DS_OFFSET, DA_2_DS_OFFSET, DA_3_DS_OFFSET, DFI_INIT_COMPLETE, DFI_INIT_START, mem_timings::dfi_init_start, DIRECT_CMD_BANK_SHIFT, DIRECT_CMD_CHIP_SHIFT, DIRECT_CMD_REFA, exynos5_dmc::directcmd, DLL_DESKEW_EN, DMC_CONCONTROL_IO_PD_CON, dmc_config_mrs(), dmc_config_prech(), dmc_config_zq(), DMC_INTERNAL_CG, ENABLE_BIT, exynos_clock, exynos_drex0, exynos_drex1, exynos_phy0_control, exynos_phy1_control, exynos_power, exynos_tzasc0, exynos_tzasc1, FOUTBPLL, mem_timings::gate_leveling_enable, INIT_DESKEW_EN, MEM_TERM_EN, mem_timings::mem_type, mem_timings::membaseconfig0, exynos5_tzasc::membaseconfig0, mem_timings::membaseconfig1, exynos5_tzasc::membaseconfig1, mem_timings::memconfig, exynos5_tzasc::memconfig0, exynos5_tzasc::memconfig1, exynos5_dmc::memcontrol, mem_timings::memcontrol, MUX_BPLL_SEL_FOUTBPLL, P0_CMD_EN, PAD_RETENTION_DRAM_COREBLK_VAL, exynos5_power::padret_dram_cblk_opt, exynos5_power::padret_dram_status, mem_timings::phy0_pulld_dqs, mem_timings::phy1_pulld_dqs, exynos5_phy_control::phy_con0, PHY_CON0_CTRL_DDR_MODE_MASK, PHY_CON0_CTRL_DDR_MODE_SHIFT, PHY_CON0_RESET_VAL, exynos5_phy_control::phy_con1, exynos5_phy_control::phy_con12, PHY_CON12_RESET_VAL, exynos5_phy_control::phy_con13, exynos5_phy_control::phy_con14, exynos5_phy_control::phy_con16, exynos5_phy_control::phy_con2, exynos5_phy_control::phy_con26, PHY_CON2_RESET_VAL, exynos5_phy_control::phy_con39, exynos5_phy_control::phy_con42, PHY_CON42_CTRL_BSTLEN_SHIFT, PHY_CON42_CTRL_RDLAT_SHIFT, PHY_TERM_EN, exynos5_dmc::phycontrol0, exynos5_dmc::phystatus, exynos5_dmc::prechconfig0, mem_timings::prechconfig_tp_cnt, PRECHCONFIG_TP_CNT_SHIFT, mem_timings::rd_fetch, RDLVL_COMPLETE_CHO, exynos5_dmc::rdlvl_config, RDLVL_GATE_EN, RDLVL_PASS_ADJ_OFFSET, RDLVL_PASS_ADJ_VAL, read32(), reset(), setbits32, SETUP_ERR_RDLV_COMPLETE_TIMEOUT, SETUP_ERR_ZQ_CALIBRATION_FAILURE, T_WRDATA_EN_DDR3, T_WRDATA_EN_MASK, T_WRDATA_EN_OFFSET, TIMEOUT, mem_timings::timing_data, mem_timings::timing_power, mem_timings::timing_ref, mem_timings::timing_row, exynos5_dmc::timingdata, exynos5_dmc::timingpower, exynos5_dmc::timingref, exynos5_dmc::timingrow, udelay(), update_reset_dll(), val, write32(), and ZQ_CLK_DIV_EN.

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