coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <types.h>
6 #include <vendorcode/google/chromeos/chromeos.h>
7 
8 /* Pad configuration in ramstage */
9 /* Leave eSPI pins untouched from default settings */
10 static const struct pad_config gpio_table[] = {
11 /* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */
12 /* ESPI_IO0 */
13 /* ESPI_IO1 */
14 /* ESPI_IO2 */
15 /* ESPI_IO3 */
16 /* ESPI_CS# */
17 /* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */
18 /* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, UP_20K, DEEP,
19  EDGE_SINGLE), /* SD_CDZ */
20 /* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */
21 /* ESPI_CLK */
22 /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */
23 /* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */
24 /* BM_BUSY# */ PAD_NC(GPP_A12, NONE),
25 /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,
26  DEEP), /* eSPI mode */
27 /* ESPI_RESET# */
28 /* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */
29 /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
30 /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
31 /* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */
32 /* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */
33 /* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
34 /* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
35 /* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
36 /* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
37 
38 /* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */
39 /* CORE_VID1 */ PAD_NC(GPP_B1, NONE),
40 /* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */
41 /* CPU_GP2 */ PAD_NC(GPP_B3, NONE),
42 /* CPU_GP3 */ PAD_NC(GPP_B4, NONE),
43 /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP,
44  NF1), /* CLK_PCIE_LAN_REQ# */
45 /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP,
46  NF1), /* PCIE_CLKREQ_SSD# */
47 /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP,
48  NF1), /* PCIE_CLKREQ_NGFF1# */
49 /* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* TP333 */
50 /* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), /* TP139 */
51 /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP,
52  NF1), /* PCIE_CLKREQ_WLAN# */
53 /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */
54 /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */
55 /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */
56 /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */
57 /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,
58  NF1), /* PCH_SPI_H1_3V3_CS_L */
59 /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,
60  NF1), /* PCH_SPI_H1_3V3_CLK */
61 /* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
62  NF1), /* PCH_SPI_H1_3V3_MISO */
63 /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
64  NF1), /* PCH_SPI_H1_3V3_MOSI */
65 /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP111 */
66 /* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, UP_20K,
67  DEEP), /* VR_DISABLE_L */
68 /* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, UP_20K,
69  DEEP), /* HWA_TRST_N */
70 /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */
71 /* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP141 */
72 
73 /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */
74 /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */
75 /* SMBALERT# */ PAD_NC(GPP_C2, NONE),
76 /* SML0CLK */ PAD_NC(GPP_C3, NONE),
77 /* SML0DATA */ PAD_NC(GPP_C4, NONE),
78 /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
79 /* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K,
80  DEEP), /* EC_IN_RW */
81 /* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP310 */
82 /* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, UP_20K,
83  DEEP), /* GPIO1 */
84 /* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, UP_20K,
85  DEEP), /* GPIO2 */
86 /* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, UP_20K,
87  DEEP), /* GPIO3 */
88 /* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, UP_20K,
89  DEEP), /* GPIO4 */
90 /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
91  DEEP), /* SKU_ID0 */
92 /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
93  DEEP), /* SKU_ID1 */
94 /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,
95  DEEP), /* SKU_ID2 */
96 /* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
97  DEEP), /* SKU_ID3 */
98 /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
99 /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
100 /* I2C1_SDA */ PAD_NC(GPP_C18, NONE),
101 /* I2C1_SCL */ PAD_NC(GPP_C19, NONE),
102 /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
103 /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
104 /* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP309 */
105 /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
106  DEEP), /* SCREW_SPI_WP_STATUS */
107 
108 /* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP259 */
109 /* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP260 */
110 /* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP261 */
111 /* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP262 */
112 /* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP153 */
113 /* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
114 /* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
115 /* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),
116 /* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
117 /* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE,
118  PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */
119 /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE,
120  DEEP), /* OEM_ID1 */
121 /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE,
122  DEEP), /* OEM_ID2 */
123 /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE,
124  DEEP), /* OEM_ID3 */
125 /* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
126 /* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
127 /* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE),
128 /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),
129 /* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE),
130 /* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE),
131 /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* TP121 */
132 /* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), /* TP122 */
133 /* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP257 */
134 /* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), /* TP258 */
135 /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */
136 
137 /* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL,
138  INVERT), /* H1_PCH_INT_ODL */
139 /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,
140  NF1), /* MB_PCIE_SATA#_DET */
141 /* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP,
142  NF1), /* DB_PCIE_SATA#_DET */
143 /* CPU_GP0 */ PAD_NC(GPP_E3, NONE),
144 /* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */
145 /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
146 /* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */
147 /* CPU_GP1 */ PAD_NC(GPP_E7, NONE),
148 /* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP314 */
149 /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */
150 /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP,
151  NF1), /* Rear Dual-Stack USB Ports */
152 /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,
153  NF1), /* Front USB Ports */
154 /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,
155  NF1), /* Rear Single USB Port */
156 /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,
157  NF1), /* INT_HDMI_HPD */
158 /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,
159  NF1), /* DDI2_HPD */
160 /* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP325 */
161 /* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP326 */
162 /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
163 /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP,
164  NF1), /* HDMI_DDCCLK_SW */
165 /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP,
166  NF1), /* HDMI_DDCCLK_DATA */
167 /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */
168 /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */
169 /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
170 /* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
171 
172 /* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), /* TP191 */
173 /* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), /* TP192 */
174 /* I2S2_TXD */ PAD_NC(GPP_F2, NONE), /* TP190 */
175 /* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP189 */
176 /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP,
177  NF1), /* PCH_I2C2_H1_3V3_SDA */
178 /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP,
179  NF1), /* PCH_I2C2_H1_3V3_SCL */
180 /* I2C3_SDA */ PAD_NC(GPP_F6, NONE),
181 /* I2C3_SCL */ PAD_NC(GPP_F7, NONE),
182 /* I2C4_SDA */ PAD_NC(GPP_F8, NONE),
183 /* I2C4_SCL */ PAD_NC(GPP_F9, NONE),
184 /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP,
185  NF1), /* PCH_I2C2_AUDIO_1V8_SDA */
186 /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP,
187  NF1), /* PCH_I2C2_AUDIO_1V8_SCL */
188 /* EMMC_CMD */ PAD_NC(GPP_F12, NONE),
189 /* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE),
190 /* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE),
191 /* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE),
192 /* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE),
193 /* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE),
194 /* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE),
195 /* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE),
196 /* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE),
197 /* EMMC_RCLK */ PAD_NC(GPP_F21, NONE),
198 /* EMMC_CLK */ PAD_NC(GPP_F22, NONE),
199 /* RSVD */ PAD_NC(GPP_F23, NONE),
200 
201 /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
202 /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
203 /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
204 /* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
205 /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
206 /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */
207 /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
208 /* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP292 */
209 
210 /* BATLOW# */ PAD_NC(GPD0, NONE), /* TP148 */
211 /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */
212 /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */
213 /* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */
214 /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */
215 /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */
216 /* SLP_A# */ PAD_NC(GPD6, NONE), /* TP147 */
217 /* RSVD */ PAD_NC(GPD7, NONE),
218 /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */
219 /* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP146 */
220 /* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP143 */
221 /* LANPHYC */ PAD_NC(GPD11, NONE),
222 };
223 
224 /* Early pad configuration in bootblock */
225 static const struct pad_config early_gpio_table[] = {
226 /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,
227  NF1), /* PCH_SPI_H1_3V3_CS_L */
228 /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,
229  NF1), /* PCH_SPI_H1_3V3_CLK */
230 /* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
231  NF1), /* PCH_SPI_H1_3V3_MISO */
232 /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
233  NF1), /* PCH_SPI_H1_3V3_MOSI */
234 /* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL,
235  INVERT), /* H1_PCH_INT_ODL */
236 /* Ensure UART pins are in native mode for H1. */
237 /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
238 /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
239 /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
240  DEEP), /* SCREW_SPI_WP_STATUS */
241 /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,
242  NF1), /* MB_PCIE_SATA#_DET */
243 /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
244 
245 /* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K,
246  DEEP), /* EC_IN_RW */
247 };
248 
249 const struct pad_config * __weak variant_gpio_table(size_t *num)
250 {
251  *num = ARRAY_SIZE(gpio_table);
252  return gpio_table;
253 }
254 
255 const struct pad_config * __weak
256  variant_early_gpio_table(size_t *num)
257 {
258  *num = ARRAY_SIZE(early_gpio_table);
259  return early_gpio_table;
260 }
261 
262 static const struct cros_gpio cros_gpios[] = {
263  CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
264  CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
265 };
266 
267 DECLARE_WEAK_CROS_GPIOS(cros_gpios);
GPD11
#define GPD11
Definition: gpio_soc_defs.h:392
GPP_C15
#define GPP_C15
Definition: gpio_soc_defs.h:552
GPD3
#define GPD3
Definition: gpio_soc_defs.h:384
GPP_B6
#define GPP_B6
Definition: gpio_soc_defs.h:59
GPP_D1
#define GPP_D1
Definition: gpio_soc_defs.h:253
GPD9
#define GPD9
Definition: gpio_soc_defs.h:390
GPP_C2
#define GPP_C2
Definition: gpio_soc_defs.h:539
GPP_D10
#define GPP_D10
Definition: gpio_soc_defs.h:262
GPP_D8
#define GPP_D8
Definition: gpio_soc_defs.h:260
GPP_D17
#define GPP_D17
Definition: gpio_soc_defs.h:269
GPP_E3
#define GPP_E3
Definition: gpio_soc_defs.h:631
GPP_A18
#define GPP_A18
Definition: gpio_soc_defs.h:137
GPP_F21
#define GPP_F21
Definition: gpio_soc_defs.h:594
GPP_C12
#define GPP_C12
Definition: gpio_soc_defs.h:549
GPP_F12
#define GPP_F12
Definition: gpio_soc_defs.h:585
GPP_F16
#define GPP_F16
Definition: gpio_soc_defs.h:589
GPP_E0
#define GPP_E0
Definition: gpio_soc_defs.h:628
GPP_F6
#define GPP_F6
Definition: gpio_soc_defs.h:579
GPP_D14
#define GPP_D14
Definition: gpio_soc_defs.h:266
GPP_B1
#define GPP_B1
Definition: gpio_soc_defs.h:54
GPP_F20
#define GPP_F20
Definition: gpio_soc_defs.h:593
GPP_F23
#define GPP_F23
Definition: gpio_soc_defs.h:596
GPP_C5
#define GPP_C5
Definition: gpio_soc_defs.h:542
GPP_B12
#define GPP_B12
Definition: gpio_soc_defs.h:65
GPP_D12
#define GPP_D12
Definition: gpio_soc_defs.h:264
GPP_B16
#define GPP_B16
Definition: gpio_soc_defs.h:69
GPP_B2
#define GPP_B2
Definition: gpio_soc_defs.h:55
GPP_D7
#define GPP_D7
Definition: gpio_soc_defs.h:259
GPP_B13
#define GPP_B13
Definition: gpio_soc_defs.h:66
GPP_E6
#define GPP_E6
Definition: gpio_soc_defs.h:634
GPP_F0
#define GPP_F0
Definition: gpio_soc_defs.h:573
GPP_D6
#define GPP_D6
Definition: gpio_soc_defs.h:258
GPP_A19
#define GPP_A19
Definition: gpio_soc_defs.h:138
GPP_D2
#define GPP_D2
Definition: gpio_soc_defs.h:254
GPP_C9
#define GPP_C9
Definition: gpio_soc_defs.h:546
GPP_C22
#define GPP_C22
Definition: gpio_soc_defs.h:559
GPD0
#define GPD0
Definition: gpio_soc_defs.h:380
GPP_D9
#define GPP_D9
Definition: gpio_soc_defs.h:261
GPP_F5
#define GPP_F5
Definition: gpio_soc_defs.h:578
GPP_B15
#define GPP_B15
Definition: gpio_soc_defs.h:68
GPP_E13
#define GPP_E13
Definition: gpio_soc_defs.h:641
GPP_C23
#define GPP_C23
Definition: gpio_soc_defs.h:560
GPP_C8
#define GPP_C8
Definition: gpio_soc_defs.h:545
GPP_D11
#define GPP_D11
Definition: gpio_soc_defs.h:263
GPP_A6
#define GPP_A6
Definition: gpio_soc_defs.h:125
GPP_C11
#define GPP_C11
Definition: gpio_soc_defs.h:548
GPP_D5
#define GPP_D5
Definition: gpio_soc_defs.h:257
GPP_B22
#define GPP_B22
Definition: gpio_soc_defs.h:75
GPP_A23
#define GPP_A23
Definition: gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition: gpio_soc_defs.h:555
GPP_F9
#define GPP_F9
Definition: gpio_soc_defs.h:582
GPP_C13
#define GPP_C13
Definition: gpio_soc_defs.h:550
GPP_E14
#define GPP_E14
Definition: gpio_soc_defs.h:642
GPP_E23
#define GPP_E23
Definition: gpio_soc_defs.h:651
GPP_E9
#define GPP_E9
Definition: gpio_soc_defs.h:637
GPP_C17
#define GPP_C17
Definition: gpio_soc_defs.h:554
GPP_E8
#define GPP_E8
Definition: gpio_soc_defs.h:636
GPP_A7
#define GPP_A7
Definition: gpio_soc_defs.h:126
GPP_E5
#define GPP_E5
Definition: gpio_soc_defs.h:633
GPP_A0
#define GPP_A0
Definition: gpio_soc_defs.h:119
GPD7
#define GPD7
Definition: gpio_soc_defs.h:388
GPP_B8
#define GPP_B8
Definition: gpio_soc_defs.h:61
GPP_C20
#define GPP_C20
Definition: gpio_soc_defs.h:557
GPP_B20
#define GPP_B20
Definition: gpio_soc_defs.h:73
GPP_A20
#define GPP_A20
Definition: gpio_soc_defs.h:139
GPP_A16
#define GPP_A16
Definition: gpio_soc_defs.h:135
GPP_F1
#define GPP_F1
Definition: gpio_soc_defs.h:574
GPP_F17
#define GPP_F17
Definition: gpio_soc_defs.h:590
GPP_A12
#define GPP_A12
Definition: gpio_soc_defs.h:131
GPP_F15
#define GPP_F15
Definition: gpio_soc_defs.h:588
GPP_D4
#define GPP_D4
Definition: gpio_soc_defs.h:256
GPP_C10
#define GPP_C10
Definition: gpio_soc_defs.h:547
GPP_C6
#define GPP_C6
Definition: gpio_soc_defs.h:543
GPD2
#define GPD2
Definition: gpio_soc_defs.h:383
GPP_F10
#define GPP_F10
Definition: gpio_soc_defs.h:583
GPP_E7
#define GPP_E7
Definition: gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition: gpio_soc_defs.h:553
GPP_F7
#define GPP_F7
Definition: gpio_soc_defs.h:580
GPD1
#define GPD1
Definition: gpio_soc_defs.h:382
GPP_F13
#define GPP_F13
Definition: gpio_soc_defs.h:586
GPP_C4
#define GPP_C4
Definition: gpio_soc_defs.h:541
GPP_D18
#define GPP_D18
Definition: gpio_soc_defs.h:270
GPP_B19
#define GPP_B19
Definition: gpio_soc_defs.h:72
GPP_E17
#define GPP_E17
Definition: gpio_soc_defs.h:645
GPP_E2
#define GPP_E2
Definition: gpio_soc_defs.h:630
GPP_E19
#define GPP_E19
Definition: gpio_soc_defs.h:647
GPP_C21
#define GPP_C21
Definition: gpio_soc_defs.h:558
GPP_B9
#define GPP_B9
Definition: gpio_soc_defs.h:62
GPD10
#define GPD10
Definition: gpio_soc_defs.h:391
GPP_E18
#define GPP_E18
Definition: gpio_soc_defs.h:646
GPP_F14
#define GPP_F14
Definition: gpio_soc_defs.h:587
GPP_F4
#define GPP_F4
Definition: gpio_soc_defs.h:577
GPP_A10
#define GPP_A10
Definition: gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition: gpio_soc_defs.h:127
GPP_D0
#define GPP_D0
Definition: gpio_soc_defs.h:252
GPP_B14
#define GPP_B14
Definition: gpio_soc_defs.h:67
GPP_B11
#define GPP_B11
Definition: gpio_soc_defs.h:64
GPP_D13
#define GPP_D13
Definition: gpio_soc_defs.h:265
GPP_B18
#define GPP_B18
Definition: gpio_soc_defs.h:71
GPP_B5
#define GPP_B5
Definition: gpio_soc_defs.h:58
GPP_B0
#define GPP_B0
Definition: gpio_soc_defs.h:53
GPP_A11
#define GPP_A11
Definition: gpio_soc_defs.h:130
GPP_C14
#define GPP_C14
Definition: gpio_soc_defs.h:551
GPP_E20
#define GPP_E20
Definition: gpio_soc_defs.h:648
GPP_A15
#define GPP_A15
Definition: gpio_soc_defs.h:134
GPP_E10
#define GPP_E10
Definition: gpio_soc_defs.h:638
GPP_F8
#define GPP_F8
Definition: gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition: gpio_soc_defs.h:556
GPD8
#define GPD8
Definition: gpio_soc_defs.h:389
GPP_A13
#define GPP_A13
Definition: gpio_soc_defs.h:132
GPP_A21
#define GPP_A21
Definition: gpio_soc_defs.h:140
GPP_B23
#define GPP_B23
Definition: gpio_soc_defs.h:76
GPP_E15
#define GPP_E15
Definition: gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition: gpio_soc_defs.h:63
GPP_E16
#define GPP_E16
Definition: gpio_soc_defs.h:644
GPP_D19
#define GPP_D19
Definition: gpio_soc_defs.h:271
GPP_C1
#define GPP_C1
Definition: gpio_soc_defs.h:538
GPP_F2
#define GPP_F2
Definition: gpio_soc_defs.h:575
GPP_E11
#define GPP_E11
Definition: gpio_soc_defs.h:639
GPD6
#define GPD6
Definition: gpio_soc_defs.h:387
GPP_F18
#define GPP_F18
Definition: gpio_soc_defs.h:591
GPP_B3
#define GPP_B3
Definition: gpio_soc_defs.h:56
GPP_A22
#define GPP_A22
Definition: gpio_soc_defs.h:141
GPP_F22
#define GPP_F22
Definition: gpio_soc_defs.h:595
GPP_D15
#define GPP_D15
Definition: gpio_soc_defs.h:267
GPP_F11
#define GPP_F11
Definition: gpio_soc_defs.h:584
GPP_B21
#define GPP_B21
Definition: gpio_soc_defs.h:74
GPD4
#define GPD4
Definition: gpio_soc_defs.h:385
GPP_B4
#define GPP_B4
Definition: gpio_soc_defs.h:57
GPP_D16
#define GPP_D16
Definition: gpio_soc_defs.h:268
GPP_F3
#define GPP_F3
Definition: gpio_soc_defs.h:576
GPP_E22
#define GPP_E22
Definition: gpio_soc_defs.h:650
GPP_E21
#define GPP_E21
Definition: gpio_soc_defs.h:649
GPP_C3
#define GPP_C3
Definition: gpio_soc_defs.h:540
GPP_E12
#define GPP_E12
Definition: gpio_soc_defs.h:640
GPP_A17
#define GPP_A17
Definition: gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition: gpio_soc_defs.h:70
GPP_E4
#define GPP_E4
Definition: gpio_soc_defs.h:632
GPP_C0
#define GPP_C0
Definition: gpio_soc_defs.h:537
GPD5
#define GPD5
Definition: gpio_soc_defs.h:386
GPP_E1
#define GPP_E1
Definition: gpio_soc_defs.h:629
GPP_F19
#define GPP_F19
Definition: gpio_soc_defs.h:592
GPP_B7
#define GPP_B7
Definition: gpio_soc_defs.h:60
GPP_C7
#define GPP_C7
Definition: gpio_soc_defs.h:544
GPP_D3
#define GPP_D3
Definition: gpio_soc_defs.h:255
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition: helpers.h:12
GPP_D23
#define GPP_D23
Definition: gpio_soc_defs.h:133
GPP_G1
#define GPP_G1
Definition: gpio_soc_defs.h:89
GPP_G7
#define GPP_G7
Definition: gpio_soc_defs.h:95
GPP_D22
#define GPP_D22
Definition: gpio_soc_defs.h:132
GPP_G4
#define GPP_G4
Definition: gpio_soc_defs.h:92
GPP_G2
#define GPP_G2
Definition: gpio_soc_defs.h:90
GPP_D21
#define GPP_D21
Definition: gpio_soc_defs.h:131
GPP_G6
#define GPP_G6
Definition: gpio_soc_defs.h:94
GPP_G0
#define GPP_G0
Definition: gpio_soc_defs.h:88
GPP_D20
#define GPP_D20
Definition: gpio_soc_defs.h:130
GPP_G3
#define GPP_G3
Definition: gpio_soc_defs.h:91
GPP_G5
#define GPP_G5
Definition: gpio_soc_defs.h:93
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition: gpio.c:204
variant_gpio_table
const struct pad_config *__weak variant_gpio_table(size_t *num)
Definition: gpio.c:406
DECLARE_WEAK_CROS_GPIOS
DECLARE_WEAK_CROS_GPIOS(cros_gpios)
GPIO_PCH_WP
#define GPIO_PCH_WP
Definition: gpio.h:14
gpio_table
static const struct pad_config gpio_table[]
Definition: gpio.c:10
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition: gpio.c:225
cros_gpios
static const struct cros_gpio cros_gpios[]
Definition: gpio.c:262
NONE
@ NONE
Definition: qup_se_handlers_common.h:196
__weak
const struct smm_save_state_ops *legacy_ops __weak
Definition: save_state.c:8
PAD_NC
#define PAD_NC(pin)
Definition: gpio_defs.h:263
CROS_GPIO_DEVICE_NAME
#define CROS_GPIO_DEVICE_NAME
Definition: gpio.h:14
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition: gpio_defs.h:197
PAD_CFG_GPI_INT
#define PAD_CFG_GPI_INT(pad, pull, rst, trig)
Definition: gpio_defs.h:348
PAD_CFG_GPI_APIC
#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv)
Definition: gpio_defs.h:376
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition: gpio_defs.h:247
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition: gpio_defs.h:323
pad_config
Definition: gpio.h:75