coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/stages.h>
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#include <
soc/usb/usb_common.h
>
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#include <
soc/qclib_common.h
>
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#include "
board.h
"
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#include <
soc/shrm.h
>
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static
void
prepare_usb
(
void
)
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{
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/*
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* Do DWC3 core and phy reset. Kick these resets
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* off early so they get at least 1ms to settle.
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*/
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reset_usb0
();
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}
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void
platform_romstage_main
(
void
)
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{
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shrm_fw_load_reset
();
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/* QCLib: DDR init & train */
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qclib_load_and_run
();
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prepare_usb
();
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/* This rail needs to be stable by the time we take the FPMCU out of
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reset in ramstage, so already turn it on here. This needs to happen
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at least 200ms after this pin was first driven low in the bootblock. */
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if
(
CONFIG
(HEROBRINE_HAS_FINGERPRINT))
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gpio_output
(
GPIO_EN_FP_RAILS
, 1);
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}
platform_romstage_main
__weak void platform_romstage_main(void)
Definition:
romstage.c:10
CONFIG
@ CONFIG
Definition:
dsi_common.h:201
GPIO_EN_FP_RAILS
#define GPIO_EN_FP_RAILS
Definition:
board.h:49
gpio_output
void gpio_output(gpio_t gpio, int value)
Definition:
gpio.c:194
prepare_usb
static void prepare_usb(void)
Definition:
romstage.c:9
board.h
qclib_common.h
qclib_load_and_run
void qclib_load_and_run(void)
Definition:
qclib.c:152
usb_common.h
reset_usb0
void reset_usb0(void)
Definition:
usb.c:75
shrm.h
shrm_fw_load_reset
void shrm_fw_load_reset(void)
Definition:
shrm_load_reset.c:13
src
mainboard
google
herobrine
romstage.c
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