coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
usb.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <device/mmio.h>
5 #include <soc/usb/usb_common.h>
6 #include <soc/addressmap.h>
7 #include <soc/clock.h>
8 
9 struct usb_dwc3 {
35  u8 reserved2[112];
37  u8 reserved3[124];
42 };
43 check_member(usb_dwc3, usb2phycfg, 0x100);
44 check_member(usb_dwc3, usb3pipectl, 0x1c0);
45 
46 struct usb_dwc3_cfg {
52 };
53 
54 static struct usb_dwc3_cfg usb_port0 = {
56  .usb3_bcr = &gcc->usb30_prim_bcr,
57  .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr,
58  .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr,
59  .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr,
60 };
61 
62 static void reset_usb(struct usb_dwc3_cfg *dwc3)
63 {
64  /* Assert Core reset */
65  clock_reset_bcr(dwc3->usb3_bcr, 1);
66 
67  /* Assert HS PHY reset */
68  clock_reset_bcr(dwc3->qusb2phy_bcr, 1);
69 
70  /* Assert QMP PHY reset */
73 }
74 
75 void reset_usb0(void)
76 {
77  /* Before Resetting PHY, put Core in Reset */
78  printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n");
79 
81 }
82 
83 static void setup_dwc3(struct usb_dwc3 *dwc3)
84 {
85  /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
89 
90  /*
91  * Configure USB phy interface of DWC3 core.
92  * 1. Select UTMI+ PHY with 16-bit interface.
93  * 2. Set USBTRDTIM to the corresponding value
94  * according to the UTMI+ PHY interface.
95  */
96  clrsetbits32(&dwc3->usb2phycfg,
101 
105 
106  /* configure controller in Host mode */
109  printk(BIOS_SPEW, "Configure USB in Host mode\n");
110 }
111 
112 /* Initialization of DWC3 Core and PHY */
113 
114 static void setup_usb_host(struct usb_dwc3_cfg *dwc3,
115  void *board_data)
116 {
117  /* Clear core reset. */
118  clock_reset_bcr(dwc3->usb3_bcr, 0);
119 
120  /* Clear QUSB PHY reset. */
121  clock_reset_bcr(dwc3->qusb2phy_bcr, 0);
122 
123  /* Initialize HS PHY */
125 
126  /* Clear QMP PHY resets. */
129 
130  /* Initialize QMP PHY */
131  ss_qmp_phy_init();
132 
133  setup_dwc3(dwc3->usb_host_dwc3);
134 
135  printk(BIOS_INFO, "DWC3 and PHY setup finished\n");
136 }
138 {
139  printk(BIOS_INFO, "Setting up USB HOST0 controller.\n");
141 }
#define printk(level,...)
Definition: stdlib.h:16
#define clrsetbits32(addr, clear, set)
Definition: mmio.h:16
#define BIOS_INFO
BIOS_INFO - Expected events.
Definition: loglevel.h:113
#define BIOS_SPEW
BIOS_SPEW - Excessively verbose output.
Definition: loglevel.h:142
void ss_qmp_phy_init(void)
#define DWC3_GUSB3PIPECTL_DELAYP1TRANS
Definition: usb_common.h:11
#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK
Definition: usb_common.h:19
#define UTMI_PHYIF_8_BIT
Definition: usb_common.h:23
#define DWC3_GCTL_PRTCAP_HOST
Definition: usb_common.h:15
#define USBTRDTIM_UTMI_8_BIT
Definition: usb_common.h:22
#define DWC3_GUSB2PHYCFG_USBTRDTIM(n)
Definition: usb_common.h:18
#define DWC3_GUSB2PHYCFG_PHYIF(n)
Definition: usb_common.h:20
#define DWC3_GCTL_U2EXIT_LFPS
Definition: usb_common.h:28
#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX
Definition: usb_common.h:12
#define DWC3_GUSB2PHYCFG_PHYIF_MASK
Definition: usb_common.h:21
void setup_usb_host(void)
Definition: usb.c:153
check_member(utmip_ctlr, pmc_wakeup, 0x84c - 0x800)
void clock_reset_bcr(void *bcr_addr, bool assert)
Definition: clock.c:54
static void reset_usb(struct usb_dwc3_cfg *dwc3)
Definition: usb.c:62
void reset_usb0(void)
Definition: usb.c:75
static void setup_dwc3(struct usb_dwc3 *dwc3)
Definition: usb.c:83
void setup_usb_host0(void *board_data)
Definition: usb.c:137
static struct usb_dwc3_cfg usb_port0
Definition: usb.c:54
#define DWC3_GCTL_PRTCAP_OTG
Definition: usb.c:42
#define DWC3_GCTL_SCALEDOWN_MASK
Definition: usb.c:54
#define DWC3_GCTL_DISSCRAMBLE
Definition: usb.c:55
#define DWC3_GCTL_DSBLCLKGTNG
Definition: usb.c:56
#define DWC3_GCTL_PRTCAPDIR(n)
Definition: usb.c:41
static struct qcs405_gcc *const gcc
Definition: clock.h:165
static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3)
Definition: usb.c:146
#define USB_HOST_DWC3_BASE
Definition: addressmap.h:47
uint64_t u64
Definition: stdint.h:54
uint32_t u32
Definition: stdint.h:51
uint8_t u8
Definition: stdint.h:45
struct usb_board_data * board_data
Definition: usb.c:94
struct usb_dwc3 * usb_host_dwc3
Definition: usb.c:47
u32 * usb3_bcr
Definition: usb.c:48
u32 * gcc_usb3phy_bcr_reg
Definition: usb.c:50
u32 * qusb2phy_bcr
Definition: usb.c:49
u32 * gcc_qmpphy_bcr_reg
Definition: usb.c:51
Definition: usb.c:9
u32 usb2phycfg
Definition: usb.c:36
u8 reserved4[60]
Definition: usb.c:39
u32 sts
Definition: usb.c:16
u64 prtbimap_fs
Definition: usb.c:34
u64 buserraddr
Definition: usb.c:22
u32 dbgfifospace
Definition: usb.c:25
u32 txthrcfg
Definition: usb.c:12
u32 dbgltssm
Definition: usb.c:26
u32 dbgbmu
Definition: usb.c:28
u32 uctl1
Definition: usb.c:17
u32 sbuscfg1
Definition: usb.c:11
u32 uctl
Definition: usb.c:21
u32 gpio
Definition: usb.c:19
u32 uid
Definition: usb.c:20
u64 prtbimap
Definition: usb.c:23
u32 rxthrcfg
Definition: usb.c:13
u64 prtbimap_hs
Definition: usb.c:33
u32 ctl
Definition: usb.c:14
u32 pmsts
Definition: usb.c:15
u32 dbgepinfo1
Definition: usb.c:32
u32 dbglspmux
Definition: usb.c:29
u32 dbglnmcc
Definition: usb.c:27
u32 usb3pipectl
Definition: usb.c:40
u8 reserved5[60]
Definition: usb.c:41
u32 dbgepinfo0
Definition: usb.c:31
u8 reserved1[32]
Definition: usb.c:24
u32 dbglsp
Definition: usb.c:30
u32 usb2phyacc
Definition: usb.c:38
u32 snpsid
Definition: usb.c:18
u32 sbuscfg0
Definition: usb.c:10
u8 reserved3[124]
Definition: usb.c:37
u8 reserved2[112]
Definition: usb.c:35