coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/gpio.h>
4 #include <intelblocks/gpio.h>
5 #include <intelblocks/pcr.h>
6 #include <soc/pcr_ids.h>
7 #include <soc/pm.h>
8 
9 /*
10  * Reset mapping for Lewisburg PCH. See page 428, Intel Doc #336067-007US
11  * 00 = RSMRST#
12  * 01 = Host Deep Reset
13  * 10 = PLTRST#
14  * 11 = Reserved
15  */
16 static const struct reset_mapping rst_map[] = {
17  { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
18  { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
19  { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
20 };
21 
22 static const struct pad_group lewisburg_community0_groups[] = {
23  INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */
24  INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */
25  INTEL_GPP(GPP_A0, GPP_F0, GPP_F23), /* GPP F */
26 };
27 
28 static const struct pad_group lewisburg_community1_groups[] = {
29  INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP C */
30  INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */
31  INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */
32 };
33 
34 static const struct pad_group lewisburg_community3_groups[] = {
35  INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */
36 };
37 
38 static const struct pad_group lewisburg_community4_groups[] = {
39  INTEL_GPP(GPP_J0, GPP_J0, GPP_J23), /* GPP F */
40  INTEL_GPP(GPP_J0, GPP_K0, GPP_K10), /* GPP K */
41 };
42 
43 static const struct pad_group lewisburg_community5_groups[] = {
44  INTEL_GPP(GPP_G0, GPP_G0, GPP_G23), /* GPP G */
45  INTEL_GPP(GPP_G0, GPP_H0, GPP_H23), /* GPP H */
46  INTEL_GPP(GPP_G0, GPP_L0, GPP_L19), /* GPP L */
47 };
48 
49 static const struct pad_group lewisburg_community2_groups[] = {
50  INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */
51 };
52 
53 static const struct pad_community lewisburg_gpio_communities[] = {
54  [COMM_0] = { /* GPIO Community 0: GPP A, B, F */
55  .port = PID_GPIOCOM0,
56  .first_pad = GPP_A0,
57  .last_pad = GPP_F23,
58  .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
59  .pad_cfg_base = PAD_CFG_BASE,
60  .host_own_reg_0 = HOSTSW_OWN_REG_0,
61  .gpi_int_sts_reg_0 = GPI_INT_STS_0,
62  .gpi_int_en_reg_0 = GPI_INT_EN_0,
63  .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
64  .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
65  .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
66  .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
67  .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
68  .name = "GPIO_COM0",
69  .acpi_path = "\\_SB.PCI0.GPIO",
70  .reset_map = rst_map,
71  .num_reset_vals = ARRAY_SIZE(rst_map),
74  },
75  [COMM_1] = { /* GPIO Community 1: GPP C, D, E */
76  .port = PID_GPIOCOM1,
77  .first_pad = GPP_C0,
78  .last_pad = GPP_E12,
79  .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
80  .pad_cfg_base = PAD_CFG_BASE,
81  .host_own_reg_0 = HOSTSW_OWN_REG_0,
82  .gpi_int_sts_reg_0 = GPI_INT_STS_0,
83  .gpi_int_en_reg_0 = GPI_INT_EN_0,
84  .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
85  .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
86  .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
87  .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
88  .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
89  .name = "GPIO_COM1",
90  .acpi_path = "\\_SB.PCI0.GPIO",
91  .reset_map = rst_map,
92  .num_reset_vals = ARRAY_SIZE(rst_map),
95  },
96  [COMM_3] = { /* GPIO Community 3: GPP I */
97  .port = PID_GPIOCOM3,
98  .first_pad = GPP_I0,
99  .last_pad = GPP_I10,
100  .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
101  .pad_cfg_base = PAD_CFG_BASE,
102  .host_own_reg_0 = HOSTSW_OWN_REG_0,
103  .gpi_int_sts_reg_0 = GPI_INT_STS_0,
104  .gpi_int_en_reg_0 = GPI_INT_EN_0,
105  .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
106  .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
107  .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
108  .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
109  .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
110  .name = "GPIO_COM3",
111  .acpi_path = "\\_SB.PCI0.GPIO",
112  .reset_map = rst_map,
113  .num_reset_vals = ARRAY_SIZE(rst_map),
114  .groups = lewisburg_community3_groups,
116  },
117  [COMM_4] = { /* GPIO Community 4: GPP F, G */
118  .port = PID_GPIOCOM4,
119  .first_pad = GPP_J0,
120  .last_pad = GPP_K10,
121  .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
122  .pad_cfg_base = PAD_CFG_BASE,
123  .host_own_reg_0 = HOSTSW_OWN_REG_0,
124  .gpi_int_sts_reg_0 = GPI_INT_STS_0,
125  .gpi_int_en_reg_0 = GPI_INT_EN_0,
126  .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
127  .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
128  .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
129  .name = "GPIO_COM4",
130  .acpi_path = "\\_SB.PCI0.GPIO",
131  .reset_map = rst_map,
132  .num_reset_vals = ARRAY_SIZE(rst_map),
133  .groups = lewisburg_community4_groups,
135  },
136  [COMM_5] = { /* GPIO Community 5: GPP G, H, L */
137  .port = PID_GPIOCOM5,
138  .first_pad = GPP_G0,
139  .last_pad = GPP_L19,
140  .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
141  .pad_cfg_base = PAD_CFG_BASE,
142  .host_own_reg_0 = HOSTSW_OWN_REG_0,
143  .gpi_int_sts_reg_0 = GPI_INT_STS_0,
144  .gpi_int_en_reg_0 = GPI_INT_EN_0,
145  .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
146  .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
147  .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
148  .name = "GPIO_COM5",
149  .acpi_path = "\\_SB.PCI0.GPIO",
150  .reset_map = rst_map,
151  .num_reset_vals = ARRAY_SIZE(rst_map),
152  .groups = lewisburg_community5_groups,
154  },
155  [COMM_2] = { /* GPIO Community 2: GPD */
156  .port = PID_GPIOCOM2,
157  .first_pad = GPD0,
158  .last_pad = GPD11,
159  .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
160  .pad_cfg_base = PAD_CFG_BASE,
161  .host_own_reg_0 = HOSTSW_OWN_REG_0,
162  .gpi_int_sts_reg_0 = GPI_INT_STS_0,
163  .gpi_int_en_reg_0 = GPI_INT_EN_0,
164  .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
165  .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
166  .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
167  .name = "GPIO_COM2",
168  .acpi_path = "\\_SB.PCI0.GPIO",
169  .reset_map = rst_map,
170  .num_reset_vals = ARRAY_SIZE(rst_map),
171  .groups = lewisburg_community2_groups,
173  }
174 };
175 
176 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
177 {
178  *num_communities = ARRAY_SIZE(lewisburg_gpio_communities);
180 }
181 
182 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
183 {
184  static const struct pmc_to_gpio_route routes[] = {
185  { GPP_A, GPP_A },
186  { GPP_B, GPP_B },
187  { GPP_F, GPP_F },
188  { GPP_C, GPP_C },
189  { GPP_D, GPP_D },
190  { GPP_E, GPP_E },
191  { GPP_I, GPP_I },
192  { GPP_J, GPP_J },
193  { GPP_K, GPP_K },
194  { GPD, GPD },
195  };
196 
197  *num = ARRAY_SIZE(routes);
198  return routes;
199 }
#define GPD11
#define GPIO_MAX_NUM_PER_GROUP
Definition: gpio_soc_defs.h:31
#define COMM_0
Definition: gpio_soc_defs.h:33
#define GPP_D
Definition: gpio_soc_defs.h:26
#define GPP_A
Definition: gpio_soc_defs.h:16
#define GPP_E0
#define GPP_F23
#define GPP_F0
#define GPP_B
Definition: gpio_soc_defs.h:14
#define GPD0
#define GPP_C23
#define COMM_1
Definition: gpio_soc_defs.h:34
#define GPP_A23
#define GPP_A0
#define COMM_3
Definition: gpio_soc_defs.h:36
#define GPP_H0
#define GPP_C
Definition: gpio_soc_defs.h:28
#define GPP_D0
#define GPP_B0
Definition: gpio_soc_defs.h:53
#define GPP_F
Definition: gpio_soc_defs.h:27
#define GPP_B23
Definition: gpio_soc_defs.h:76
#define GPP_E
Definition: gpio_soc_defs.h:29
#define GPD
Definition: gpio_soc_defs.h:18
#define COMM_4
Definition: gpio_soc_defs.h:37
#define COMM_5
Definition: gpio_soc_defs.h:38
#define GPP_E12
#define GPP_C0
#define COMM_2
Definition: gpio_soc_defs.h:35
#define GPP_H23
#define PID_GPIOCOM4
Definition: pcr_ids.h:19
#define PID_GPIOCOM5
Definition: pcr_ids.h:20
#define PID_GPIOCOM2
Definition: pcr_ids.h:17
#define PID_GPIOCOM3
Definition: pcr_ids.h:18
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define GPP_D23
#define GPP_G0
Definition: gpio_soc_defs.h:88
@ PID_GPIOCOM0
Definition: pcr.h:17
@ PID_GPIOCOM1
Definition: pcr.h:18
#define GPP_G23
#define GPP_J
#define GPP_I10
#define GPP_J0
#define GPP_I0
#define GPP_K10
#define GPP_K0
#define GPP_K
#define GPP_I
#define GPP_L0
#define GPP_L19
#define GPP_J23
const struct pmc_to_gpio_route * soc_pmc_gpio_routes(size_t *num)
Definition: gpio.c:247
const struct pad_community * soc_gpio_get_community(size_t *num_communities)
Definition: gpio.c:241
#define NUM_GPIO_COM5_GPI_REGS
Definition: gpio_defs.h:21
#define NUM_GPIO_COM1_GPI_REGS
Definition: gpio_defs.h:17
#define NUM_GPIO_COM3_GPI_REGS
Definition: gpio_defs.h:19
#define GPI_INT_EN_0
Definition: gpio_defs.h:346
#define GPI_INT_STS_0
Definition: gpio_defs.h:345
#define NUM_GPIO_COM2_GPI_REGS
Definition: gpio_defs.h:18
#define NUM_GPIO_COM4_GPI_REGS
Definition: gpio_defs.h:20
#define HOSTSW_OWN_REG_0
Definition: gpio_defs.h:344
#define NUM_GPIO_COM0_GPI_REGS
Definition: gpio_defs.h:16
#define GPI_SMI_STS_0
Definition: gpio_defs.h:347
#define PAD_CFG_BASE
Definition: gpio_defs.h:349
#define GPI_SMI_EN_0
Definition: gpio_defs.h:348
#define GPI_NMI_EN_0
Definition: gpio_defs.h:240
#define GPI_NMI_STS_0
Definition: gpio_defs.h:239
#define INTEL_GPP(first_of_community, start_of_group, end_of_group)
Definition: gpio.h:49
#define PAD_CFG0_LOGICAL_RESET_RSMRST
Definition: gpio_defs.h:47
#define PAD_CFG0_LOGICAL_RESET_PLTRST
Definition: gpio_defs.h:46
#define PAD_CFG0_LOGICAL_RESET_DEEP
Definition: gpio_defs.h:45
static const struct pad_group lewisburg_community2_groups[]
Definition: gpio.c:49
static const struct pad_group lewisburg_community0_groups[]
Definition: gpio.c:22
static const struct pad_group lewisburg_community3_groups[]
Definition: gpio.c:34
static const struct pad_group lewisburg_community5_groups[]
Definition: gpio.c:43
static const struct pad_group lewisburg_community1_groups[]
Definition: gpio.c:28
static const struct pad_community lewisburg_gpio_communities[]
Definition: gpio.c:53
static const struct reset_mapping rst_map[]
Definition: gpio.c:16
static const struct pad_group lewisburg_community4_groups[]
Definition: gpio.c:38
uint8_t port
Definition: gpio.h:135
Definition: gpio.h:94
uint32_t logical
Definition: gpio.h:89