coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
devapc.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /* This file is created based on MT8169_DEVICE_APC_REG_DEVAPC_external.docx */
4 
5 #include <console/console.h>
6 #include <soc/devapc.h>
7 #include <soc/devapc_common.h>
8 
9 static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = {
10  /* 0 */
11  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOPCKGEN",
14  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_INFRASYS_CONFIG_REGS",
17  DAPC_INFRA_AO_SYS0_ATTR("IO_CFG_REG",
19  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_ PERICFG",
22  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_EFUSAO_DEBUG",
24  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_GPIO",
27  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SLEEP_CONTROLLER",
30  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOPRGU",
32  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_APXGPT",
34  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_RESERVE",
36 
37  /* 10 */
38  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SEJ",
40  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_AP_CIRQ_EINT",
42  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_APMIXEDSYS",
45  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PMIC_WRAP",
48  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_INFRA_PERI",
50  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_MM",
52  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_KEYPAD",
54  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOP_MISC",
56  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_ DVFS_CTRL_PROC",
59  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_IFNRA_TOP_MBIST_CTRL",
61 
62  /* 20 */
63  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DPMAIF_AO_TOP",
65  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PMIF",
67  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_AES_TOP_0",
69  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SYS_TIMER",
71  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_MDEM_TEMP_SHARE",
73  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_MD",
75  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SECURITY_AO",
77  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPMI_MST_WRAP",
79  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM",
81  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM",
83 
84  /* 30 */
85  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM",
87  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM",
90  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_AP_DMA",
92  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE",
94  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE",
96  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_SYS_CIRQ",
98  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE",
100  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE",
102  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DEVICAPC",
104  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DBG_TRACKER",
106 
107  /* 40 */
108  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF0_AP",
110  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF0_MD",
112  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF1_AP",
114  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF1_MD",
116  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE",
118  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_INFRA_PDN_REGISTER",
120  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_TRNG",
122  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DX_CC",
124  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF4_AP",
127  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CQ_DMA",
129 
130  /* 50 */
131  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF4_MD",
134  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_SRAMROM",
136  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE",
138  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE",
140  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE",
142  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE",
144  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_EMI",
146  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DEVICMPU_LOW",
148  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_EMI_MPU_REG",
150  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP",
152 
153  /* 60 */
154  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP",
156  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP",
158  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP",
160  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP0",
162  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP1",
165  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP2",
168  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP3",
171  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP4",
174  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP5",
177  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP6",
180 
181  /* 70 */
182  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_GCE",
184  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP0",
187  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP1",
190  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP2",
193  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP3",
196  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP4",
199  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP5",
202  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP6",
205  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF2_AP",
207  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF2_MD",
209 
210  /* 80 */
211  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF3_AP",
214  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF3_MD",
217  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_1",
219  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_2",
221  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_3",
223  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_2",
226  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_3",
228  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_4",
230  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_5",
232  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_6",
234 
235  /* 90 */
236  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_7",
238  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_8",
240  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SCP",
243  DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_MCUCFG(*)",
246  DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DBUGSYS",
248  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_RESERVE",
250  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUXADC",
252  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART0",
254  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART1",
256  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C7",
258 
259  /* 100 */
260  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C8",
262  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_PWM",
264  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C0",
266  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C1",
268  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C2",
270  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI0",
272  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_PTP",
275  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_BTIF",
277  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C6",
279  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_DISP_PWM",
281 
282  /* 110 */
283  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C3",
285  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI1",
287  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C4",
289  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI2",
291  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI3",
293  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI4",
295  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI5",
297  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C5",
299  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_IMP_IIC_WRAP",
301  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART2",
303 
304  /* 120 */
305  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C9",
307  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB",
309  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB_2.0_SUB",
311  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC0",
313  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC1",
315  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC2",
317  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC3",
319  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UFS",
321  DAPC_INFRA_AO_SYS0_ATTR("PERISUS_USB3.0_SIF",
323  DAPC_INFRA_AO_SYS0_ATTR("PERISUS_USB3.0_SIF2",
325 
326  /* 130 */
327  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB_2.0_SIF(**)",
329  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUDIO",
332  DAPC_INFRA_AO_SYS0_ATTR("EAST_RESERVE",
334  DAPC_INFRA_AO_SYS0_ATTR("EAST_ CSI_TOP_AO",
336  DAPC_INFRA_AO_SYS0_ATTR("EAST_ RESERVE",
338  DAPC_INFRA_AO_SYS0_ATTR("EAST_ RESERVE",
340  DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE",
342  DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE",
344  DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE",
346  DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE",
348 
349  /* 140 */
350  DAPC_INFRA_AO_SYS0_ATTR("WEST_MIPI_TX_CONFIG",
352  DAPC_INFRA_AO_SYS0_ATTR("WEST_MSDC1",
354  DAPC_INFRA_AO_SYS0_ATTR("WEST_USB20_PHY",
356  DAPC_INFRA_AO_SYS0_ATTR("WEST_EFUSE",
358  DAPC_INFRA_AO_SYS0_ATTR("NORTH_UFS_MPHY",
360  DAPC_INFRA_AO_SYS0_ATTR("NORTH_MSDC0",
362  DAPC_INFRA_AO_SYS0_ATTR("NORTH_RESERV0",
364  DAPC_INFRA_AO_SYS0_ATTR("NORTH_RESERV1",
366  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_CONN",
369  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MD1",
371 
372  /* 150 */
373  DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUDIODSP",
375 };
376 
377 /* module, AP permission, N/A, SSPM permission, N/A */
378 static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[] = {
379 
380  /* 0 */
383  DAPC_MM_AO_SYS0_ATTR("Reserved",
385  DAPC_MM_AO_SYS0_ATTR("DFD",
387  DAPC_MM_AO_SYS0_ATTR("Reserved",
389  DAPC_MM_AO_SYS0_ATTR("G3D Secure Reg",
391  DAPC_MM_AO_SYS0_ATTR("G3D TestBench",
393  DAPC_MM_AO_SYS0_ATTR("G3D_CONFIG",
395  DAPC_MM_AO_SYS0_ATTR("Reserved",
397  DAPC_MM_AO_SYS0_ATTR("MMSYS_CONFIG",
399  DAPC_MM_AO_SYS0_ATTR("DISP_MUTEX0",
401 
402  /* 10 */
403  DAPC_MM_AO_SYS0_ATTR("SMI_COMMON",
405  DAPC_MM_AO_SYS0_ATTR("SMI_LARB0",
407  DAPC_MM_AO_SYS0_ATTR("SMI_LARB1",
409  DAPC_MM_AO_SYS0_ATTR("DISP_OVL0",
411  DAPC_MM_AO_SYS0_ATTR("DISP_OVL0_2L",
413  DAPC_MM_AO_SYS0_ATTR("DISP_RDMA0",
415  DAPC_MM_AO_SYS0_ATTR("DISP_RSZ0",
417  DAPC_MM_AO_SYS0_ATTR("DISP_COLOR0",
419  DAPC_MM_AO_SYS0_ATTR("Reserved",
421  DAPC_MM_AO_SYS0_ATTR("DISP_CCORR0",
423 
424  /* 20 */
425  DAPC_MM_AO_SYS0_ATTR("DISP_AAL0",
427  DAPC_MM_AO_SYS0_ATTR("DISP_GAMMA0",
429  DAPC_MM_AO_SYS0_ATTR("DISP_POSTMASK0",
431  DAPC_MM_AO_SYS0_ATTR("DISP_DITHER0",
433  DAPC_MM_AO_SYS0_ATTR("Reserved",
435  DAPC_MM_AO_SYS0_ATTR("Reserved",
437  DAPC_MM_AO_SYS0_ATTR("DISP_DSC_WRAP0",
439  DAPC_MM_AO_SYS0_ATTR("DSI0",
441  DAPC_MM_AO_SYS0_ATTR("DISP_WDMA0",
443  DAPC_MM_AO_SYS0_ATTR("RESERVED",
445 
446  /* 30 */
447  DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_0",
449  DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_1",
451  DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_2",
453  DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_3",
455  DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_4",
457  DAPC_MM_AO_SYS0_ATTR("DISP_SMI_2X1_SUB_COMMON_U0",
459  DAPC_MM_AO_SYS0_ATTR("DISP_SMI_2X1_SUB_COMMON_U1",
461  DAPC_MM_AO_SYS0_ATTR("Reserved",
463  DAPC_MM_AO_SYS0_ATTR("IMG1_SMI_2X1_SUB_COMMON",
465  DAPC_MM_AO_SYS0_ATTR("Reserved",
467 
468  /* 40 */
469  DAPC_MM_AO_SYS0_ATTR("Reserved",
471  DAPC_MM_AO_SYS0_ATTR("reserved (mfb_a)",
473  DAPC_MM_AO_SYS0_ATTR("reserved (wpe_a)",
475  DAPC_MM_AO_SYS0_ATTR("reserved (mss_a)",
477  DAPC_MM_AO_SYS0_ATTR("reserved",
479  DAPC_MM_AO_SYS0_ATTR("reserved",
481  DAPC_MM_AO_SYS0_ATTR("reserved",
483  DAPC_MM_AO_SYS0_ATTR("reserved",
484 
486  DAPC_MM_AO_SYS0_ATTR("reserved",
488  DAPC_MM_AO_SYS0_ATTR("reserved",
490 
491  /* 50 */
492  DAPC_MM_AO_SYS0_ATTR("reserved",
494  DAPC_MM_AO_SYS0_ATTR("reserved",
496  DAPC_MM_AO_SYS0_ATTR("reserved",
498  DAPC_MM_AO_SYS0_ATTR("reserved",
500  DAPC_MM_AO_SYS0_ATTR("reserved",
502  DAPC_MM_AO_SYS0_ATTR("reserved",
504  DAPC_MM_AO_SYS0_ATTR("reserved",
506  DAPC_MM_AO_SYS0_ATTR("imgsys1_top",
508  DAPC_MM_AO_SYS0_ATTR("dip_a0",
510  DAPC_MM_AO_SYS0_ATTR("dip_a1",
512 
513  /* 60 */
514  DAPC_MM_AO_SYS0_ATTR("dip_a2",
516  DAPC_MM_AO_SYS0_ATTR("dip_a3",
518  DAPC_MM_AO_SYS0_ATTR("dip_a4",
520  DAPC_MM_AO_SYS0_ATTR("dip_a5",
522  DAPC_MM_AO_SYS0_ATTR("dip_a6",
524  DAPC_MM_AO_SYS0_ATTR("dip_a7",
526  DAPC_MM_AO_SYS0_ATTR("reserved (dip_a8)",
528  DAPC_MM_AO_SYS0_ATTR("reserved (dip_a9)",
530  DAPC_MM_AO_SYS0_ATTR("dip_a10",
532  DAPC_MM_AO_SYS0_ATTR("dip_a11",
534 
535  /* 70 */
536  DAPC_MM_AO_SYS0_ATTR("reserved",
538  DAPC_MM_AO_SYS0_ATTR("smi_larb9",
540  DAPC_MM_AO_SYS0_ATTR("2x1_sub_common",
542  DAPC_MM_AO_SYS0_ATTR("reserved",
544  DAPC_MM_AO_SYS0_ATTR("mfb_b",
546  DAPC_MM_AO_SYS0_ATTR("wpe_b",
548  DAPC_MM_AO_SYS0_ATTR("mss_b",
550  DAPC_MM_AO_SYS0_ATTR("reserved",
552  DAPC_MM_AO_SYS0_ATTR("reserved",
554  DAPC_MM_AO_SYS0_ATTR("reserved",
556 
557  /* 80 */
558  DAPC_MM_AO_SYS0_ATTR("reserved",
560  DAPC_MM_AO_SYS0_ATTR("reserved",
562  DAPC_MM_AO_SYS0_ATTR("reserved",
564  DAPC_MM_AO_SYS0_ATTR("reserved",
566  DAPC_MM_AO_SYS0_ATTR("reserved",
568  DAPC_MM_AO_SYS0_ATTR("reserved",
570  DAPC_MM_AO_SYS0_ATTR("reserved",
572  DAPC_MM_AO_SYS0_ATTR("reserved",
574  DAPC_MM_AO_SYS0_ATTR("reserved",
576  DAPC_MM_AO_SYS0_ATTR("imgsys2_top",
578 
579  /* 90 */
580  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b0)",
582  DAPC_MM_AO_SYS0_ATTR("reserved (dip_a8)",
584  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b1)",
586  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b2)",
588  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b3)",
590  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b4)",
592  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b5)",
594  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b6)",
596  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b7)",
598  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b8)",
600 
601  /* 100 */
602  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b9)",
604  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b10)",
606  DAPC_MM_AO_SYS0_ATTR("reserved (dip_b11)",
608  DAPC_MM_AO_SYS0_ATTR("reserved",
610  DAPC_MM_AO_SYS0_ATTR("smi_larb11",
612  DAPC_MM_AO_SYS0_ATTR("reserved (smi_larb12)",
614  DAPC_MM_AO_SYS0_ATTR("rserved",
616  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
618  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
620  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
622 
623  /* 110 */
624  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
626  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
628  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
630  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
632  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
634  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
636  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
638  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
640  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
642  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
644 
645  /* 120 */
646  DAPC_MM_AO_SYS0_ATTR("vdec_core0",
648  DAPC_MM_AO_SYS0_ATTR("vdec_core0_larb",
650  DAPC_MM_AO_SYS0_ATTR("vdec_core0_gcon",
652  DAPC_MM_AO_SYS0_ATTR("vdec_mini_mdp_top",
654  DAPC_MM_AO_SYS0_ATTR("reserved",
656  DAPC_MM_AO_SYS0_ATTR("venc_global_con",
658  DAPC_MM_AO_SYS0_ATTR("smi_larb7",
660  DAPC_MM_AO_SYS0_ATTR("venc",
662  DAPC_MM_AO_SYS0_ATTR("jpgenc",
664  DAPC_MM_AO_SYS0_ATTR("reserved",
666 
667  /* 130 */
668  DAPC_MM_AO_SYS0_ATTR("reserved",
670  DAPC_MM_AO_SYS0_ATTR("venc_mbist_ctrl",
672  DAPC_MM_AO_SYS0_ATTR("reserved",
674  DAPC_MM_AO_SYS0_ATTR("camsys top",
676  DAPC_MM_AO_SYS0_ATTR("smi_larb13",
678  DAPC_MM_AO_SYS0_ATTR("smi_larb14",
680  DAPC_MM_AO_SYS0_ATTR("RESERVED",
682  DAPC_MM_AO_SYS0_ATTR("seninf_a",
684  DAPC_MM_AO_SYS0_ATTR("seninf_b",
686  DAPC_MM_AO_SYS0_ATTR("seninf_c",
688 
689  /* 140 */
690  DAPC_MM_AO_SYS0_ATTR("seninf_d",
692  DAPC_MM_AO_SYS0_ATTR("seninf_e",
694  DAPC_MM_AO_SYS0_ATTR("seninf_f",
696  DAPC_MM_AO_SYS0_ATTR("seninf_g",
698  DAPC_MM_AO_SYS0_ATTR("seninf_h",
700  DAPC_MM_AO_SYS0_ATTR("cam_smi_3x1_sub_common_u0",
702  DAPC_MM_AO_SYS0_ATTR("cam_smi_4x1_sub_common_u0",
704  DAPC_MM_AO_SYS0_ATTR("RESERVED",
706  DAPC_MM_AO_SYS0_ATTR("smi_larb_16",
708  DAPC_MM_AO_SYS0_ATTR("smi_larb_17",
710 
711  /* 150 */
712  DAPC_MM_AO_SYS0_ATTR("RESERVED",
714  DAPC_MM_AO_SYS0_ATTR("RESERVED",
716  DAPC_MM_AO_SYS0_ATTR("RESERVED",
718  DAPC_MM_AO_SYS0_ATTR("RESERVED",
720  DAPC_MM_AO_SYS0_ATTR("RESERVED",
722  DAPC_MM_AO_SYS0_ATTR("RESERVED",
724  DAPC_MM_AO_SYS0_ATTR("RESERVED",
726  DAPC_MM_AO_SYS0_ATTR("RESERVED",
728  DAPC_MM_AO_SYS0_ATTR("RESERVED",
730  DAPC_MM_AO_SYS0_ATTR("RESERVED",
732 
733  /* 160 */
734  DAPC_MM_AO_SYS0_ATTR("RESERVED",
736  DAPC_MM_AO_SYS0_ATTR("RESERVED",
738  DAPC_MM_AO_SYS0_ATTR("RESERVED",
740  DAPC_MM_AO_SYS0_ATTR("RESERVED",
742  DAPC_MM_AO_SYS0_ATTR("RESERVED",
744  DAPC_MM_AO_SYS0_ATTR("RESERVED",
746  DAPC_MM_AO_SYS0_ATTR("RESERVED",
748  DAPC_MM_AO_SYS0_ATTR("RESERVED",
750  DAPC_MM_AO_SYS0_ATTR("RESERVED",
752  DAPC_MM_AO_SYS0_ATTR("RESERVED",
754 
755  /* 170 */
756  DAPC_MM_AO_SYS0_ATTR("RESERVED",
758  DAPC_MM_AO_SYS0_ATTR("RESERVED",
760  DAPC_MM_AO_SYS0_ATTR("RESERVED",
762  DAPC_MM_AO_SYS0_ATTR("RESERVED",
764  DAPC_MM_AO_SYS0_ATTR("RESERVED",
766  DAPC_MM_AO_SYS0_ATTR("RESERVED",
768  DAPC_MM_AO_SYS0_ATTR("RESERVED",
770  DAPC_MM_AO_SYS0_ATTR("RESERVED",
772  DAPC_MM_AO_SYS0_ATTR("RESERVED",
774  DAPC_MM_AO_SYS0_ATTR("RESERVED",
776 
777  /* 180 */
778  DAPC_MM_AO_SYS0_ATTR("RESERVED",
780  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_0",
782  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_1",
784  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_2",
786  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_3",
788  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_0",
790  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_1",
792  DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_0",
794  DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_1",
796  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_0_inner",
798 
799  /* 190 */
800  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_1_inner",
802  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_2_inner",
804  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_3_inner",
806  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_0_inner",
808  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_1_inner",
810  DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_0_inner",
812  DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_1_inner",
814  DAPC_MM_AO_SYS0_ATTR("RESERVED",
816  DAPC_MM_AO_SYS0_ATTR("RESERVED",
818  DAPC_MM_AO_SYS0_ATTR("RESERVED",
820 
821  /* 200 */
822  DAPC_MM_AO_SYS0_ATTR("RESERVED",
824  DAPC_MM_AO_SYS0_ATTR("RESERVED",
826  DAPC_MM_AO_SYS0_ATTR("RESERVED",
828  DAPC_MM_AO_SYS0_ATTR("RESERVED",
830  DAPC_MM_AO_SYS0_ATTR("RESERVED",
832  DAPC_MM_AO_SYS0_ATTR("RESERVED",
834  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_set",
836  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_clr",
838  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_set_inner",
840  DAPC_MM_AO_SYS0_ATTR("cam_raw_a_clr_inner",
842 
843  /* 210 */
844  DAPC_MM_AO_SYS0_ATTR("RESERVED",
846  DAPC_MM_AO_SYS0_ATTR("RESERVED",
848  DAPC_MM_AO_SYS0_ATTR("camsys_a_config",
850  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_0",
852  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_1",
854  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_2",
856  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_3",
858  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_0",
860  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_1",
862  DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_0",
864 
865  /* 220 */
866  DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_1",
868  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_0_inner",
870  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_1_inner",
872  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_2_inner",
874  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_3_inner",
876  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_0_inner",
878  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_1_inner",
880  DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_0_inner",
882  DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_1_inner",
884  DAPC_MM_AO_SYS0_ATTR("RESERVED",
886 
887  /* 230 */
888  DAPC_MM_AO_SYS0_ATTR("RESERVED",
890  DAPC_MM_AO_SYS0_ATTR("RESERVED",
892  DAPC_MM_AO_SYS0_ATTR("RESERVED",
894  DAPC_MM_AO_SYS0_ATTR("RESERVED",
896  DAPC_MM_AO_SYS0_ATTR("RESERVED",
898  DAPC_MM_AO_SYS0_ATTR("RESERVED",
900  DAPC_MM_AO_SYS0_ATTR("RESERVED",
902  DAPC_MM_AO_SYS0_ATTR("RESERVED",
904  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_set",
906  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_clr",
908 
909  /* 240 */
910  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_set_inner",
912  DAPC_MM_AO_SYS0_ATTR("cam_raw_b_clr_inner",
914  DAPC_MM_AO_SYS0_ATTR("RESERVED",
916  DAPC_MM_AO_SYS0_ATTR("RESERVED",
918  DAPC_MM_AO_SYS0_ATTR("camsys_b_config",
920  DAPC_MM_AO_SYS0_ATTR("RESERVED",
922  DAPC_MM_AO_SYS0_ATTR("RESERVED",
924  DAPC_MM_AO_SYS0_ATTR("RESERVED",
926  DAPC_MM_AO_SYS0_ATTR("RESERVED",
928  DAPC_MM_AO_SYS0_ATTR("RESERVED",
930 
931  /* 250 */
932  DAPC_MM_AO_SYS0_ATTR("RESERVED",
934  DAPC_MM_AO_SYS0_ATTR("RESERVED",
936  DAPC_MM_AO_SYS0_ATTR("RESERVED",
938  DAPC_MM_AO_SYS0_ATTR("RESERVED",
940  DAPC_MM_AO_SYS0_ATTR("RESERVED",
942  DAPC_MM_AO_SYS0_ATTR("RESERVED",
944  DAPC_MM_AO_SYS0_ATTR("RESERVED",
946  DAPC_MM_AO_SYS0_ATTR("RESERVED",
948  DAPC_MM_AO_SYS0_ATTR("RESERVED",
950  DAPC_MM_AO_SYS0_ATTR("RESERVED",
952 
953  /* 260 */
954  DAPC_MM_AO_SYS0_ATTR("RESERVED",
956  DAPC_MM_AO_SYS0_ATTR("RESERVED",
958  DAPC_MM_AO_SYS0_ATTR("RESERVED",
960  DAPC_MM_AO_SYS0_ATTR("RESERVED",
962  DAPC_MM_AO_SYS0_ATTR("RESERVED",
964  DAPC_MM_AO_SYS0_ATTR("RESERVED",
966  DAPC_MM_AO_SYS0_ATTR("RESERVED",
968  DAPC_MM_AO_SYS0_ATTR("RESERVED",
970  DAPC_MM_AO_SYS0_ATTR("RESERVED",
972  DAPC_MM_AO_SYS0_ATTR("RESERVED",
974 
975  /* 270 */
976  DAPC_MM_AO_SYS0_ATTR("RESERVED",
978  DAPC_MM_AO_SYS0_ATTR("RESERVED",
980  DAPC_MM_AO_SYS0_ATTR("RESERVED",
982  DAPC_MM_AO_SYS0_ATTR("RESERVED",
984  DAPC_MM_AO_SYS0_ATTR("RESERVED",
986  DAPC_MM_AO_SYS0_ATTR("RESERVED",
988  DAPC_MM_AO_SYS0_ATTR("RESERVED",
990  DAPC_MM_AO_SYS0_ATTR("RESERVED",
992  DAPC_MM_AO_SYS0_ATTR("RESERVED",
994  DAPC_MM_AO_SYS0_ATTR("camsv_2",
996 
997  /* 280 */
998  DAPC_MM_AO_SYS0_ATTR("camsv_3",
1000  DAPC_MM_AO_SYS0_ATTR("camsv_4",
1002  DAPC_MM_AO_SYS0_ATTR("camsv_5",
1004  DAPC_MM_AO_SYS0_ATTR("camsv_6",
1006  DAPC_MM_AO_SYS0_ATTR("camsv_7",
1008  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1010  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1012  DAPC_MM_AO_SYS0_ATTR("camsv_2_inner",
1014  DAPC_MM_AO_SYS0_ATTR("camsv_3_inner",
1016  DAPC_MM_AO_SYS0_ATTR("camsv_4_inner",
1018 
1019  /* 290 */
1020  DAPC_MM_AO_SYS0_ATTR("camsv_5_inner",
1022  DAPC_MM_AO_SYS0_ATTR("camsv_6_inner",
1024  DAPC_MM_AO_SYS0_ATTR("camsv_7_inner",
1026  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1028  DAPC_MM_AO_SYS0_ATTR("asg",
1030  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1032  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1034  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1036  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1038  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1040 
1041  /* 300 */
1042  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1044  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1046  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1048  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1050  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1052  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1054  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1056  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1058  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1060  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1062 
1063  /* 310 */
1064  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1066  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1068  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1070  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1072  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1074  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1076  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1078  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1080  DAPC_MM_AO_SYS0_ATTR("RESERVED",
1082  DAPC_MM_AO_SYS0_ATTR("mdpsys_config",
1084 
1085  /* 320 */
1086  DAPC_MM_AO_SYS0_ATTR("mdp_mutex0",
1088  DAPC_MM_AO_SYS0_ATTR("smi_larb0",
1089  NO_PROTECTION4),
1090  DAPC_MM_AO_SYS0_ATTR("mdp_rdma0",
1092  DAPC_MM_AO_SYS0_ATTR("Reserved",
1094  DAPC_MM_AO_SYS0_ATTR("mdp_aal0",
1096  DAPC_MM_AO_SYS0_ATTR("Reserved",
1098  DAPC_MM_AO_SYS0_ATTR("mdp_hdr0",
1100  DAPC_MM_AO_SYS0_ATTR("mdp_rsz0",
1102  DAPC_MM_AO_SYS0_ATTR("mdp_rsz1",
1104  DAPC_MM_AO_SYS0_ATTR("mdp_wrot0",
1106 
1107  /* 330 */
1108  DAPC_MM_AO_SYS0_ATTR("mdp_wrot1",
1110  DAPC_MM_AO_SYS0_ATTR("mdp_tdshp0",
1112  DAPC_MM_AO_SYS0_ATTR("Reserved",
1114  DAPC_MM_AO_SYS0_ATTR("Reserved",
1116  DAPC_MM_AO_SYS0_ATTR("Reserved",
1118  DAPC_MM_AO_SYS0_ATTR("ipesys_top",
1120  DAPC_MM_AO_SYS0_ATTR("fdvt",
1122  DAPC_MM_AO_SYS0_ATTR("Reserved (fe)",
1124  DAPC_MM_AO_SYS0_ATTR("rsc",
1126  DAPC_MM_AO_SYS0_ATTR("reserved",
1128 
1129  /* 340 */
1130  DAPC_MM_AO_SYS0_ATTR("reserved",
1132  DAPC_MM_AO_SYS0_ATTR("reserved",
1134  DAPC_MM_AO_SYS0_ATTR("reserved",
1136  DAPC_MM_AO_SYS0_ATTR("reserved",
1138  DAPC_MM_AO_SYS0_ATTR("reserved",
1140  DAPC_MM_AO_SYS0_ATTR("reserved",
1142  DAPC_MM_AO_SYS0_ATTR("reserved",
1144  DAPC_MM_AO_SYS0_ATTR("reserved",
1146  DAPC_MM_AO_SYS0_ATTR("reserved",
1148  DAPC_MM_AO_SYS0_ATTR("ipe_smi_2x1_sub_common",
1150 
1151  /* 350 */
1152  DAPC_MM_AO_SYS0_ATTR("smi_larb20",
1153  NO_PROTECTION4),
1154  DAPC_MM_AO_SYS0_ATTR("depth",
1156  DAPC_MM_AO_SYS0_ATTR("reserved",
1158  DAPC_MM_AO_SYS0_ATTR("reserved",
1160  DAPC_MM_AO_SYS0_ATTR("reserved",
1162  DAPC_MM_AO_SYS0_ATTR("reserved",
1164  DAPC_MM_AO_SYS0_ATTR("reserved",
1166  DAPC_MM_AO_SYS0_ATTR("reserved",
1168  DAPC_MM_AO_SYS0_ATTR("reserved",
1170  DAPC_MM_AO_SYS0_ATTR("reserved",
1172 
1173  /* 360 */
1174  DAPC_MM_AO_SYS0_ATTR("reserved",
1176  DAPC_MM_AO_SYS0_ATTR("reserved",
1178  DAPC_MM_AO_SYS0_ATTR("reserved",
1180  DAPC_MM_AO_SYS0_ATTR("reserved",
1182  DAPC_MM_AO_SYS0_ATTR("reserved",
1184  DAPC_MM_AO_SYS0_ATTR("reserved",
1186  DAPC_MM_AO_SYS0_ATTR("smi_larb19",
1187  NO_PROTECTION4),
1188  DAPC_MM_AO_SYS0_ATTR("reserved",
1190 };
1191 
1192 static const enum domain_id domain_map[] = {
1197 };
1198 
1199 static inline void *getreg_domain(uintptr_t base, unsigned int offset,
1200  enum domain_id domain_id, unsigned int index)
1201 {
1202  return (void *)(base + offset + domain_id * 0x100 + index * 0x4);
1203 }
1204 
1205 static inline void *getreg(uintptr_t base, unsigned int offset)
1206 {
1207  return getreg_domain(base, offset, 0, 0);
1208 }
1209 
1211  enum devapc_perm_type perm)
1212 {
1213  uint32_t apc_register_index;
1214  uint32_t apc_set_index;
1215 
1216  apc_register_index = module / MOD_NO_IN_1_DEVAPC;
1217  apc_set_index = module % MOD_NO_IN_1_DEVAPC;
1218 
1219  clrsetbits32(getreg_domain(base, 0, domain_id, apc_register_index),
1220  0x3 << (apc_set_index * 2),
1221  perm << (apc_set_index * 2));
1222 }
1223 
1225 {
1226  int i, j;
1227 
1228  for (i = 0; i < ARRAY_SIZE(infra_ao_sys0_devices); i++)
1229  for (j = 0; j < ARRAY_SIZE(infra_ao_sys0_devices[i].d_permission); j++)
1232 
1233  /*
1234  * Extra apc setting.
1235  * Block debugsys to avoid privilege escalation.
1236  */
1237  if (!CONFIG(CONSOLE_SERIAL))
1240 }
1241 
1243 {
1244  int i, j;
1245 
1246  for (i = 0; i < ARRAY_SIZE(mm_ao_sys0_devices); i++)
1247  for (j = 0; j < ARRAY_SIZE(mm_ao_sys0_devices[i].d_permission); j++)
1250 }
1251 
1253 {
1254  int reg_max;
1255  unsigned int d, i;
1256 
1258  for (d = 0; d < DOM_NUM_INFRA_AO_SYS0; d++)
1259  for (i = 0; i < reg_max; i++)
1260  printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO_SYS0)D%d_APC_%d: %#x\n", d, i,
1262 
1263  printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO)MAS_SEC_0: %#x\n",
1265 }
1266 
1268 {
1269  int reg_max;
1270  unsigned int d, i;
1271 
1273  for (d = 0; d < DOM_NUM_MM_AO_SYS0; d++)
1274  for (i = 0; i < reg_max; i++)
1275  printk(BIOS_DEBUG, "[DEVAPC] (MM_AO_SYS0)D%d_APC_%d: %#x\n", d, i,
1277 
1278  printk(BIOS_DEBUG, "[DEVAPC] (MM_AO)MAS_SEC_0: %#x\n",
1280 }
1281 
1283 {
1284  /* Side band */
1285  SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, SECURE_TRANS);
1286 
1287  /* Default APC Setting */
1289 }
1290 
1291 static void mm_init(uintptr_t base)
1292 {
1293  /* Default APC Setting */
1295 }
1296 
1301 } devapc_init[] = {
1304 };
1305 
1306 void dapc_init(void)
1307 {
1308  unsigned int i;
1309  uintptr_t devapc_ao_base;
1310 
1311  for (i = 0; i < ARRAY_SIZE(devapc_init); i++) {
1312  devapc_ao_base = devapc_init[i].base;
1313 
1314  /* Init dapc */
1315  write32(getreg(devapc_ao_base, AO_APC_CON), 0x0);
1316 
1317  /* Initialization */
1318  if (devapc_init[i].init)
1319  devapc_init[i].init(devapc_ao_base);
1320 
1321  /* Dump Setting */
1322  if (devapc_init[i].dump)
1323  devapc_init[i].dump(devapc_ao_base);
1324  }
1325 }
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
static uint32_t read32(const void *addr)
Definition: mmio.h:22
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define DIV_ROUND_UP(x, y)
Definition: helpers.h:60
#define printk(level,...)
Definition: stdlib.h:16
#define FORBIDDEN3
Definition: devapc_common.h:34
#define NO_PROTECTION4
Definition: devapc_common.h:48
#define FORBIDDEN5
Definition: devapc_common.h:36
#define FORBIDDEN4
Definition: devapc_common.h:35
#define FORBIDDEN6
Definition: devapc_common.h:37
#define FORBIDDEN7
Definition: devapc_common.h:38
@ CONFIG
Definition: dsi_common.h:201
static size_t offset
Definition: flashconsole.c:16
static void init(struct device *dev)
This function is the driver entry point for the init phase of the PCI bus allocator.
Definition: i210.c:181
#define SET32_BITFIELDS(addr,...)
Definition: mmio.h:201
#define clrsetbits32(addr, clear, set)
Definition: mmio.h:16
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
static void set_infra_ao_apc(uintptr_t base)
Definition: devapc.c:1224
static void * getreg(uintptr_t base, unsigned int offset)
Definition: devapc.c:1205
static void infra_init(uintptr_t base)
Definition: devapc.c:1282
static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[]
Definition: devapc.c:9
static void set_module_apc(uintptr_t base, uint32_t module, enum domain_id domain_id, enum devapc_perm_type perm)
Definition: devapc.c:1210
static void * getreg_domain(uintptr_t base, unsigned int offset, enum domain_id domain_id, unsigned int index)
Definition: devapc.c:1199
static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[]
Definition: devapc.c:378
static void dump_infra_ao_apc(uintptr_t base)
Definition: devapc.c:1252
static void dump_mm_ao_apc(uintptr_t base)
Definition: devapc.c:1267
void dapc_init(void)
Definition: devapc.c:1306
static void set_mm_ao_apc(uintptr_t base)
Definition: devapc.c:1242
static enum domain_id domain_map[]
Definition: devapc.c:1192
static void mm_init(uintptr_t base)
Definition: devapc.c:1291
#define DAPC_MM_AO_SYS0_ATTR(...)
Definition: devapc.h:81
#define DAPC_INFRA_AO_SYS0_ATTR(...)
Definition: devapc.h:80
@ DEVAPC_DEBUGSYS_INDEX
Definition: devapc.h:76
@ SECURE_TRANS
Definition: devapc.h:28
devapc_perm_type
Definition: devapc.h:31
@ SEC_RW_NS_R
Definition: devapc.h:34
@ SEC_RW_ONLY
Definition: devapc.h:33
@ FORBIDDEN
Definition: devapc.h:35
@ NO_PROTECTION
Definition: devapc.h:32
@ DOM_NUM_INFRA_AO_SYS0
Definition: devapc.h:71
@ DOM_NUM_MM_AO_SYS0
Definition: devapc.h:72
#define MOD_NO_IN_1_DEVAPC
Definition: devapc.h:86
@ SYS0_D0_APC_0
Definition: devapc.h:14
@ AO_APC_CON
Definition: devapc.h:19
@ MAS_SEC_0
Definition: devapc.h:18
domain_id
Definition: devapc.h:39
@ DOMAIN_0
Definition: devapc.h:40
@ DOMAIN_3
Definition: devapc.h:43
@ DOMAIN_1
Definition: devapc.h:41
@ DOMAIN_5
Definition: devapc.h:45
@ DOMAIN_7
Definition: devapc.h:47
@ DOMAIN_15
Definition: devapc.h:55
@ DOMAIN_2
Definition: devapc.h:42
@ DOMAIN_6
Definition: devapc.h:46
@ DOMAIN_14
Definition: devapc.h:54
@ DOMAIN_11
Definition: devapc.h:51
@ DOMAIN_12
Definition: devapc.h:52
@ DOMAIN_9
Definition: devapc.h:49
@ DOMAIN_8
Definition: devapc.h:48
@ DOMAIN_10
Definition: devapc.h:50
@ DOMAIN_13
Definition: devapc.h:53
@ DOMAIN_4
Definition: devapc.h:44
uintptr_t base
Definition: uart.c:17
@ DEVAPC_AO_MM_BASE
Definition: addressmap.h:33
@ DEVAPC_AO_INFRA_PERI_BASE
Definition: addressmap.h:32
int dump
Definition: display.c:23
unsigned int uint32_t
Definition: stdint.h:14
unsigned long uintptr_t
Definition: stdint.h:21
unsigned char d_permission[4]
Definition: devapc.h:67
uintptr_t base
Definition: devapc.c:1298
void(* init)(uintptr_t base)
Definition: devapc.c:1299
void(* dump)(uintptr_t base)
Definition: devapc.c:1300
uintptr_t base
Definition: devapc.c:113
void(* init)(uintptr_t base)
Definition: devapc.c:114
typedef void(X86APIP X86EMU_intrFuncs)(int num)