coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
#include <baseboard/gpio.h>
4
#include <baseboard/variants.h>
5
#include <
commonlib/helpers.h
>
6
7
/* Pad configuration in ramstage */
8
/* Leave eSPI pins untouched from default settings */
9
static
const
struct
pad_config
gpio_table
[] = {
10
/* A0 : RCIN# ==> NC(TP763) */
11
PAD_NC
(
GPP_A0
,
NONE
),
12
/* A1 : ESPI_IO0_R */
13
/* A2 : ESPI_IO1_R */
14
/* A3 : ESPI_IO2_R */
15
/* A4 : ESPI_IO3_R */
16
/* A5 : ESPI_CS_L_R */
17
/* A6 : SERIRQ ==> NC(TP764) */
18
PAD_NC
(
GPP_A6
,
NONE
),
19
/* A7 : PIRQA# ==> NC(TP703) */
20
PAD_NC
(
GPP_A7
,
NONE
),
21
/* A8 : CLKRUN# ==> NC(TP758)) */
22
PAD_NC
(
GPP_A8
,
NONE
),
23
/* A9 : ESPI_CLK_R */
24
PAD_CFG_NF
(
GPP_A9
, DN_20K, DEEP, NF3),
25
/* A10 : CLKOUT_LPC1 ==> NC */
26
PAD_NC
(
GPP_A10
,
NONE
),
27
/* A11 : PCH_FP_PWR_EN */
28
PAD_CFG_GPO
(
GPP_A11
, 1, DEEP),
29
/* A12 : ISH_GP6 */
30
PAD_NC
(
GPP_A12
,
NONE
),
31
/* A13 : SUSWARN# ==> SUSWARN_L */
32
PAD_CFG_NF
(
GPP_A13
,
NONE
, DEEP, NF1),
33
/* A14 : ESPI_RESET# */
34
/* A15 : SUSACK# ==> SUSACK_L */
35
PAD_CFG_NF
(
GPP_A15
,
NONE
, DEEP, NF1),
36
/* A16 : SD_1P8_SEL ==> NC */
37
PAD_NC
(
GPP_A16
,
NONE
),
38
/* A17 : SD_PWR_EN# ==> NC */
39
PAD_NC
(
GPP_A17
,
NONE
),
40
/* A18 : ISH_GP0 ==> ISH_GP0 */
41
PAD_NC
(
GPP_A18
,
NONE
),
42
/* A19 : SPKR_RST_L */
43
PAD_CFG_GPO
(
GPP_A19
, 1, PLTRST),
44
/* A20 : ISH_GP2 ==> ISH_UART0_RXD */
45
PAD_NC
(
GPP_A20
,
NONE
),
46
/* A21 : ISH_GP3 */
47
PAD_NC
(
GPP_A21
,
NONE
),
48
/* A22 : ISH_GP4 */
49
PAD_NC
(
GPP_A22
,
NONE
),
50
/* A23 : ISH_GP5 */
51
PAD_NC
(
GPP_A23
,
NONE
),
52
53
/* B0 : CORE_VID0 */
54
PAD_CFG_NF
(
GPP_B0
,
NONE
, DEEP, NF1),
55
/* B1 : CORE_VID1 */
56
PAD_CFG_NF
(
GPP_B1
,
NONE
, DEEP, NF1),
57
/* B2 : VRALERT# ==> NC */
58
PAD_NC
(
GPP_B2
,
NONE
),
59
/* B3 : CPU_GP2 ==> NC */
60
PAD_NC
(
GPP_B3
,
NONE
),
61
/* B4 : CPU_GP3 ==> FCAM_PWR_EN */
62
PAD_CFG_GPO
(
GPP_B4
, 0, DEEP),
63
/* B5 : SRCCLKREQ0# ==> NC */
64
PAD_NC
(
GPP_B5
,
NONE
),
65
/* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */
66
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_B6
,
NONE
, DEEP),
67
/* B7 : SRCCLKREQ2# ==> PCIE_NVME_CLKREQ_ODL */
68
PAD_CFG_NF
(
GPP_B7
,
NONE
, DEEP, NF1),
69
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
70
PAD_CFG_GPO
(
GPP_B8
, 0, RSMRST),
71
/* B9 : SRCCLKREQ4# ==> NC */
72
PAD_NC
(
GPP_B9
,
NONE
),
73
/* B10 : SRCCLKREQ5# ==> NC */
74
PAD_NC
(
GPP_B10
,
NONE
),
75
/* B11 : EXT_PWR_GATE# ==> NC */
76
PAD_NC
(
GPP_B11
,
NONE
),
77
/* B12 : SLP_S0# ==> SLP_S0_L_G */
78
PAD_CFG_NF
(
GPP_B12
,
NONE
, DEEP, NF1),
79
/* B13 : PLTRST# ==> PLT_RST_L */
80
PAD_CFG_NF
(
GPP_B13
,
NONE
, DEEP, NF1),
81
/* B14 : SPKR ==> NC */
82
PAD_NC
(
GPP_B14
,
NONE
),
83
/* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */
84
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
85
/* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */
86
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
87
/* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */
88
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
89
/* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */
90
PAD_CFG_NF
(
GPP_B18
, DN_20K, DEEP, NF1),
91
/* B19 : GSPI1_CS# ==> PCH_FPMCU_SPI_CS_L_R */
92
PAD_CFG_NF
(
GPP_B19
,
NONE
, DEEP, NF1),
93
/* B20 : GSPI1_CLK ==> PCH_FPMCU_SPI_CLK_R */
94
PAD_CFG_NF
(
GPP_B20
,
NONE
, DEEP, NF1),
95
/* B21 : GSPI1_MISO ==> PCH_FPMCU_SPI_MISO_R */
96
PAD_CFG_NF
(
GPP_B21
,
NONE
, DEEP, NF1),
97
/* B22 : GSPI1_MOSI ==> PCH_FPMCU_SPI_MOSI_R */
98
PAD_CFG_NF
(
GPP_B22
,
NONE
, DEEP, NF1),
99
/* B23 : SM1ALERT# ==> PCHHOT# */
100
PAD_CFG_NF
(
GPP_B23
, DN_20K, DEEP, NF2),
101
102
/* C0 : SMBCLK ==> NC */
103
PAD_NC
(
GPP_C0
,
NONE
),
104
/* C1 : SMBDATA ==> NC */
105
PAD_NC
(
GPP_C1
,
NONE
),
106
/* C2 : SMBALERT# ==> NC */
107
PAD_NC
(
GPP_C2
,
NONE
),
108
/* C3 : SML0CLK ==> NC */
109
PAD_NC
(
GPP_C3
,
NONE
),
110
/* C4 : SML0DATA ==> NC */
111
PAD_NC
(
GPP_C4
,
NONE
),
112
/* C5 : SML0ALERT# */
113
PAD_CFG_NF
(
GPP_C5
, DN_20K, DEEP, NF1),
114
/* C6 : SM1CLK ==> EC_IN_RW_OD */
115
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C6
,
NONE
, DEEP),
116
/* C7 : SM1DATA ==> NC */
117
PAD_NC
(
GPP_C7
,
NONE
),
118
/* C8 : UART0_RXD ==> PCH_FPMCU_BOOT0 */
119
PAD_CFG_GPO
(
GPP_C8
, 0, DEEP),
120
/* C9 : UART0_TXD ==> FPMCU_INT */
121
PAD_CFG_GPI_SCI
(
GPP_C9
,
NONE
, DEEP, EDGE_SINGLE, INVERT),
122
/* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */
123
PAD_CFG_GPO
(
GPP_C10
, 1, DEEP),
124
/* C11 : UART0_CTS# ==> FPMCU_INT */
125
PAD_CFG_GPI_APIC_HIGH
(
GPP_C11
, UP_20K, PLTRST),
126
/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
127
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C12
,
NONE
, DEEP),
128
/* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
129
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C13
,
NONE
, DEEP),
130
/* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
131
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C14
,
NONE
, DEEP),
132
/* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
133
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C15
,
NONE
, DEEP),
134
/* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_SDA */
135
PAD_CFG_NF
(
GPP_C16
,
NONE
, DEEP, NF1),
136
/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_SCL */
137
PAD_CFG_NF
(
GPP_C17
,
NONE
, DEEP, NF1),
138
/* C18 : I2C1_SDA ==> PCH_I2C1_DISPLAY_SAR_SDA */
139
PAD_CFG_NF
(
GPP_C18
,
NONE
, DEEP, NF1),
140
/* C19 : I2C1_SCL ==> PCH_I2C1_DISPLAY_SAR_SCL */
141
PAD_CFG_NF
(
GPP_C19
,
NONE
, DEEP, NF1),
142
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
143
PAD_CFG_NF
(
GPP_C20
,
NONE
, DEEP, NF1),
144
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
145
PAD_CFG_NF
(
GPP_C21
,
NONE
, DEEP, NF1),
146
/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
147
PAD_CFG_GPO
(
GPP_C22
, 0, DEEP),
148
/* C23 : UART2_CTS# ==> PCH_WP_OD */
149
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C23
, UP_20K, DEEP),
150
151
/* D0 : SPI1_CS# ==> NC */
152
PAD_NC
(
GPP_D0
,
NONE
),
153
/* D1 : SPI1_CLK ==> NC */
154
PAD_NC
(
GPP_D1
,
NONE
),
155
/* D2 : SPI1_MISO ==> NC */
156
PAD_NC
(
GPP_D2
,
NONE
),
157
/* D3 : SPI1_MOSI ==> NC */
158
PAD_NC
(
GPP_D3
,
NONE
),
159
/* D4 : FASHTRIG ==> NC */
160
PAD_NC
(
GPP_D4
,
NONE
),
161
/* D5 : ISH_I2C0_SDA ==> NC */
162
PAD_NC
(
GPP_D5
,
NONE
),
163
/* D6 : ISH_I2C0_SCL ==> NC */
164
PAD_NC
(
GPP_D6
,
NONE
),
165
/* D7 : ISH_I2C1_SDA ==> RCAM_PWR_EN */
166
PAD_CFG_GPO
(
GPP_D7
, 0, DEEP),
167
/* D8 : ISH_I2C1_SCL ==> NC */
168
PAD_NC
(
GPP_D8
,
NONE
),
169
/* D9 : ISH_SPI_CS# ==> PCH_SR1_INT_L */
170
PAD_CFG_GPI_APIC_HIGH
(
GPP_D9
,
NONE
, PLTRST),
171
/* D10 : ISH_SPI_CLK ==> PCH_SR0_INT_L */
172
PAD_CFG_GPI_APIC_HIGH
(
GPP_D10
,
NONE
, PLTRST),
173
/* D11 : ISH_SPI_MISO ==> NC */
174
PAD_NC
(
GPP_D11
,
NONE
),
175
/* D12 : ISH_SPI_MOSI ==> NC */
176
PAD_NC
(
GPP_D12
,
NONE
),
177
/* D13 : ISH_UART0_RXD ==> PCH_FCAM_CLK_EN */
178
PAD_CFG_GPO
(
GPP_D13
, 0, DEEP),
179
/* D14 : ISH_UART0_TXD ==> PCH_RCAM_CLK_EN */
180
PAD_CFG_GPO
(
GPP_D14
, 0, DEEP),
181
/* D15 : ISH_UART0_RTS# ==> FCAM_RST_L */
182
PAD_CFG_GPO
(
GPP_D15
, 0, DEEP),
183
/* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */
184
PAD_CFG_GPO
(
GPP_D16
, 0, DEEP),
185
/* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */
186
PAD_CFG_GPI_APIC_HIGH
(
GPP_D17
,
NONE
, PLTRST),
187
/* D18 : DMIC_DATA1 ==> TP131 */
188
PAD_NC
(
GPP_D18
,
NONE
),
189
/* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */
190
PAD_CFG_NF
(
GPP_D19
,
NONE
, DEEP, NF1),
191
/* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */
192
PAD_CFG_NF
(
GPP_D20
,
NONE
, DEEP, NF1),
193
/* D21 : SPI1_IO2 ==> NC */
194
PAD_NC
(
GPP_D21
,
NONE
),
195
/* D22 : SPI1_IO3 ==> NC */
196
PAD_NC
(
GPP_D22
,
NONE
),
197
/* D23 : I2S_MCLK ==> NC */
198
PAD_NC
(
GPP_D23
,
NONE
),
199
200
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
201
PAD_CFG_GPI_APIC_LOW
(
GPP_E0
,
NONE
, PLTRST),
202
/* E1 : SATAXPCIE1 ==> WLAN_WAKE_L */
203
PAD_CFG_GPI_SCI
(
GPP_E1
,
NONE
, DEEP, EDGE_SINGLE, INVERT),
204
/* E2 : SATAXPCIE2 ==> BT_DISABLE_L */
205
PAD_CFG_GPO
(
GPP_E2
, 1, DEEP),
206
/* E3 : CPU_GP0 ==> NC */
207
PAD_NC
(
GPP_E3
,
NONE
),
208
/* E3 : DEVSLP0 ==> NC */
209
PAD_NC
(
GPP_E4
,
NONE
),
210
/* E5 : SATA_DEVSLP1 ==> NC */
211
PAD_NC
(
GPP_E5
,
NONE
),
212
/* E6 : SATA_DEVSLP2 ==> NC */
213
PAD_NC
(
GPP_E6
,
NONE
),
214
/* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */
215
PAD_CFG_GPI_APIC_HIGH
(
GPP_E7
,
NONE
, PLTRST),
216
/* E8 : SATALED# ==> NC */
217
PAD_NC
(
GPP_E8
,
NONE
),
218
/* E9 : USB2_OCO# ==> USB_C0_OC_ODL */
219
PAD_CFG_NF
(
GPP_E9
,
NONE
, DEEP, NF1),
220
/* E10 : USB2_OC1# ==> USB_C1_OC_ODL */
221
PAD_CFG_NF
(
GPP_E10
,
NONE
, DEEP, NF1),
222
/* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */
223
PAD_CFG_TERM_GPO
(
GPP_E11
, 0, DN_20K, DEEP),
224
/* E12 : USB2_OC3# ==> NC */
225
PAD_NC
(
GPP_E12
,
NONE
),
226
/* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */
227
PAD_CFG_NF
(
GPP_E13
,
NONE
, DEEP, NF1),
228
/* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */
229
PAD_CFG_NF
(
GPP_E14
,
NONE
, DEEP, NF1),
230
/* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */
231
PAD_CFG_GPO
(
GPP_E15
, 1, DEEP),
232
/* E16 : DDPE_HPD3 ==> NC */
233
PAD_NC
(
GPP_E16
,
NONE
),
234
/* E17 : EDP_HPD ==> EDP_HPD_3V3 */
235
PAD_CFG_NF
(
GPP_E17
,
NONE
, DEEP, NF1),
236
/* E18 : DDPB_CTRLCLK ==> NC */
237
PAD_NC
(
GPP_E18
,
NONE
),
238
/* E19 : DDPB_CTRLDATA ==> DDPB_CTRLDATA */
239
PAD_CFG_NF
(
GPP_E19
, DN_20K, DEEP, NF1),
240
/* E20 : DDPC_CTRLCLK ==> NC */
241
PAD_NC
(
GPP_E20
,
NONE
),
242
/* E21 : DDPC_CTRLDATA ==> DDPC_CTRLDATA */
243
PAD_CFG_NF
(
GPP_E21
, DN_20K, DEEP, NF1),
244
/* E22 : DDPD_CTRLCLK ==> NC */
245
PAD_NC
(
GPP_E22
,
NONE
),
246
/* E23 : DDPD_CTRLDATA ==> NC */
247
PAD_NC
(
GPP_E23
,
NONE
),
248
249
/* F0 : I2S2_SCLK ==> BOOT_BEEP_CLK */
250
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F0
,
NONE
, DEEP),
251
/* F1 : I2S2_SFRM ==> BOOT_BEEP_BUFFER_OE */
252
PAD_CFG_GPO
(
GPP_F1
, 1, DEEP),
253
/* F2 : I2S2_TXD ==> BOOT_BEEP_SFRM */
254
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_F2
,
NONE
, DEEP),
255
/* F3 : I2S2_RXD ==> NC */
256
PAD_NC
(
GPP_F3
,
NONE
),
257
/* F4 : I2C2_SDA ==> NC */
258
PAD_NC
(
GPP_F4
,
NONE
),
259
/* F5 : I2C2_SCL ==> NC */
260
PAD_NC
(
GPP_F5
,
NONE
),
261
/* F6 : I2C3_SDA ==> PCH_I2C3_FCAM_1V8_SDA */
262
PAD_CFG_NF_1V8(
GPP_F6
,
NONE
, DEEP, NF1),
263
/* F7 : I2C3_SCL ==> PCH_I2C3_FCAM_1V8_SCL */
264
PAD_CFG_NF_1V8(
GPP_F7
,
NONE
, DEEP, NF1),
265
/* F8 : I2C4_SDA ==> PCH_I2C4_AUDIO_1V8_SDA */
266
PAD_CFG_NF_1V8(
GPP_F8
,
NONE
, DEEP, NF1),
267
/* F9 : I2C4_SCL ==> PCH_I2C4_AUDIO_1V8_SCL */
268
PAD_CFG_NF_1V8(
GPP_F9
,
NONE
, DEEP, NF1),
269
/* F10 : I2C5_SDA ==> SOC_RCAM_SAR0_I2C5_SDA */
270
PAD_CFG_NF
(
GPP_F10
,
NONE
, DEEP, NF1),
271
/* F11 : I2C5_SCL ==> SOC_RCAM_SAR0_I2C5_SCL */
272
PAD_CFG_NF
(
GPP_F11
,
NONE
, DEEP, NF1),
273
/* F12 : EMMC_CMD */
274
PAD_CFG_NF
(
GPP_F12
,
NONE
, DEEP, NF1),
275
/* F13 : EMMC_DATA0 */
276
PAD_CFG_NF
(
GPP_F13
,
NONE
, DEEP, NF1),
277
/* F14 : EMMC_DATA1 */
278
PAD_CFG_NF
(
GPP_F14
,
NONE
, DEEP, NF1),
279
/* F15 : EMMC_DATA2 */
280
PAD_CFG_NF
(
GPP_F15
,
NONE
, DEEP, NF1),
281
/* F16 : EMMC_DATA3 */
282
PAD_CFG_NF
(
GPP_F16
,
NONE
, DEEP, NF1),
283
/* F17 : EMMC_DATA4 */
284
PAD_CFG_NF
(
GPP_F17
,
NONE
, DEEP, NF1),
285
/* F18 : EMMC_DATA5 */
286
PAD_CFG_NF
(
GPP_F18
,
NONE
, DEEP, NF1),
287
/* F19 : EMMC_DATA6 */
288
PAD_CFG_NF
(
GPP_F19
,
NONE
, DEEP, NF1),
289
/* F20 : EMMC_DATA7 */
290
PAD_CFG_NF
(
GPP_F20
,
NONE
, DEEP, NF1),
291
/* F21 : EMMC_RCLK */
292
PAD_CFG_NF
(
GPP_F21
,
NONE
, DEEP, NF1),
293
/* F22 : EMMC_CLK */
294
PAD_CFG_NF
(
GPP_F22
,
NONE
, DEEP, NF1),
295
/* F23 : RSVD ==> NC */
296
PAD_NC
(
GPP_F23
,
NONE
),
297
298
/* G0 : SD_CMD */
299
PAD_NC
(
GPP_G0
,
NONE
),
300
/* G1 : SD_DATA0 */
301
PAD_NC
(
GPP_G1
,
NONE
),
302
/* G2 : SD_DATA1 */
303
PAD_NC
(
GPP_G2
,
NONE
),
304
/* G3 : SD_DATA2 */
305
PAD_NC
(
GPP_G3
,
NONE
),
306
/* G4 : SD_DATA3 */
307
PAD_NC
(
GPP_G4
,
NONE
),
308
/* G5 : SD_CD# */
309
PAD_NC
(
GPP_G5
,
NONE
),
310
/* G6 : SD_CLK */
311
PAD_NC
(
GPP_G6
,
NONE
),
312
/* G7 : SD_WP */
313
PAD_NC
(
GPP_G7
,
NONE
),
314
315
/* GPD0: BATLOW# ==> PCH_BATLOW_L */
316
PAD_CFG_NF
(
GPD0
,
NONE
, DEEP, NF1),
317
/* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */
318
PAD_CFG_NF
(
GPD1
,
NONE
, DEEP, NF1),
319
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */
320
PAD_CFG_NF
(
GPD2
,
NONE
, DEEP, NF1),
321
/* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */
322
PAD_CFG_NF
(
GPD3
, UP_20K, DEEP, NF1),
323
/* GPD4: SLP_S3# ==> SLP_S3_L */
324
PAD_CFG_NF
(
GPD4
,
NONE
, DEEP, NF1),
325
/* GPD5: SLP_S4# ==> SLP_S4_L */
326
PAD_CFG_NF
(
GPD5
,
NONE
, DEEP, NF1),
327
/* GPD6: SLP_A# ==> NC */
328
PAD_NC
(
GPD6
,
NONE
),
329
/* GPD7: RSVD ==> NC */
330
PAD_NC
(
GPD7
,
NONE
),
331
/* GPD8: SUSCLK ==> PCH_SUSCLK */
332
PAD_CFG_NF
(
GPD8
,
NONE
, DEEP, NF1),
333
/* GPD9: SLP_WLAN# ==> NC */
334
PAD_NC
(
GPD9
,
NONE
),
335
/* GPD10: SLP_S5# ==> NC */
336
PAD_NC
(
GPD10
,
NONE
),
337
/* GPD11: LANPHYC ==> NC */
338
PAD_NC
(
GPD11
,
NONE
),
339
};
340
341
/* Early pad configuration in bootblock */
342
static
const
struct
pad_config
early_gpio_table
[] = {
343
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
344
PAD_CFG_GPO
(
GPP_B8
, 0, RSMRST),
345
346
/* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */
347
PAD_CFG_NF
(
GPP_B15
,
NONE
, DEEP, NF1),
348
/* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */
349
PAD_CFG_NF
(
GPP_B16
,
NONE
, DEEP, NF1),
350
/* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */
351
PAD_CFG_NF
(
GPP_B17
,
NONE
, DEEP, NF1),
352
/* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */
353
PAD_CFG_NF
(
GPP_B18
, DN_20K, DEEP, NF1),
354
355
/* C6 : SM1CLK ==> EC_IN_RW_OD */
356
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C6
, UP_20K, DEEP),
357
358
/* Ensure UART pins are in native mode for H1. */
359
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
360
PAD_CFG_NF
(
GPP_C20
,
NONE
, DEEP, NF1),
361
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
362
PAD_CFG_NF
(
GPP_C21
,
NONE
, DEEP, NF1),
363
364
/* C23 : UART2_CTS# ==> PCH_WP */
365
PAD_CFG_GPI_GPIO_DRIVER
(
GPP_C23
, UP_20K, DEEP),
366
367
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
368
PAD_CFG_GPI_APIC_LOW
(
GPP_E0
,
NONE
, PLTRST),
369
};
370
371
const
struct
pad_config
*
variant_gpio_table
(
size_t
*num)
372
{
373
*num =
ARRAY_SIZE
(
gpio_table
);
374
return
gpio_table
;
375
}
376
377
const
struct
pad_config
*
variant_early_gpio_table
(
size_t
*num)
378
{
379
*num =
ARRAY_SIZE
(
early_gpio_table
);
380
return
early_gpio_table
;
381
}
GPD11
#define GPD11
Definition:
gpio_soc_defs.h:392
GPP_C15
#define GPP_C15
Definition:
gpio_soc_defs.h:552
GPD3
#define GPD3
Definition:
gpio_soc_defs.h:384
GPP_B6
#define GPP_B6
Definition:
gpio_soc_defs.h:59
GPP_D1
#define GPP_D1
Definition:
gpio_soc_defs.h:253
GPD9
#define GPD9
Definition:
gpio_soc_defs.h:390
GPP_C2
#define GPP_C2
Definition:
gpio_soc_defs.h:539
GPP_D10
#define GPP_D10
Definition:
gpio_soc_defs.h:262
GPP_D8
#define GPP_D8
Definition:
gpio_soc_defs.h:260
GPP_D17
#define GPP_D17
Definition:
gpio_soc_defs.h:269
GPP_E3
#define GPP_E3
Definition:
gpio_soc_defs.h:631
GPP_A18
#define GPP_A18
Definition:
gpio_soc_defs.h:137
GPP_F21
#define GPP_F21
Definition:
gpio_soc_defs.h:594
GPP_C12
#define GPP_C12
Definition:
gpio_soc_defs.h:549
GPP_F12
#define GPP_F12
Definition:
gpio_soc_defs.h:585
GPP_F16
#define GPP_F16
Definition:
gpio_soc_defs.h:589
GPP_E0
#define GPP_E0
Definition:
gpio_soc_defs.h:628
GPP_F6
#define GPP_F6
Definition:
gpio_soc_defs.h:579
GPP_D14
#define GPP_D14
Definition:
gpio_soc_defs.h:266
GPP_B1
#define GPP_B1
Definition:
gpio_soc_defs.h:54
GPP_F20
#define GPP_F20
Definition:
gpio_soc_defs.h:593
GPP_F23
#define GPP_F23
Definition:
gpio_soc_defs.h:596
GPP_C5
#define GPP_C5
Definition:
gpio_soc_defs.h:542
GPP_B12
#define GPP_B12
Definition:
gpio_soc_defs.h:65
GPP_D12
#define GPP_D12
Definition:
gpio_soc_defs.h:264
GPP_B16
#define GPP_B16
Definition:
gpio_soc_defs.h:69
GPP_B2
#define GPP_B2
Definition:
gpio_soc_defs.h:55
GPP_D7
#define GPP_D7
Definition:
gpio_soc_defs.h:259
GPP_B13
#define GPP_B13
Definition:
gpio_soc_defs.h:66
GPP_E6
#define GPP_E6
Definition:
gpio_soc_defs.h:634
GPP_F0
#define GPP_F0
Definition:
gpio_soc_defs.h:573
GPP_D6
#define GPP_D6
Definition:
gpio_soc_defs.h:258
GPP_A19
#define GPP_A19
Definition:
gpio_soc_defs.h:138
GPP_D2
#define GPP_D2
Definition:
gpio_soc_defs.h:254
GPP_C9
#define GPP_C9
Definition:
gpio_soc_defs.h:546
GPP_C22
#define GPP_C22
Definition:
gpio_soc_defs.h:559
GPD0
#define GPD0
Definition:
gpio_soc_defs.h:380
GPP_D9
#define GPP_D9
Definition:
gpio_soc_defs.h:261
GPP_F5
#define GPP_F5
Definition:
gpio_soc_defs.h:578
GPP_B15
#define GPP_B15
Definition:
gpio_soc_defs.h:68
GPP_E13
#define GPP_E13
Definition:
gpio_soc_defs.h:641
GPP_C23
#define GPP_C23
Definition:
gpio_soc_defs.h:560
GPP_C8
#define GPP_C8
Definition:
gpio_soc_defs.h:545
GPP_D11
#define GPP_D11
Definition:
gpio_soc_defs.h:263
GPP_A6
#define GPP_A6
Definition:
gpio_soc_defs.h:125
GPP_C11
#define GPP_C11
Definition:
gpio_soc_defs.h:548
GPP_D5
#define GPP_D5
Definition:
gpio_soc_defs.h:257
GPP_B22
#define GPP_B22
Definition:
gpio_soc_defs.h:75
GPP_A23
#define GPP_A23
Definition:
gpio_soc_defs.h:142
GPP_C18
#define GPP_C18
Definition:
gpio_soc_defs.h:555
GPP_F9
#define GPP_F9
Definition:
gpio_soc_defs.h:582
GPP_C13
#define GPP_C13
Definition:
gpio_soc_defs.h:550
GPP_E14
#define GPP_E14
Definition:
gpio_soc_defs.h:642
GPP_E23
#define GPP_E23
Definition:
gpio_soc_defs.h:651
GPP_E9
#define GPP_E9
Definition:
gpio_soc_defs.h:637
GPP_C17
#define GPP_C17
Definition:
gpio_soc_defs.h:554
GPP_E8
#define GPP_E8
Definition:
gpio_soc_defs.h:636
GPP_A7
#define GPP_A7
Definition:
gpio_soc_defs.h:126
GPP_E5
#define GPP_E5
Definition:
gpio_soc_defs.h:633
GPP_A0
#define GPP_A0
Definition:
gpio_soc_defs.h:119
GPD7
#define GPD7
Definition:
gpio_soc_defs.h:388
GPP_B8
#define GPP_B8
Definition:
gpio_soc_defs.h:61
GPP_C20
#define GPP_C20
Definition:
gpio_soc_defs.h:557
GPP_B20
#define GPP_B20
Definition:
gpio_soc_defs.h:73
GPP_A20
#define GPP_A20
Definition:
gpio_soc_defs.h:139
GPP_A16
#define GPP_A16
Definition:
gpio_soc_defs.h:135
GPP_F1
#define GPP_F1
Definition:
gpio_soc_defs.h:574
GPP_F17
#define GPP_F17
Definition:
gpio_soc_defs.h:590
GPP_A12
#define GPP_A12
Definition:
gpio_soc_defs.h:131
GPP_F15
#define GPP_F15
Definition:
gpio_soc_defs.h:588
GPP_D4
#define GPP_D4
Definition:
gpio_soc_defs.h:256
GPP_C10
#define GPP_C10
Definition:
gpio_soc_defs.h:547
GPP_C6
#define GPP_C6
Definition:
gpio_soc_defs.h:543
GPD2
#define GPD2
Definition:
gpio_soc_defs.h:383
GPP_F10
#define GPP_F10
Definition:
gpio_soc_defs.h:583
GPP_E7
#define GPP_E7
Definition:
gpio_soc_defs.h:635
GPP_C16
#define GPP_C16
Definition:
gpio_soc_defs.h:553
GPP_F7
#define GPP_F7
Definition:
gpio_soc_defs.h:580
GPD1
#define GPD1
Definition:
gpio_soc_defs.h:382
GPP_F13
#define GPP_F13
Definition:
gpio_soc_defs.h:586
GPP_C4
#define GPP_C4
Definition:
gpio_soc_defs.h:541
GPP_D18
#define GPP_D18
Definition:
gpio_soc_defs.h:270
GPP_B19
#define GPP_B19
Definition:
gpio_soc_defs.h:72
GPP_E17
#define GPP_E17
Definition:
gpio_soc_defs.h:645
GPP_E2
#define GPP_E2
Definition:
gpio_soc_defs.h:630
GPP_E19
#define GPP_E19
Definition:
gpio_soc_defs.h:647
GPP_C21
#define GPP_C21
Definition:
gpio_soc_defs.h:558
GPP_B9
#define GPP_B9
Definition:
gpio_soc_defs.h:62
GPD10
#define GPD10
Definition:
gpio_soc_defs.h:391
GPP_E18
#define GPP_E18
Definition:
gpio_soc_defs.h:646
GPP_F14
#define GPP_F14
Definition:
gpio_soc_defs.h:587
GPP_F4
#define GPP_F4
Definition:
gpio_soc_defs.h:577
GPP_A10
#define GPP_A10
Definition:
gpio_soc_defs.h:129
GPP_A8
#define GPP_A8
Definition:
gpio_soc_defs.h:127
GPP_D0
#define GPP_D0
Definition:
gpio_soc_defs.h:252
GPP_B14
#define GPP_B14
Definition:
gpio_soc_defs.h:67
GPP_B11
#define GPP_B11
Definition:
gpio_soc_defs.h:64
GPP_D13
#define GPP_D13
Definition:
gpio_soc_defs.h:265
GPP_B18
#define GPP_B18
Definition:
gpio_soc_defs.h:71
GPP_B5
#define GPP_B5
Definition:
gpio_soc_defs.h:58
GPP_B0
#define GPP_B0
Definition:
gpio_soc_defs.h:53
GPP_A11
#define GPP_A11
Definition:
gpio_soc_defs.h:130
GPP_C14
#define GPP_C14
Definition:
gpio_soc_defs.h:551
GPP_E20
#define GPP_E20
Definition:
gpio_soc_defs.h:648
GPP_A15
#define GPP_A15
Definition:
gpio_soc_defs.h:134
GPP_A9
#define GPP_A9
Definition:
gpio_soc_defs.h:128
GPP_E10
#define GPP_E10
Definition:
gpio_soc_defs.h:638
GPP_F8
#define GPP_F8
Definition:
gpio_soc_defs.h:581
GPP_C19
#define GPP_C19
Definition:
gpio_soc_defs.h:556
GPD8
#define GPD8
Definition:
gpio_soc_defs.h:389
GPP_A13
#define GPP_A13
Definition:
gpio_soc_defs.h:132
GPP_A21
#define GPP_A21
Definition:
gpio_soc_defs.h:140
GPP_B23
#define GPP_B23
Definition:
gpio_soc_defs.h:76
GPP_E15
#define GPP_E15
Definition:
gpio_soc_defs.h:643
GPP_B10
#define GPP_B10
Definition:
gpio_soc_defs.h:63
GPP_E16
#define GPP_E16
Definition:
gpio_soc_defs.h:644
GPP_D19
#define GPP_D19
Definition:
gpio_soc_defs.h:271
GPP_C1
#define GPP_C1
Definition:
gpio_soc_defs.h:538
GPP_F2
#define GPP_F2
Definition:
gpio_soc_defs.h:575
GPP_E11
#define GPP_E11
Definition:
gpio_soc_defs.h:639
GPD6
#define GPD6
Definition:
gpio_soc_defs.h:387
GPP_F18
#define GPP_F18
Definition:
gpio_soc_defs.h:591
GPP_B3
#define GPP_B3
Definition:
gpio_soc_defs.h:56
GPP_A22
#define GPP_A22
Definition:
gpio_soc_defs.h:141
GPP_F22
#define GPP_F22
Definition:
gpio_soc_defs.h:595
GPP_D15
#define GPP_D15
Definition:
gpio_soc_defs.h:267
GPP_F11
#define GPP_F11
Definition:
gpio_soc_defs.h:584
GPP_B21
#define GPP_B21
Definition:
gpio_soc_defs.h:74
GPD4
#define GPD4
Definition:
gpio_soc_defs.h:385
GPP_B4
#define GPP_B4
Definition:
gpio_soc_defs.h:57
GPP_D16
#define GPP_D16
Definition:
gpio_soc_defs.h:268
GPP_F3
#define GPP_F3
Definition:
gpio_soc_defs.h:576
GPP_E22
#define GPP_E22
Definition:
gpio_soc_defs.h:650
GPP_E21
#define GPP_E21
Definition:
gpio_soc_defs.h:649
GPP_C3
#define GPP_C3
Definition:
gpio_soc_defs.h:540
GPP_E12
#define GPP_E12
Definition:
gpio_soc_defs.h:640
GPP_A17
#define GPP_A17
Definition:
gpio_soc_defs.h:136
GPP_B17
#define GPP_B17
Definition:
gpio_soc_defs.h:70
GPP_E4
#define GPP_E4
Definition:
gpio_soc_defs.h:632
GPP_C0
#define GPP_C0
Definition:
gpio_soc_defs.h:537
GPD5
#define GPD5
Definition:
gpio_soc_defs.h:386
GPP_E1
#define GPP_E1
Definition:
gpio_soc_defs.h:629
GPP_F19
#define GPP_F19
Definition:
gpio_soc_defs.h:592
GPP_B7
#define GPP_B7
Definition:
gpio_soc_defs.h:60
GPP_C7
#define GPP_C7
Definition:
gpio_soc_defs.h:544
GPP_D3
#define GPP_D3
Definition:
gpio_soc_defs.h:255
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
GPP_D23
#define GPP_D23
Definition:
gpio_soc_defs.h:133
GPP_G1
#define GPP_G1
Definition:
gpio_soc_defs.h:89
GPP_G7
#define GPP_G7
Definition:
gpio_soc_defs.h:95
GPP_D22
#define GPP_D22
Definition:
gpio_soc_defs.h:132
GPP_G4
#define GPP_G4
Definition:
gpio_soc_defs.h:92
GPP_G2
#define GPP_G2
Definition:
gpio_soc_defs.h:90
GPP_D21
#define GPP_D21
Definition:
gpio_soc_defs.h:131
GPP_G6
#define GPP_G6
Definition:
gpio_soc_defs.h:94
GPP_G0
#define GPP_G0
Definition:
gpio_soc_defs.h:88
GPP_D20
#define GPP_D20
Definition:
gpio_soc_defs.h:130
GPP_G3
#define GPP_G3
Definition:
gpio_soc_defs.h:91
GPP_G5
#define GPP_G5
Definition:
gpio_soc_defs.h:93
helpers.h
variant_early_gpio_table
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition:
gpio.c:204
variant_gpio_table
const struct pad_config *__weak variant_gpio_table(size_t *num)
Definition:
gpio.c:406
gpio_table
static const struct pad_config gpio_table[]
Definition:
gpio.c:9
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio.c:342
NONE
@ NONE
Definition:
qup_se_handlers_common.h:196
PAD_NC
#define PAD_NC(pin)
Definition:
gpio_defs.h:263
PAD_CFG_TERM_GPO
#define PAD_CFG_TERM_GPO(pad, val, pull, rst)
Definition:
gpio_defs.h:262
PAD_CFG_NF
#define PAD_CFG_NF(pad, pull, rst, func)
Definition:
gpio_defs.h:197
PAD_CFG_GPI_APIC_HIGH
#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst)
Definition:
gpio_defs.h:405
PAD_CFG_GPO
#define PAD_CFG_GPO(pad, val, rst)
Definition:
gpio_defs.h:247
PAD_CFG_GPI_SCI
#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv)
Definition:
gpio_defs.h:432
PAD_CFG_GPI_APIC_LOW
#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst)
Definition:
gpio_defs.h:402
PAD_CFG_GPI_GPIO_DRIVER
#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst)
Definition:
gpio_defs.h:323
pad_config
Definition:
gpio.h:75
src
mainboard
google
poppy
variants
nocturne
gpio.c
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