coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Macros | Enumerations | Functions
setup.h File Reference

Go to the source code of this file.

Macros

#define TZPC0_BASE   0x10100000
 
#define TZPC1_BASE   0x10110000
 
#define TZPC2_BASE   0x10120000
 
#define TZPC3_BASE   0x10130000
 
#define TZPC4_BASE   0x10140000
 
#define TZPC5_BASE   0x10150000
 
#define TZPC6_BASE   0x10160000
 
#define TZPC7_BASE   0x10170000
 
#define TZPC8_BASE   0x10180000
 
#define TZPC9_BASE   0x10190000
 
#define APLL_FOUT   (1 << 0)
 
#define APLL_CON1_VAL   (0x00203800)
 
#define MPLL_CON1_VAL   (0x00203800)
 
#define CPLL_CON1_VAL   (0x00203800)
 
#define GPLL_CON1_VAL   (0x00203800)
 
#define EPLL_CON1_VAL   0x00000000
 
#define EPLL_CON2_VAL   0x00000080
 
#define VPLL_CON1_VAL   0x00000000
 
#define VPLL_CON2_VAL   0x00000080
 
#define BPLL_CON1_VAL   0x00203800
 
#define set_pll(mdiv, pdiv, sdiv)   (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
 
#define MUX_HPM_SEL   0
 
#define MUX_CPU_SEL   0
 
#define MUX_APLL_SEL   1
 
#define CLK_SRC_CPU_VAL
 
#define DMC_MEMCONTROL_CLK_STOP_DISABLE   (0 << 0)
 
#define DMC_MEMCONTROL_DPWRDN_DISABLE   (0 << 1)
 
#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE   (0 << 2)
 
#define DMC_MEMCONTROL_TP_DISABLE   (0 << 4)
 
#define DMC_MEMCONTROL_DSREF_DISABLE   (0 << 5)
 
#define DMC_MEMCONTROL_DSREF_ENABLE   (1 << 5)
 
#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x)   (x << 6)
 
#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3   (7 << 8)
 
#define DMC_MEMCONTROL_MEM_TYPE_DDR3   (6 << 8)
 
#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2   (5 << 8)
 
#define DMC_MEMCONTROL_MEM_WIDTH_32BIT   (2 << 12)
 
#define DMC_MEMCONTROL_NUM_CHIP_1   (0 << 16)
 
#define DMC_MEMCONTROL_NUM_CHIP_2   (1 << 16)
 
#define DMC_MEMCONTROL_BL_8   (3 << 20)
 
#define DMC_MEMCONTROL_BL_4   (2 << 20)
 
#define DMC_MEMCONTROL_PZQ_DISABLE   (0 << 24)
 
#define DMC_MEMCONTROL_MRR_BYTE_7_0   (0 << 25)
 
#define DMC_MEMCONTROL_MRR_BYTE_15_8   (1 << 25)
 
#define DMC_MEMCONTROL_MRR_BYTE_23_16   (2 << 25)
 
#define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)
 
#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED   (1 << 12)
 
#define DMC_MEMCONFIGx_CHIP_COL_10   (3 << 8)
 
#define DMC_MEMCONFIGx_CHIP_ROW_14   (2 << 4)
 
#define DMC_MEMCONFIGx_CHIP_ROW_15   (3 << 4)
 
#define DMC_MEMCONFIGx_CHIP_BANK_8   (3 << 0)
 
#define DMC_MEMBASECONFIGx_CHIP_BASE(x)   (x << 16)
 
#define DMC_MEMBASECONFIGx_CHIP_MASK(x)   (x << 0)
 
#define DMC_MEMBASECONFIG_VAL(x)
 
#define DMC_MEMBASECONFIG0_VAL   DMC_MEMBASECONFIG_VAL(0x40)
 
#define DMC_MEMBASECONFIG1_VAL   DMC_MEMBASECONFIG_VAL(0x80)
 
#define DMC_PRECHCONFIG_VAL   0xFF000000
 
#define DMC_PWRDNCONFIG_VAL   0xFFFF00FF
 
#define DMC_CONCONTROL_RESET_VAL   0x0FFF0000
 
#define DFI_INIT_START   (1 << 28)
 
#define EMPTY   (1 << 8)
 
#define AREF_EN   (1 << 5)
 
#define DFI_INIT_COMPLETE_CHO   (1 << 2)
 
#define DFI_INIT_COMPLETE_CH1   (1 << 3)
 
#define RDLVL_COMPLETE_CHO   (1 << 14)
 
#define RDLVL_COMPLETE_CH1   (1 << 15)
 
#define CLK_STOP_EN   (1 << 0)
 
#define DPWRDN_EN   (1 << 1)
 
#define DSREF_EN   (1 << 5)
 
#define DMC_CONCONTROL_IO_PD_CON_DISABLE   (0 << 3)
 
#define DMC_CONCONTROL_AREF_EN_DISABLE   (0 << 5)
 
#define DMC_CONCONTROL_EMPTY_DISABLE   (0 << 8)
 
#define DMC_CONCONTROL_EMPTY_ENABLE   (1 << 8)
 
#define DMC_CONCONTROL_RD_FETCH_DISABLE   (0x0 << 12)
 
#define DMC_CONCONTROL_TIMEOUT_LEVEL0   (0xFFF << 16)
 
#define DMC_CONCONTROL_DFI_INIT_START_DISABLE   (0 << 28)
 
#define CLK_DIV_CPU0_VAL
 
#define CLK_SRC_FSYS0_VAL   0x66666
 
#define CLK_DIV_FSYS0_VAL   0x0BB00000
 
#define HPM_RATIO   0x2
 
#define COPY_RATIO   0x0
 
#define CLK_DIV_CPU1_VAL
 
#define CLK_SRC_CORE0_VAL   0x00000000
 
#define CLK_SRC_CORE1_VAL   0x100
 
#define CLK_DIV_CORE0_VAL   0x00120000
 
#define CLK_DIV_CORE1_VAL   0x07070700
 
#define CLK_DIV_SYSRGT_VAL   0x00000111
 
#define CLK_DIV_ACP_VAL   0x12
 
#define CLK_DIV_SYSLFT_VAL   0x00000311
 
#define CLK_SRC_CDREX_VAL   0x1
 
#define MCLK_CDREX2_RATIO   0x0
 
#define ACLK_EFCON_RATIO   0x1
 
#define MCLK_DPHY_RATIO   0x1
 
#define MCLK_CDREX_RATIO   0x1
 
#define ACLK_C2C_200_RATIO   0x1
 
#define C2C_CLK_400_RATIO   0x1
 
#define PCLK_CDREX_RATIO   0x1
 
#define ACLK_CDREX_RATIO   0x1
 
#define CLK_DIV_CDREX_VAL
 
#define MUX_ACLK_300_GSCL_SEL   0x0
 
#define MUX_ACLK_300_GSCL_MID_SEL   0x0
 
#define MUX_ACLK_400_G3D_MID_SEL   0x0
 
#define MUX_ACLK_333_SEL   0x0
 
#define MUX_ACLK_300_DISP1_SEL   0x0
 
#define MUX_ACLK_300_DISP1_MID_SEL   0x0
 
#define MUX_ACLK_200_SEL   0x0
 
#define MUX_ACLK_166_SEL   0x0
 
#define CLK_SRC_TOP0_VAL
 
#define MUX_ACLK_400_G3D_SEL   0x1
 
#define MUX_ACLK_400_ISP_SEL   0x0
 
#define MUX_ACLK_400_IOP_SEL   0x0
 
#define MUX_ACLK_MIPI_HSI_TXBASE_SEL   0x0
 
#define MUX_ACLK_300_GSCL_MID1_SEL   0x0
 
#define MUX_ACLK_300_DISP1_MID1_SEL   0x0
 
#define CLK_SRC_TOP1_VAL
 
#define MUX_GPLL_SEL   0x1
 
#define MUX_BPLL_USER_SEL   0x0
 
#define MUX_MPLL_USER_SEL   0x0
 
#define MUX_VPLL_SEL   0x1
 
#define MUX_EPLL_SEL   0x1
 
#define MUX_CPLL_SEL   0x1
 
#define VPLLSRC_SEL   0x0
 
#define CLK_SRC_TOP2_VAL
 
#define MUX_ACLK_333_SUB_SEL   0x1
 
#define MUX_ACLK_400_SUB_SEL   0x1
 
#define MUX_ACLK_266_ISP_SUB_SEL   0x1
 
#define MUX_ACLK_266_GPS_SUB_SEL   0x0
 
#define MUX_ACLK_300_GSCL_SUB_SEL   0x1
 
#define MUX_ACLK_266_GSCL_SUB_SEL   0x1
 
#define MUX_ACLK_300_DISP1_SUB_SEL   0x1
 
#define MUX_ACLK_200_DISP1_SUB_SEL   0x1
 
#define CLK_SRC_TOP3_VAL
 
#define ACLK_300_DISP1_RATIO   0x2
 
#define ACLK_400_G3D_RATIO   0x0
 
#define ACLK_333_RATIO   0x0
 
#define ACLK_266_RATIO   0x2
 
#define ACLK_200_RATIO   0x3
 
#define ACLK_166_RATIO   0x1
 
#define ACLK_133_RATIO   0x1
 
#define ACLK_66_RATIO   0x5
 
#define CLK_DIV_TOP0_VAL
 
#define ACLK_MIPI_HSI_TX_BASE_RATIO   0x3
 
#define ACLK_66_PRE_RATIO   0x1
 
#define ACLK_400_ISP_RATIO   0x1
 
#define ACLK_400_IOP_RATIO   0x1
 
#define ACLK_300_GSCL_RATIO   0x2
 
#define CLK_DIV_TOP1_VAL
 
#define APLL_LOCK_VAL   (0x546)
 
#define MPLL_LOCK_VAL   (0x546)
 
#define CPLL_LOCK_VAL   (0x546)
 
#define GPLL_LOCK_VAL   (0x546)
 
#define EPLL_LOCK_VAL   (0x3A98)
 
#define VPLL_LOCK_VAL   (0x3A98)
 
#define BPLL_LOCK_VAL   (0x546)
 
#define MUX_MCLK_CDREX_SEL   (1 << 4)
 
#define MUX_MCLK_DPHY_SEL   (1 << 8)
 
#define MUX_APLL_SEL_MASK   (1 << 0)
 
#define MUX_MPLL_FOUT_SEL   (1 << 4)
 
#define MUX_BPLL_FOUT_SEL   (1 << 0)
 
#define MUX_MPLL_SEL_MASK   (1 << 8)
 
#define MPLL_SEL_MOUT_MPLLFOUT   (2 << 8)
 
#define MUX_CPLL_SEL_MASK   (1 << 8)
 
#define MUX_EPLL_SEL_MASK   (1 << 12)
 
#define MUX_VPLL_SEL_MASK   (1 << 16)
 
#define MUX_GPLL_SEL_MASK   (1 << 28)
 
#define MUX_BPLL_SEL_MASK   (1 << 0)
 
#define MUX_HPM_SEL_MASK   (1 << 20)
 
#define HPM_SEL_SCLK_MPLL   (1 << 21)
 
#define APLL_CON0_LOCKED   (1 << 29)
 
#define MPLL_CON0_LOCKED   (1 << 29)
 
#define BPLL_CON0_LOCKED   (1 << 29)
 
#define CPLL_CON0_LOCKED   (1 << 29)
 
#define EPLL_CON0_LOCKED   (1 << 29)
 
#define GPLL_CON0_LOCKED   (1 << 29)
 
#define VPLL_CON0_LOCKED   (1 << 29)
 
#define CLK_REG_DISABLE   0x0
 
#define TOP2_VAL   0x0110000
 
#define PWM_SEL   6
 
#define UART3_SEL   6
 
#define UART2_SEL   6
 
#define UART1_SEL   6
 
#define UART0_SEL   6
 
#define CLK_SRC_PERIC0_VAL
 
#define SPI0_SEL   6
 
#define SPI1_SEL   6
 
#define SPI2_SEL   6
 
#define CLK_SRC_PERIC1_VAL
 
#define SPI0_ISP_SEL   6
 
#define SPI1_ISP_SEL   6
 
#define SCLK_SRC_ISP_VAL
 
#define SPI0_ISP_RATIO   0xf
 
#define SPI1_ISP_RATIO   0xf
 
#define SCLK_DIV_ISP_VAL
 
#define UART5_RATIO   7
 
#define UART4_RATIO   7
 
#define UART3_RATIO   7
 
#define UART2_RATIO   7
 
#define UART1_RATIO   7
 
#define UART0_RATIO   7
 
#define CLK_DIV_PERIC0_VAL
 
#define SPI1_RATIO   0x7
 
#define SPI0_RATIO   0xf
 
#define SPI1_SUB_RATIO   0x0
 
#define SPI0_SUB_RATIO   0x0
 
#define CLK_DIV_PERIC1_VAL
 
#define SPI2_RATIO   0xf
 
#define SPI2_SUB_RATIO   0x0
 
#define CLK_DIV_PERIC2_VAL
 
#define MMC2_RATIO_MASK   0xf
 
#define MMC2_RATIO_VAL   0x3
 
#define MMC2_RATIO_OFFSET   0
 
#define MMC2_PRE_RATIO_MASK   0xff
 
#define MMC2_PRE_RATIO_VAL   0x9
 
#define MMC2_PRE_RATIO_OFFSET   8
 
#define MMC3_RATIO_MASK   0xf
 
#define MMC3_RATIO_VAL   0x1
 
#define MMC3_RATIO_OFFSET   16
 
#define MMC3_PRE_RATIO_MASK   0xff
 
#define MMC3_PRE_RATIO_VAL   0x0
 
#define MMC3_PRE_RATIO_OFFSET   24
 
#define CLK_SRC_LEX_VAL   0x0
 
#define CLK_DIV_LEX_VAL   0x10
 
#define CLK_DIV_R0X_VAL   0x10
 
#define CLK_DIV_R1X_VAL   0x10
 
#define CLK_DIV_ISP0_VAL   0x31
 
#define CLK_DIV_ISP1_VAL   0x0
 
#define CLK_DIV_ISP2_VAL   0x1
 
#define CLK_SRC_DISP1_0_VAL   0x6
 
#define CLK_DIV_DISP1_0_FIMD1   (2 << 0)
 
#define CLK_GATE_DP1_ALLOW   (1 << 4)
 
#define CLK_C2C_MASK   (1 << 1)
 
#define CLK_SMMUG2D_MASK   (1 << 7)
 
#define CLK_SMMUSSS_MASK   (1 << 6)
 
#define CLK_SMMUMDMA_MASK   (1 << 5)
 
#define CLK_ID_REMAPPER_MASK   (1 << 4)
 
#define CLK_G2D_MASK   (1 << 3)
 
#define CLK_SSS_MASK   (1 << 2)
 
#define CLK_MDMA_MASK   (1 << 1)
 
#define CLK_SECJTAG_MASK   (1 << 0)
 
#define CLK_EFCLK_MASK   (1 << 16)
 
#define CLK_UART_ISP_MASK   (1 << 31)
 
#define CLK_WDT_ISP_MASK   (1 << 30)
 
#define CLK_PWM_ISP_MASK   (1 << 28)
 
#define CLK_MTCADC_ISP_MASK   (1 << 27)
 
#define CLK_I2C1_ISP_MASK   (1 << 26)
 
#define CLK_I2C0_ISP_MASK   (1 << 25)
 
#define CLK_MPWM_ISP_MASK   (1 << 24)
 
#define CLK_MCUCTL_ISP_MASK   (1 << 23)
 
#define CLK_INT_COMB_ISP_MASK   (1 << 22)
 
#define CLK_SMMU_MCUISP_MASK   (1 << 13)
 
#define CLK_SMMU_SCALERP_MASK   (1 << 12)
 
#define CLK_SMMU_SCALERC_MASK   (1 << 11)
 
#define CLK_SMMU_FD_MASK   (1 << 10)
 
#define CLK_SMMU_DRC_MASK   (1 << 9)
 
#define CLK_SMMU_ISP_MASK   (1 << 8)
 
#define CLK_GICISP_MASK   (1 << 7)
 
#define CLK_ARM9S_MASK   (1 << 6)
 
#define CLK_MCUISP_MASK   (1 << 5)
 
#define CLK_SCALERP_MASK   (1 << 4)
 
#define CLK_SCALERC_MASK   (1 << 3)
 
#define CLK_FD_MASK   (1 << 2)
 
#define CLK_DRC_MASK   (1 << 1)
 
#define CLK_ISP_MASK   (1 << 0)
 
#define CLK_SPI1_ISP_MASK   (1 << 13)
 
#define CLK_SPI0_ISP_MASK   (1 << 12)
 
#define CLK_SMMU3DNR_MASK   (1 << 7)
 
#define CLK_SMMUDIS1_MASK   (1 << 6)
 
#define CLK_SMMUDIS0_MASK   (1 << 5)
 
#define CLK_SMMUODC_MASK   (1 << 4)
 
#define CLK_3DNR_MASK   (1 << 2)
 
#define CLK_DIS_MASK   (1 << 1)
 
#define CLK_ODC_MASK   (1 << 0)
 
#define CLK_SMMUFIMC_LITE2_MASK   (1 << 20)
 
#define CLK_SMMUFIMC_LITE1_MASK   (1 << 12)
 
#define CLK_SMMUFIMC_LITE0_MASK   (1 << 11)
 
#define CLK_SMMUGSCL3_MASK   (1 << 10)
 
#define CLK_SMMUGSCL2_MASK   (1 << 9)
 
#define CLK_SMMUGSCL1_MASK   (1 << 8)
 
#define CLK_SMMUGSCL0_MASK   (1 << 7)
 
#define CLK_GSCL_WRAP_B_MASK   (1 << 6)
 
#define CLK_GSCL_WRAP_A_MASK   (1 << 5)
 
#define CLK_CAMIF_TOP_MASK   (1 << 4)
 
#define CLK_GSCL3_MASK   (1 << 3)
 
#define CLK_GSCL2_MASK   (1 << 2)
 
#define CLK_GSCL1_MASK   (1 << 1)
 
#define CLK_GSCL0_MASK   (1 << 0)
 
#define CLK_SMMUMFCR_MASK   (1 << 2)
 
#define CLK_SMMUMFCL_MASK   (1 << 1)
 
#define CLK_MFC_MASK   (1 << 0)
 
#define SCLK_MPWM_ISP_MASK   (1 << 0)
 
#define CLK_SMMUTVX_MASK   (1 << 9)
 
#define CLK_ASYNCTVX_MASK   (1 << 7)
 
#define CLK_HDMI_MASK   (1 << 6)
 
#define CLK_MIXER_MASK   (1 << 5)
 
#define CLK_DSIM1_MASK   (1 << 3)
 
#define CLK_SMMUMDMA1_MASK   (1 << 9)
 
#define CLK_SMMUJPEG_MASK   (1 << 7)
 
#define CLK_SMMUROTATOR_MASK   (1 << 6)
 
#define CLK_MDMA1_MASK   (1 << 4)
 
#define CLK_JPEG_MASK   (1 << 2)
 
#define CLK_ROTATOR_MASK   (1 << 1)
 
#define CLK_WDT_IOP_MASK   (1 << 30)
 
#define CLK_SMMUMCU_IOP_MASK   (1 << 26)
 
#define CLK_SATA_PHY_I2C_MASK   (1 << 25)
 
#define CLK_SATA_PHY_CTRL_MASK   (1 << 24)
 
#define CLK_MCUCTL_MASK   (1 << 23)
 
#define CLK_NFCON_MASK   (1 << 22)
 
#define CLK_SMMURTIC_MASK   (1 << 11)
 
#define CLK_RTIC_MASK   (1 << 9)
 
#define CLK_MIPI_HSI_MASK   (1 << 8)
 
#define CLK_USBOTG_MASK   (1 << 7)
 
#define CLK_SATA_MASK   (1 << 6)
 
#define CLK_PDMA1_MASK   (1 << 2)
 
#define CLK_PDMA0_MASK   (1 << 1)
 
#define CLK_MCU_IOP_MASK   (1 << 0)
 
#define CLK_HS_I2C3_MASK   (1 << 31)
 
#define CLK_HS_I2C2_MASK   (1 << 30)
 
#define CLK_HS_I2C1_MASK   (1 << 29)
 
#define CLK_HS_I2C0_MASK   (1 << 28)
 
#define CLK_AC97_MASK   (1 << 27)
 
#define CLK_SPDIF_MASK   (1 << 26)
 
#define CLK_PCM2_MASK   (1 << 23)
 
#define CLK_PCM1_MASK   (1 << 22)
 
#define CLK_I2S2_MASK   (1 << 21)
 
#define CLK_I2S1_MASK   (1 << 20)
 
#define CLK_SPI2_MASK   (1 << 18)
 
#define CLK_SPI0_MASK   (1 << 16)
 
#define CLK_I2CHDMI_MASK   (1 << 14)
 
#define CLK_I2C7_MASK   (1 << 13)
 
#define CLK_I2C6_MASK   (1 << 12)
 
#define CLK_I2C5_MASK   (1 << 11)
 
#define CLK_I2C4_MASK   (1 << 10)
 
#define CLK_I2C3_MASK   (1 << 9)
 
#define CLK_I2C2_MASK   (1 << 8)
 
#define CLK_I2C1_MASK   (1 << 7)
 
#define CLK_I2C0_MASK   (1 << 6)
 
#define CLK_RTC_MASK   (1 << 20)
 
#define CLK_TZPC9_MASK   (1 << 15)
 
#define CLK_TZPC8_MASK   (1 << 14)
 
#define CLK_TZPC7_MASK   (1 << 13)
 
#define CLK_TZPC6_MASK   (1 << 12)
 
#define CLK_TZPC5_MASK   (1 << 11)
 
#define CLK_TZPC4_MASK   (1 << 10)
 
#define CLK_TZPC3_MASK   (1 << 9)
 
#define CLK_TZPC2_MASK   (1 << 8)
 
#define CLK_TZPC1_MASK   (1 << 7)
 
#define CLK_TZPC0_MASK   (1 << 6)
 
#define CLK_CHIPID_MASK   (1 << 0)
 
#define CLK_ACP_MASK   (1 << 7)
 
#define CLK_TZASC_DRBXW_MASK   (1 << 23)
 
#define CLK_TZASC_DRBXR_MASK   (1 << 22)
 
#define CLK_TZASC_XLBXW_MASK   (1 << 21)
 
#define CLK_TZASC_XLBXR_MASK   (1 << 20)
 
#define CLK_TZASC_XR1BXW_MASK   (1 << 19)
 
#define CLK_TZASC_XR1BXR_MASK   (1 << 18)
 
#define CLK_DPHY1_MASK   (1 << 5)
 
#define CLK_DPHY0_MASK   (1 << 4)
 
#define R0SIZE   0x0
 
#define DECPROTXSET   0xFF
 
#define LPDDR3PHY_CTRL_PHY_RESET_DISABLE   (1 << 0)
 
#define LPDDR3PHY_CTRL_PHY_RESET_ENABLE   (0 << 0 )
 
#define PHY_CON0_RESET_VAL   0x17020a40
 
#define P0_CMD_EN   (1 << 14)
 
#define BYTE_RDLVL_EN   (1 << 13)
 
#define CTRL_SHGATE   (1 << 8)
 
#define PHY_CON1_RESET_VAL   0x09210100
 
#define CTRL_GATEDURADJ_MASK   (0xf << 20)
 
#define PHY_CON2_RESET_VAL   0x00010004
 
#define INIT_DESKEW_EN   (1 << 6)
 
#define RDLVL_GATE_EN   (1 << 24)
 
#define PHY_CON16_RESET_VAL   0x08000304
 
#define ZQ_CLK_DIV_EN   (1 << 18)
 
#define ZQ_MANUAL_STR   (1 << 1)
 
#define ZQ_DONE   (1 << 0)
 
#define CTRL_RDLVL_GATE_ENABLE   1
 
#define CTRL_RDLVL_GATE_DISABLE   1
 
#define DIRECT_CMD_NOP   0x07000000
 
#define DIRECT_CMD_PALL   0x01000000
 
#define DIRECT_CMD_ZQINIT   0x0a000000
 
#define DIRECT_CMD_CHANNEL_SHIFT   28
 
#define DIRECT_CMD_CHIP_SHIFT   20
 
#define PHY_CONTROL0_RESET_VAL   0x0
 
#define MEM_TERM_EN   (1 << 31) /* Termination enable for memory */
 
#define PHY_TERM_EN   (1 << 30) /* Termination enable for PHY */
 
#define DMC_CTRL_SHGATE   (1 << 29) /* Duration of DQS gating signal */
 
#define FP_RSYNC   (1 << 3) /* Force DLL resynchronization */
 
#define IMP_OUTPUT_DRV_40_OHM   0x5
 
#define IMP_OUTPUT_DRV_30_OHM   0x7
 
#define CA_CK_DRVR_DS_OFFSET   9
 
#define CA_CKE_DRVR_DS_OFFSET   6
 
#define CA_CS_DRVR_DS_OFFSET   3
 
#define CA_ADR_DRVR_DS_OFFSET   0
 
#define PHY_CON42_CTRL_BSTLEN_SHIFT   8
 
#define PHY_CON42_CTRL_RDLAT_SHIFT   0
 

Enumerations

enum  { SETUP_ERR_OK , SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1 , SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2 }
 

Functions

void cpu_info_init (void)
 
void mem_ctrl_init (void)
 
int ddr3_mem_ctrl_init (struct mem_timings *mem, unsigned long mem_iv_size, int mem_reset)
 
int dmc_config_zq (struct mem_timings *mem, struct exynos5_phy_control *phy0_ctrl, struct exynos5_phy_control *phy1_ctrl)
 
void dmc_config_mrs (struct mem_timings *mem, struct exynos5_dmc *dmc)
 
void dmc_config_prech (struct mem_timings *mem, struct exynos5_dmc *dmc)
 
void dmc_config_memory (struct mem_timings *mem, struct exynos5_dmc *dmc)
 
void update_reset_dll (struct exynos5_dmc *, enum ddr_mode)
 

Macro Definition Documentation

◆ ACLK_133_RATIO

#define ACLK_133_RATIO   0x1

Definition at line 267 of file setup.h.

◆ ACLK_166_RATIO

#define ACLK_166_RATIO   0x1

Definition at line 266 of file setup.h.

◆ ACLK_200_RATIO

#define ACLK_200_RATIO   0x3

Definition at line 265 of file setup.h.

◆ ACLK_266_RATIO

#define ACLK_266_RATIO   0x2

Definition at line 264 of file setup.h.

◆ ACLK_300_DISP1_RATIO

#define ACLK_300_DISP1_RATIO   0x2

Definition at line 261 of file setup.h.

◆ ACLK_300_GSCL_RATIO

#define ACLK_300_GSCL_RATIO   0x2

Definition at line 284 of file setup.h.

◆ ACLK_333_RATIO

#define ACLK_333_RATIO   0x0

Definition at line 263 of file setup.h.

◆ ACLK_400_G3D_RATIO

#define ACLK_400_G3D_RATIO   0x0

Definition at line 262 of file setup.h.

◆ ACLK_400_IOP_RATIO

#define ACLK_400_IOP_RATIO   0x1

Definition at line 283 of file setup.h.

◆ ACLK_400_ISP_RATIO

#define ACLK_400_ISP_RATIO   0x1

Definition at line 282 of file setup.h.

◆ ACLK_66_PRE_RATIO

#define ACLK_66_PRE_RATIO   0x1

Definition at line 281 of file setup.h.

◆ ACLK_66_RATIO

#define ACLK_66_RATIO   0x5

Definition at line 268 of file setup.h.

◆ ACLK_C2C_200_RATIO

#define ACLK_C2C_200_RATIO   0x1

Definition at line 185 of file setup.h.

◆ ACLK_CDREX_RATIO

#define ACLK_CDREX_RATIO   0x1

Definition at line 188 of file setup.h.

◆ ACLK_EFCON_RATIO

#define ACLK_EFCON_RATIO   0x1

Definition at line 182 of file setup.h.

◆ ACLK_MIPI_HSI_TX_BASE_RATIO

#define ACLK_MIPI_HSI_TX_BASE_RATIO   0x3

Definition at line 280 of file setup.h.

◆ APLL_CON0_LOCKED

#define APLL_CON0_LOCKED   (1 << 29)

Definition at line 322 of file setup.h.

◆ APLL_CON1_VAL

#define APLL_CON1_VAL   (0x00203800)

Definition at line 27 of file setup.h.

◆ APLL_FOUT

#define APLL_FOUT   (1 << 0)

Definition at line 24 of file setup.h.

◆ APLL_LOCK_VAL

#define APLL_LOCK_VAL   (0x546)

Definition at line 293 of file setup.h.

◆ AREF_EN

#define AREF_EN   (1 << 5)

Definition at line 113 of file setup.h.

◆ BPLL_CON0_LOCKED

#define BPLL_CON0_LOCKED   (1 << 29)

Definition at line 324 of file setup.h.

◆ BPLL_CON1_VAL

#define BPLL_CON1_VAL   0x00203800

Definition at line 47 of file setup.h.

◆ BPLL_LOCK_VAL

#define BPLL_LOCK_VAL   (0x546)

Definition at line 305 of file setup.h.

◆ BYTE_RDLVL_EN

#define BYTE_RDLVL_EN   (1 << 13)

Definition at line 616 of file setup.h.

◆ C2C_CLK_400_RATIO

#define C2C_CLK_400_RATIO   0x1

Definition at line 186 of file setup.h.

◆ CA_ADR_DRVR_DS_OFFSET

#define CA_ADR_DRVR_DS_OFFSET   0

Definition at line 656 of file setup.h.

◆ CA_CK_DRVR_DS_OFFSET

#define CA_CK_DRVR_DS_OFFSET   9

Definition at line 653 of file setup.h.

◆ CA_CKE_DRVR_DS_OFFSET

#define CA_CKE_DRVR_DS_OFFSET   6

Definition at line 654 of file setup.h.

◆ CA_CS_DRVR_DS_OFFSET

#define CA_CS_DRVR_DS_OFFSET   3

Definition at line 655 of file setup.h.

◆ CLK_3DNR_MASK

#define CLK_3DNR_MASK   (1 << 2)

Definition at line 491 of file setup.h.

◆ CLK_AC97_MASK

#define CLK_AC97_MASK   (1 << 27)

Definition at line 554 of file setup.h.

◆ CLK_ACP_MASK

#define CLK_ACP_MASK   (1 << 7)

Definition at line 587 of file setup.h.

◆ CLK_ARM9S_MASK

#define CLK_ARM9S_MASK   (1 << 6)

Definition at line 476 of file setup.h.

◆ CLK_ASYNCTVX_MASK

#define CLK_ASYNCTVX_MASK   (1 << 7)

Definition at line 520 of file setup.h.

◆ CLK_C2C_MASK

#define CLK_C2C_MASK   (1 << 1)

Definition at line 444 of file setup.h.

◆ CLK_CAMIF_TOP_MASK

#define CLK_CAMIF_TOP_MASK   (1 << 4)

Definition at line 505 of file setup.h.

◆ CLK_CHIPID_MASK

#define CLK_CHIPID_MASK   (1 << 0)

Definition at line 584 of file setup.h.

◆ CLK_DIS_MASK

#define CLK_DIS_MASK   (1 << 1)

Definition at line 492 of file setup.h.

◆ CLK_DIV_ACP_VAL

#define CLK_DIV_ACP_VAL   0x12

Definition at line 172 of file setup.h.

◆ CLK_DIV_CDREX_VAL

#define CLK_DIV_CDREX_VAL
Value:
((MCLK_DPHY_RATIO << 24) \
| (C2C_CLK_400_RATIO << 6) \
| (PCLK_CDREX_RATIO << 4) \
| (ACLK_CDREX_RATIO))
MCLK_DPHY_RATIO
#define MCLK_DPHY_RATIO
Definition: setup.h:183
PCLK_CDREX_RATIO
#define PCLK_CDREX_RATIO
Definition: setup.h:187
C2C_CLK_400_RATIO
#define C2C_CLK_400_RATIO
Definition: setup.h:186
ACLK_CDREX_RATIO
#define ACLK_CDREX_RATIO
Definition: setup.h:188

Definition at line 190 of file setup.h.

◆ CLK_DIV_CORE0_VAL

#define CLK_DIV_CORE0_VAL   0x00120000

Definition at line 163 of file setup.h.

◆ CLK_DIV_CORE1_VAL

#define CLK_DIV_CORE1_VAL   0x07070700

Definition at line 166 of file setup.h.

◆ CLK_DIV_CPU0_VAL

#define CLK_DIV_CPU0_VAL
Value:
((ARM2_RATIO << 28) \
| (APLL_RATIO << 24) \
| (PCLK_DBG_RATIO << 20) \
| (ATB_RATIO << 16) \
| (PERIPH_RATIO << 12) \
| (ACP_RATIO << 8) \
| (CPUD_RATIO << 4) \
| (ARM_RATIO))

Definition at line 135 of file setup.h.

◆ CLK_DIV_CPU1_VAL

#define CLK_DIV_CPU1_VAL
Value:
((HPM_RATIO << 4) \
| (COPY_RATIO))
HPM_RATIO
#define HPM_RATIO
Definition: setup.h:149
COPY_RATIO
#define COPY_RATIO
Definition: setup.h:150

Definition at line 153 of file setup.h.

◆ CLK_DIV_DISP1_0_FIMD1

#define CLK_DIV_DISP1_0_FIMD1   (2 << 0)

Definition at line 438 of file setup.h.

◆ CLK_DIV_FSYS0_VAL

#define CLK_DIV_FSYS0_VAL   0x0BB00000

Definition at line 146 of file setup.h.

◆ CLK_DIV_ISP0_VAL

#define CLK_DIV_ISP0_VAL   0x31

Definition at line 423 of file setup.h.

◆ CLK_DIV_ISP1_VAL

#define CLK_DIV_ISP1_VAL   0x0

Definition at line 426 of file setup.h.

◆ CLK_DIV_ISP2_VAL

#define CLK_DIV_ISP2_VAL   0x1

Definition at line 429 of file setup.h.

◆ CLK_DIV_LEX_VAL

#define CLK_DIV_LEX_VAL   0x10

Definition at line 414 of file setup.h.

◆ CLK_DIV_PERIC0_VAL

#define CLK_DIV_PERIC0_VAL
Value:
((UART3_RATIO << 12) \
| (UART2_RATIO << 8) \
| (UART1_RATIO << 4) \
| (UART0_RATIO))
UART1_RATIO
#define UART1_RATIO
Definition: setup.h:371
UART2_RATIO
#define UART2_RATIO
Definition: setup.h:370
UART3_RATIO
#define UART3_RATIO
Definition: setup.h:369
UART0_RATIO
#define UART0_RATIO
Definition: setup.h:372

Definition at line 374 of file setup.h.

◆ CLK_DIV_PERIC1_VAL

#define CLK_DIV_PERIC1_VAL
Value:
((SPI1_SUB_RATIO << 24) \
| ((SPI1_RATIO << 16) \
| (SPI0_SUB_RATIO << 8) \
| (SPI0_RATIO << 0)))
SPI0_SUB_RATIO
#define SPI0_SUB_RATIO
Definition: setup.h:382
SPI1_SUB_RATIO
#define SPI1_SUB_RATIO
Definition: setup.h:381
SPI0_RATIO
#define SPI0_RATIO
Definition: setup.h:380
SPI1_RATIO
#define SPI1_RATIO
Definition: setup.h:379

Definition at line 383 of file setup.h.

◆ CLK_DIV_PERIC2_VAL

#define CLK_DIV_PERIC2_VAL
Value:
((SPI2_SUB_RATIO << 8) \
| (SPI2_RATIO << 0))
SPI2_RATIO
#define SPI2_RATIO
Definition: setup.h:389
SPI2_SUB_RATIO
#define SPI2_SUB_RATIO
Definition: setup.h:390

Definition at line 391 of file setup.h.

◆ CLK_DIV_R0X_VAL

#define CLK_DIV_R0X_VAL   0x10

Definition at line 417 of file setup.h.

◆ CLK_DIV_R1X_VAL

#define CLK_DIV_R1X_VAL   0x10

Definition at line 420 of file setup.h.

◆ CLK_DIV_SYSLFT_VAL

#define CLK_DIV_SYSLFT_VAL   0x00000311

Definition at line 175 of file setup.h.

◆ CLK_DIV_SYSRGT_VAL

#define CLK_DIV_SYSRGT_VAL   0x00000111

Definition at line 169 of file setup.h.

◆ CLK_DIV_TOP0_VAL

#define CLK_DIV_TOP0_VAL
Value:
((ACLK_300_DISP1_RATIO << 28) \
| (ACLK_400_G3D_RATIO << 24) \
| (ACLK_333_RATIO << 20) \
| (ACLK_266_RATIO << 16) \
| (ACLK_200_RATIO << 12) \
| (ACLK_166_RATIO << 8) \
| (ACLK_133_RATIO << 4) \
| (ACLK_66_RATIO))
ACLK_266_RATIO
#define ACLK_266_RATIO
Definition: setup.h:264
ACLK_400_G3D_RATIO
#define ACLK_400_G3D_RATIO
Definition: setup.h:262
ACLK_200_RATIO
#define ACLK_200_RATIO
Definition: setup.h:265
ACLK_66_RATIO
#define ACLK_66_RATIO
Definition: setup.h:268
ACLK_333_RATIO
#define ACLK_333_RATIO
Definition: setup.h:263
ACLK_133_RATIO
#define ACLK_133_RATIO
Definition: setup.h:267
ACLK_300_DISP1_RATIO
#define ACLK_300_DISP1_RATIO
Definition: setup.h:261
ACLK_166_RATIO
#define ACLK_166_RATIO
Definition: setup.h:266

Definition at line 270 of file setup.h.

◆ CLK_DIV_TOP1_VAL

#define CLK_DIV_TOP1_VAL
Value:
((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
| (ACLK_66_PRE_RATIO << 24) \
| (ACLK_400_ISP_RATIO << 20) \
| (ACLK_400_IOP_RATIO << 16) \
| (ACLK_300_GSCL_RATIO << 12))
ACLK_MIPI_HSI_TX_BASE_RATIO
#define ACLK_MIPI_HSI_TX_BASE_RATIO
Definition: setup.h:280
ACLK_400_ISP_RATIO
#define ACLK_400_ISP_RATIO
Definition: setup.h:282
ACLK_66_PRE_RATIO
#define ACLK_66_PRE_RATIO
Definition: setup.h:281
ACLK_300_GSCL_RATIO
#define ACLK_300_GSCL_RATIO
Definition: setup.h:284
ACLK_400_IOP_RATIO
#define ACLK_400_IOP_RATIO
Definition: setup.h:283

Definition at line 286 of file setup.h.

◆ CLK_DPHY0_MASK

#define CLK_DPHY0_MASK   (1 << 4)

Definition at line 597 of file setup.h.

◆ CLK_DPHY1_MASK

#define CLK_DPHY1_MASK   (1 << 5)

Definition at line 596 of file setup.h.

◆ CLK_DRC_MASK

#define CLK_DRC_MASK   (1 << 1)

Definition at line 481 of file setup.h.

◆ CLK_DSIM1_MASK

#define CLK_DSIM1_MASK   (1 << 3)

Definition at line 523 of file setup.h.

◆ CLK_EFCLK_MASK

#define CLK_EFCLK_MASK   (1 << 16)

Definition at line 457 of file setup.h.

◆ CLK_FD_MASK

#define CLK_FD_MASK   (1 << 2)

Definition at line 480 of file setup.h.

◆ CLK_G2D_MASK

#define CLK_G2D_MASK   (1 << 3)

Definition at line 451 of file setup.h.

◆ CLK_GATE_DP1_ALLOW

#define CLK_GATE_DP1_ALLOW   (1 << 4)

Definition at line 441 of file setup.h.

◆ CLK_GICISP_MASK

#define CLK_GICISP_MASK   (1 << 7)

Definition at line 475 of file setup.h.

◆ CLK_GSCL0_MASK

#define CLK_GSCL0_MASK   (1 << 0)

Definition at line 509 of file setup.h.

◆ CLK_GSCL1_MASK

#define CLK_GSCL1_MASK   (1 << 1)

Definition at line 508 of file setup.h.

◆ CLK_GSCL2_MASK

#define CLK_GSCL2_MASK   (1 << 2)

Definition at line 507 of file setup.h.

◆ CLK_GSCL3_MASK

#define CLK_GSCL3_MASK   (1 << 3)

Definition at line 506 of file setup.h.

◆ CLK_GSCL_WRAP_A_MASK

#define CLK_GSCL_WRAP_A_MASK   (1 << 5)

Definition at line 504 of file setup.h.

◆ CLK_GSCL_WRAP_B_MASK

#define CLK_GSCL_WRAP_B_MASK   (1 << 6)

Definition at line 503 of file setup.h.

◆ CLK_HDMI_MASK

#define CLK_HDMI_MASK   (1 << 6)

Definition at line 521 of file setup.h.

◆ CLK_HS_I2C0_MASK

#define CLK_HS_I2C0_MASK   (1 << 28)

Definition at line 553 of file setup.h.

◆ CLK_HS_I2C1_MASK

#define CLK_HS_I2C1_MASK   (1 << 29)

Definition at line 552 of file setup.h.

◆ CLK_HS_I2C2_MASK

#define CLK_HS_I2C2_MASK   (1 << 30)

Definition at line 551 of file setup.h.

◆ CLK_HS_I2C3_MASK

#define CLK_HS_I2C3_MASK   (1 << 31)

Definition at line 550 of file setup.h.

◆ CLK_I2C0_ISP_MASK

#define CLK_I2C0_ISP_MASK   (1 << 25)

Definition at line 465 of file setup.h.

◆ CLK_I2C0_MASK

#define CLK_I2C0_MASK   (1 << 6)

Definition at line 570 of file setup.h.

◆ CLK_I2C1_ISP_MASK

#define CLK_I2C1_ISP_MASK   (1 << 26)

Definition at line 464 of file setup.h.

◆ CLK_I2C1_MASK

#define CLK_I2C1_MASK   (1 << 7)

Definition at line 569 of file setup.h.

◆ CLK_I2C2_MASK

#define CLK_I2C2_MASK   (1 << 8)

Definition at line 568 of file setup.h.

◆ CLK_I2C3_MASK

#define CLK_I2C3_MASK   (1 << 9)

Definition at line 567 of file setup.h.

◆ CLK_I2C4_MASK

#define CLK_I2C4_MASK   (1 << 10)

Definition at line 566 of file setup.h.

◆ CLK_I2C5_MASK

#define CLK_I2C5_MASK   (1 << 11)

Definition at line 565 of file setup.h.

◆ CLK_I2C6_MASK

#define CLK_I2C6_MASK   (1 << 12)

Definition at line 564 of file setup.h.

◆ CLK_I2C7_MASK

#define CLK_I2C7_MASK   (1 << 13)

Definition at line 563 of file setup.h.

◆ CLK_I2CHDMI_MASK

#define CLK_I2CHDMI_MASK   (1 << 14)

Definition at line 562 of file setup.h.

◆ CLK_I2S1_MASK

#define CLK_I2S1_MASK   (1 << 20)

Definition at line 559 of file setup.h.

◆ CLK_I2S2_MASK

#define CLK_I2S2_MASK   (1 << 21)

Definition at line 558 of file setup.h.

◆ CLK_ID_REMAPPER_MASK

#define CLK_ID_REMAPPER_MASK   (1 << 4)

Definition at line 450 of file setup.h.

◆ CLK_INT_COMB_ISP_MASK

#define CLK_INT_COMB_ISP_MASK   (1 << 22)

Definition at line 468 of file setup.h.

◆ CLK_ISP_MASK

#define CLK_ISP_MASK   (1 << 0)

Definition at line 482 of file setup.h.

◆ CLK_JPEG_MASK

#define CLK_JPEG_MASK   (1 << 2)

Definition at line 530 of file setup.h.

◆ CLK_MCU_IOP_MASK

#define CLK_MCU_IOP_MASK   (1 << 0)

Definition at line 547 of file setup.h.

◆ CLK_MCUCTL_ISP_MASK

#define CLK_MCUCTL_ISP_MASK   (1 << 23)

Definition at line 467 of file setup.h.

◆ CLK_MCUCTL_MASK

#define CLK_MCUCTL_MASK   (1 << 23)

Definition at line 538 of file setup.h.

◆ CLK_MCUISP_MASK

#define CLK_MCUISP_MASK   (1 << 5)

Definition at line 477 of file setup.h.

◆ CLK_MDMA1_MASK

#define CLK_MDMA1_MASK   (1 << 4)

Definition at line 529 of file setup.h.

◆ CLK_MDMA_MASK

#define CLK_MDMA_MASK   (1 << 1)

Definition at line 453 of file setup.h.

◆ CLK_MFC_MASK

#define CLK_MFC_MASK   (1 << 0)

Definition at line 514 of file setup.h.

◆ CLK_MIPI_HSI_MASK

#define CLK_MIPI_HSI_MASK   (1 << 8)

Definition at line 542 of file setup.h.

◆ CLK_MIXER_MASK

#define CLK_MIXER_MASK   (1 << 5)

Definition at line 522 of file setup.h.

◆ CLK_MPWM_ISP_MASK

#define CLK_MPWM_ISP_MASK   (1 << 24)

Definition at line 466 of file setup.h.

◆ CLK_MTCADC_ISP_MASK

#define CLK_MTCADC_ISP_MASK   (1 << 27)

Definition at line 463 of file setup.h.

◆ CLK_NFCON_MASK

#define CLK_NFCON_MASK   (1 << 22)

Definition at line 539 of file setup.h.

◆ CLK_ODC_MASK

#define CLK_ODC_MASK   (1 << 0)

Definition at line 493 of file setup.h.

◆ CLK_PCM1_MASK

#define CLK_PCM1_MASK   (1 << 22)

Definition at line 557 of file setup.h.

◆ CLK_PCM2_MASK

#define CLK_PCM2_MASK   (1 << 23)

Definition at line 556 of file setup.h.

◆ CLK_PDMA0_MASK

#define CLK_PDMA0_MASK   (1 << 1)

Definition at line 546 of file setup.h.

◆ CLK_PDMA1_MASK

#define CLK_PDMA1_MASK   (1 << 2)

Definition at line 545 of file setup.h.

◆ CLK_PWM_ISP_MASK

#define CLK_PWM_ISP_MASK   (1 << 28)

Definition at line 462 of file setup.h.

◆ CLK_REG_DISABLE

#define CLK_REG_DISABLE   0x0

Definition at line 329 of file setup.h.

◆ CLK_ROTATOR_MASK

#define CLK_ROTATOR_MASK   (1 << 1)

Definition at line 531 of file setup.h.

◆ CLK_RTC_MASK

#define CLK_RTC_MASK   (1 << 20)

Definition at line 573 of file setup.h.

◆ CLK_RTIC_MASK

#define CLK_RTIC_MASK   (1 << 9)

Definition at line 541 of file setup.h.

◆ CLK_SATA_MASK

#define CLK_SATA_MASK   (1 << 6)

Definition at line 544 of file setup.h.

◆ CLK_SATA_PHY_CTRL_MASK

#define CLK_SATA_PHY_CTRL_MASK   (1 << 24)

Definition at line 537 of file setup.h.

◆ CLK_SATA_PHY_I2C_MASK

#define CLK_SATA_PHY_I2C_MASK   (1 << 25)

Definition at line 536 of file setup.h.

◆ CLK_SCALERC_MASK

#define CLK_SCALERC_MASK   (1 << 3)

Definition at line 479 of file setup.h.

◆ CLK_SCALERP_MASK

#define CLK_SCALERP_MASK   (1 << 4)

Definition at line 478 of file setup.h.

◆ CLK_SECJTAG_MASK

#define CLK_SECJTAG_MASK   (1 << 0)

Definition at line 454 of file setup.h.

◆ CLK_SMMU3DNR_MASK

#define CLK_SMMU3DNR_MASK   (1 << 7)

Definition at line 487 of file setup.h.

◆ CLK_SMMU_DRC_MASK

#define CLK_SMMU_DRC_MASK   (1 << 9)

Definition at line 473 of file setup.h.

◆ CLK_SMMU_FD_MASK

#define CLK_SMMU_FD_MASK   (1 << 10)

Definition at line 472 of file setup.h.

◆ CLK_SMMU_ISP_MASK

#define CLK_SMMU_ISP_MASK   (1 << 8)

Definition at line 474 of file setup.h.

◆ CLK_SMMU_MCUISP_MASK

#define CLK_SMMU_MCUISP_MASK   (1 << 13)

Definition at line 469 of file setup.h.

◆ CLK_SMMU_SCALERC_MASK

#define CLK_SMMU_SCALERC_MASK   (1 << 11)

Definition at line 471 of file setup.h.

◆ CLK_SMMU_SCALERP_MASK

#define CLK_SMMU_SCALERP_MASK   (1 << 12)

Definition at line 470 of file setup.h.

◆ CLK_SMMUDIS0_MASK

#define CLK_SMMUDIS0_MASK   (1 << 5)

Definition at line 489 of file setup.h.

◆ CLK_SMMUDIS1_MASK

#define CLK_SMMUDIS1_MASK   (1 << 6)

Definition at line 488 of file setup.h.

◆ CLK_SMMUFIMC_LITE0_MASK

#define CLK_SMMUFIMC_LITE0_MASK   (1 << 11)

Definition at line 498 of file setup.h.

◆ CLK_SMMUFIMC_LITE1_MASK

#define CLK_SMMUFIMC_LITE1_MASK   (1 << 12)

Definition at line 497 of file setup.h.

◆ CLK_SMMUFIMC_LITE2_MASK

#define CLK_SMMUFIMC_LITE2_MASK   (1 << 20)

Definition at line 496 of file setup.h.

◆ CLK_SMMUG2D_MASK

#define CLK_SMMUG2D_MASK   (1 << 7)

Definition at line 447 of file setup.h.

◆ CLK_SMMUGSCL0_MASK

#define CLK_SMMUGSCL0_MASK   (1 << 7)

Definition at line 502 of file setup.h.

◆ CLK_SMMUGSCL1_MASK

#define CLK_SMMUGSCL1_MASK   (1 << 8)

Definition at line 501 of file setup.h.

◆ CLK_SMMUGSCL2_MASK

#define CLK_SMMUGSCL2_MASK   (1 << 9)

Definition at line 500 of file setup.h.

◆ CLK_SMMUGSCL3_MASK

#define CLK_SMMUGSCL3_MASK   (1 << 10)

Definition at line 499 of file setup.h.

◆ CLK_SMMUJPEG_MASK

#define CLK_SMMUJPEG_MASK   (1 << 7)

Definition at line 527 of file setup.h.

◆ CLK_SMMUMCU_IOP_MASK

#define CLK_SMMUMCU_IOP_MASK   (1 << 26)

Definition at line 535 of file setup.h.

◆ CLK_SMMUMDMA1_MASK

#define CLK_SMMUMDMA1_MASK   (1 << 9)

Definition at line 526 of file setup.h.

◆ CLK_SMMUMDMA_MASK

#define CLK_SMMUMDMA_MASK   (1 << 5)

Definition at line 449 of file setup.h.

◆ CLK_SMMUMFCL_MASK

#define CLK_SMMUMFCL_MASK   (1 << 1)

Definition at line 513 of file setup.h.

◆ CLK_SMMUMFCR_MASK

#define CLK_SMMUMFCR_MASK   (1 << 2)

Definition at line 512 of file setup.h.

◆ CLK_SMMUODC_MASK

#define CLK_SMMUODC_MASK   (1 << 4)

Definition at line 490 of file setup.h.

◆ CLK_SMMUROTATOR_MASK

#define CLK_SMMUROTATOR_MASK   (1 << 6)

Definition at line 528 of file setup.h.

◆ CLK_SMMURTIC_MASK

#define CLK_SMMURTIC_MASK   (1 << 11)

Definition at line 540 of file setup.h.

◆ CLK_SMMUSSS_MASK

#define CLK_SMMUSSS_MASK   (1 << 6)

Definition at line 448 of file setup.h.

◆ CLK_SMMUTVX_MASK

#define CLK_SMMUTVX_MASK   (1 << 9)

Definition at line 519 of file setup.h.

◆ CLK_SPDIF_MASK

#define CLK_SPDIF_MASK   (1 << 26)

Definition at line 555 of file setup.h.

◆ CLK_SPI0_ISP_MASK

#define CLK_SPI0_ISP_MASK   (1 << 12)

Definition at line 486 of file setup.h.

◆ CLK_SPI0_MASK

#define CLK_SPI0_MASK   (1 << 16)

Definition at line 561 of file setup.h.

◆ CLK_SPI1_ISP_MASK

#define CLK_SPI1_ISP_MASK   (1 << 13)

Definition at line 485 of file setup.h.

◆ CLK_SPI2_MASK

#define CLK_SPI2_MASK   (1 << 18)

Definition at line 560 of file setup.h.

◆ CLK_SRC_CDREX_VAL

#define CLK_SRC_CDREX_VAL   0x1

Definition at line 178 of file setup.h.

◆ CLK_SRC_CORE0_VAL

#define CLK_SRC_CORE0_VAL   0x00000000

Definition at line 157 of file setup.h.

◆ CLK_SRC_CORE1_VAL

#define CLK_SRC_CORE1_VAL   0x100

Definition at line 160 of file setup.h.

◆ CLK_SRC_CPU_VAL

#define CLK_SRC_CPU_VAL
Value:
((MUX_HPM_SEL << 20) \
| (MUX_CPU_SEL << 16) \
| (MUX_APLL_SEL))
MUX_HPM_SEL
#define MUX_HPM_SEL
Definition: setup.h:54
MUX_APLL_SEL
#define MUX_APLL_SEL
Definition: setup.h:56
MUX_CPU_SEL
#define MUX_CPU_SEL
Definition: setup.h:55

Definition at line 58 of file setup.h.

◆ CLK_SRC_DISP1_0_VAL

#define CLK_SRC_DISP1_0_VAL   0x6

Definition at line 432 of file setup.h.

◆ CLK_SRC_FSYS0_VAL

#define CLK_SRC_FSYS0_VAL   0x66666

Definition at line 145 of file setup.h.

◆ CLK_SRC_LEX_VAL

#define CLK_SRC_LEX_VAL   0x0

Definition at line 411 of file setup.h.

◆ CLK_SRC_PERIC0_VAL

#define CLK_SRC_PERIC0_VAL
Value:
((PWM_SEL << 24) \
| (UART3_SEL << 12) \
| (UART2_SEL << 8) \
| (UART1_SEL << 4) \
| (UART0_SEL))
UART2_SEL
#define UART2_SEL
Definition: setup.h:335
PWM_SEL
#define PWM_SEL
Definition: setup.h:333
UART1_SEL
#define UART1_SEL
Definition: setup.h:336
UART3_SEL
#define UART3_SEL
Definition: setup.h:334
UART0_SEL
#define UART0_SEL
Definition: setup.h:337

Definition at line 339 of file setup.h.

◆ CLK_SRC_PERIC1_VAL

#define CLK_SRC_PERIC1_VAL
Value:
((SPI2_SEL << 24) \
| (SPI1_SEL << 20) \
| (SPI0_SEL << 16))
SPI1_SEL
#define SPI1_SEL
Definition: setup.h:348
SPI0_SEL
#define SPI0_SEL
Definition: setup.h:347
SPI2_SEL
#define SPI2_SEL
Definition: setup.h:349

Definition at line 350 of file setup.h.

◆ CLK_SRC_TOP0_VAL

#define CLK_SRC_TOP0_VAL
Value:
((MUX_ACLK_300_GSCL_SEL << 25) \
| (MUX_ACLK_300_GSCL_MID_SEL << 24) \
| (MUX_ACLK_400_G3D_MID_SEL << 20) \
| (MUX_ACLK_333_SEL << 16) \
| (MUX_ACLK_300_DISP1_SEL << 15) \
| (MUX_ACLK_300_DISP1_MID_SEL << 14) \
| (MUX_ACLK_200_SEL << 12) \
| (MUX_ACLK_166_SEL << 8))
MUX_ACLK_300_DISP1_SEL
#define MUX_ACLK_300_DISP1_SEL
Definition: setup.h:200
MUX_ACLK_300_GSCL_SEL
#define MUX_ACLK_300_GSCL_SEL
Definition: setup.h:196
MUX_ACLK_333_SEL
#define MUX_ACLK_333_SEL
Definition: setup.h:199
MUX_ACLK_200_SEL
#define MUX_ACLK_200_SEL
Definition: setup.h:202
MUX_ACLK_400_G3D_MID_SEL
#define MUX_ACLK_400_G3D_MID_SEL
Definition: setup.h:198
MUX_ACLK_300_DISP1_MID_SEL
#define MUX_ACLK_300_DISP1_MID_SEL
Definition: setup.h:201
MUX_ACLK_300_GSCL_MID_SEL
#define MUX_ACLK_300_GSCL_MID_SEL
Definition: setup.h:197
MUX_ACLK_166_SEL
#define MUX_ACLK_166_SEL
Definition: setup.h:203

Definition at line 204 of file setup.h.

◆ CLK_SRC_TOP1_VAL

#define CLK_SRC_TOP1_VAL
Value:
((MUX_ACLK_400_G3D_SEL << 28) \
|(MUX_ACLK_400_ISP_SEL << 24) \
|(MUX_ACLK_400_IOP_SEL << 20) \
|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
|(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
|(MUX_ACLK_300_DISP1_MID1_SEL << 8))
MUX_ACLK_MIPI_HSI_TXBASE_SEL
#define MUX_ACLK_MIPI_HSI_TXBASE_SEL
Definition: setup.h:217
MUX_ACLK_400_G3D_SEL
#define MUX_ACLK_400_G3D_SEL
Definition: setup.h:214
MUX_ACLK_400_ISP_SEL
#define MUX_ACLK_400_ISP_SEL
Definition: setup.h:215
MUX_ACLK_300_GSCL_MID1_SEL
#define MUX_ACLK_300_GSCL_MID1_SEL
Definition: setup.h:218
MUX_ACLK_300_DISP1_MID1_SEL
#define MUX_ACLK_300_DISP1_MID1_SEL
Definition: setup.h:219
MUX_ACLK_400_IOP_SEL
#define MUX_ACLK_400_IOP_SEL
Definition: setup.h:216

Definition at line 220 of file setup.h.

◆ CLK_SRC_TOP2_VAL

#define CLK_SRC_TOP2_VAL
Value:
((MUX_GPLL_SEL << 28) \
| (MUX_BPLL_USER_SEL << 24) \
| (MUX_MPLL_USER_SEL << 20) \
| (MUX_VPLL_SEL << 16) \
| (MUX_EPLL_SEL << 12) \
| (MUX_CPLL_SEL << 8) \
| (VPLLSRC_SEL))
MUX_BPLL_USER_SEL
#define MUX_BPLL_USER_SEL
Definition: setup.h:229
MUX_EPLL_SEL
#define MUX_EPLL_SEL
Definition: setup.h:232
VPLLSRC_SEL
#define VPLLSRC_SEL
Definition: setup.h:234
MUX_GPLL_SEL
#define MUX_GPLL_SEL
Definition: setup.h:228
MUX_CPLL_SEL
#define MUX_CPLL_SEL
Definition: setup.h:233
MUX_VPLL_SEL
#define MUX_VPLL_SEL
Definition: setup.h:231
MUX_MPLL_USER_SEL
#define MUX_MPLL_USER_SEL
Definition: setup.h:230

Definition at line 235 of file setup.h.

◆ CLK_SRC_TOP3_VAL

#define CLK_SRC_TOP3_VAL
Value:
((MUX_ACLK_333_SUB_SEL << 24) \
| (MUX_ACLK_400_SUB_SEL << 20) \
| (MUX_ACLK_266_ISP_SUB_SEL << 16) \
| (MUX_ACLK_266_GPS_SUB_SEL << 12) \
| (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
| (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
MUX_ACLK_300_GSCL_SUB_SEL
#define MUX_ACLK_300_GSCL_SUB_SEL
Definition: setup.h:247
MUX_ACLK_266_GPS_SUB_SEL
#define MUX_ACLK_266_GPS_SUB_SEL
Definition: setup.h:246
MUX_ACLK_266_GSCL_SUB_SEL
#define MUX_ACLK_266_GSCL_SUB_SEL
Definition: setup.h:248
MUX_ACLK_333_SUB_SEL
#define MUX_ACLK_333_SUB_SEL
Definition: setup.h:243
MUX_ACLK_200_DISP1_SUB_SEL
#define MUX_ACLK_200_DISP1_SUB_SEL
Definition: setup.h:250
MUX_ACLK_266_ISP_SUB_SEL
#define MUX_ACLK_266_ISP_SUB_SEL
Definition: setup.h:245
MUX_ACLK_300_DISP1_SUB_SEL
#define MUX_ACLK_300_DISP1_SUB_SEL
Definition: setup.h:249
MUX_ACLK_400_SUB_SEL
#define MUX_ACLK_400_SUB_SEL
Definition: setup.h:244

Definition at line 251 of file setup.h.

◆ CLK_SSS_MASK

#define CLK_SSS_MASK   (1 << 2)

Definition at line 452 of file setup.h.

◆ CLK_STOP_EN

#define CLK_STOP_EN   (1 << 0)

Definition at line 121 of file setup.h.

◆ CLK_TZASC_DRBXR_MASK

#define CLK_TZASC_DRBXR_MASK   (1 << 22)

Definition at line 591 of file setup.h.

◆ CLK_TZASC_DRBXW_MASK

#define CLK_TZASC_DRBXW_MASK   (1 << 23)

Definition at line 590 of file setup.h.

◆ CLK_TZASC_XLBXR_MASK

#define CLK_TZASC_XLBXR_MASK   (1 << 20)

Definition at line 593 of file setup.h.

◆ CLK_TZASC_XLBXW_MASK

#define CLK_TZASC_XLBXW_MASK   (1 << 21)

Definition at line 592 of file setup.h.

◆ CLK_TZASC_XR1BXR_MASK

#define CLK_TZASC_XR1BXR_MASK   (1 << 18)

Definition at line 595 of file setup.h.

◆ CLK_TZASC_XR1BXW_MASK

#define CLK_TZASC_XR1BXW_MASK   (1 << 19)

Definition at line 594 of file setup.h.

◆ CLK_TZPC0_MASK

#define CLK_TZPC0_MASK   (1 << 6)

Definition at line 583 of file setup.h.

◆ CLK_TZPC1_MASK

#define CLK_TZPC1_MASK   (1 << 7)

Definition at line 582 of file setup.h.

◆ CLK_TZPC2_MASK

#define CLK_TZPC2_MASK   (1 << 8)

Definition at line 581 of file setup.h.

◆ CLK_TZPC3_MASK

#define CLK_TZPC3_MASK   (1 << 9)

Definition at line 580 of file setup.h.

◆ CLK_TZPC4_MASK

#define CLK_TZPC4_MASK   (1 << 10)

Definition at line 579 of file setup.h.

◆ CLK_TZPC5_MASK

#define CLK_TZPC5_MASK   (1 << 11)

Definition at line 578 of file setup.h.

◆ CLK_TZPC6_MASK

#define CLK_TZPC6_MASK   (1 << 12)

Definition at line 577 of file setup.h.

◆ CLK_TZPC7_MASK

#define CLK_TZPC7_MASK   (1 << 13)

Definition at line 576 of file setup.h.

◆ CLK_TZPC8_MASK

#define CLK_TZPC8_MASK   (1 << 14)

Definition at line 575 of file setup.h.

◆ CLK_TZPC9_MASK

#define CLK_TZPC9_MASK   (1 << 15)

Definition at line 574 of file setup.h.

◆ CLK_UART_ISP_MASK

#define CLK_UART_ISP_MASK   (1 << 31)

Definition at line 460 of file setup.h.

◆ CLK_USBOTG_MASK

#define CLK_USBOTG_MASK   (1 << 7)

Definition at line 543 of file setup.h.

◆ CLK_WDT_IOP_MASK

#define CLK_WDT_IOP_MASK   (1 << 30)

Definition at line 534 of file setup.h.

◆ CLK_WDT_ISP_MASK

#define CLK_WDT_ISP_MASK   (1 << 30)

Definition at line 461 of file setup.h.

◆ COPY_RATIO

#define COPY_RATIO   0x0

Definition at line 150 of file setup.h.

◆ CPLL_CON0_LOCKED

#define CPLL_CON0_LOCKED   (1 << 29)

Definition at line 325 of file setup.h.

◆ CPLL_CON1_VAL

#define CPLL_CON1_VAL   (0x00203800)

Definition at line 33 of file setup.h.

◆ CPLL_LOCK_VAL

#define CPLL_LOCK_VAL   (0x546)

Definition at line 297 of file setup.h.

◆ CTRL_GATEDURADJ_MASK

#define CTRL_GATEDURADJ_MASK   (0xf << 20)

Definition at line 620 of file setup.h.

◆ CTRL_RDLVL_GATE_DISABLE

#define CTRL_RDLVL_GATE_DISABLE   1

Definition at line 634 of file setup.h.

◆ CTRL_RDLVL_GATE_ENABLE

#define CTRL_RDLVL_GATE_ENABLE   1

Definition at line 633 of file setup.h.

◆ CTRL_SHGATE

#define CTRL_SHGATE   (1 << 8)

Definition at line 617 of file setup.h.

◆ DECPROTXSET

#define DECPROTXSET   0xFF

Definition at line 609 of file setup.h.

◆ DFI_INIT_COMPLETE_CH1

#define DFI_INIT_COMPLETE_CH1   (1 << 3)

Definition at line 116 of file setup.h.

◆ DFI_INIT_COMPLETE_CHO

#define DFI_INIT_COMPLETE_CHO   (1 << 2)

Definition at line 115 of file setup.h.

◆ DFI_INIT_START

#define DFI_INIT_START   (1 << 28)

Definition at line 111 of file setup.h.

◆ DIRECT_CMD_CHANNEL_SHIFT

#define DIRECT_CMD_CHANNEL_SHIFT   28

Definition at line 640 of file setup.h.

◆ DIRECT_CMD_CHIP_SHIFT

#define DIRECT_CMD_CHIP_SHIFT   20

Definition at line 641 of file setup.h.

◆ DIRECT_CMD_NOP

#define DIRECT_CMD_NOP   0x07000000

Definition at line 637 of file setup.h.

◆ DIRECT_CMD_PALL

#define DIRECT_CMD_PALL   0x01000000

Definition at line 638 of file setup.h.

◆ DIRECT_CMD_ZQINIT

#define DIRECT_CMD_ZQINIT   0x0a000000

Definition at line 639 of file setup.h.

◆ DMC_CONCONTROL_AREF_EN_DISABLE

#define DMC_CONCONTROL_AREF_EN_DISABLE   (0 << 5)

Definition at line 127 of file setup.h.

◆ DMC_CONCONTROL_DFI_INIT_START_DISABLE

#define DMC_CONCONTROL_DFI_INIT_START_DISABLE   (0 << 28)

Definition at line 132 of file setup.h.

◆ DMC_CONCONTROL_EMPTY_DISABLE

#define DMC_CONCONTROL_EMPTY_DISABLE   (0 << 8)

Definition at line 128 of file setup.h.

◆ DMC_CONCONTROL_EMPTY_ENABLE

#define DMC_CONCONTROL_EMPTY_ENABLE   (1 << 8)

Definition at line 129 of file setup.h.

◆ DMC_CONCONTROL_IO_PD_CON_DISABLE

#define DMC_CONCONTROL_IO_PD_CON_DISABLE   (0 << 3)

Definition at line 126 of file setup.h.

◆ DMC_CONCONTROL_RD_FETCH_DISABLE

#define DMC_CONCONTROL_RD_FETCH_DISABLE   (0x0 << 12)

Definition at line 130 of file setup.h.

◆ DMC_CONCONTROL_RESET_VAL

#define DMC_CONCONTROL_RESET_VAL   0x0FFF0000

Definition at line 110 of file setup.h.

◆ DMC_CONCONTROL_TIMEOUT_LEVEL0

#define DMC_CONCONTROL_TIMEOUT_LEVEL0   (0xFFF << 16)

Definition at line 131 of file setup.h.

◆ DMC_CTRL_SHGATE

#define DMC_CTRL_SHGATE   (1 << 29) /* Duration of DQS gating signal */

Definition at line 647 of file setup.h.

◆ DMC_MEMBASECONFIG0_VAL

#define DMC_MEMBASECONFIG0_VAL   DMC_MEMBASECONFIG_VAL(0x40)

Definition at line 104 of file setup.h.

◆ DMC_MEMBASECONFIG1_VAL

#define DMC_MEMBASECONFIG1_VAL   DMC_MEMBASECONFIG_VAL(0x80)

Definition at line 105 of file setup.h.

◆ DMC_MEMBASECONFIG_VAL

#define DMC_MEMBASECONFIG_VAL (   x)
Value:
( \
DMC_MEMBASECONFIGx_CHIP_BASE(x) | \
DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \
)
x
int x
Definition: edid.c:994

Definition at line 99 of file setup.h.

◆ DMC_MEMBASECONFIGx_CHIP_BASE

#define DMC_MEMBASECONFIGx_CHIP_BASE (   x)    (x << 16)

Definition at line 97 of file setup.h.

◆ DMC_MEMBASECONFIGx_CHIP_MASK

#define DMC_MEMBASECONFIGx_CHIP_MASK (   x)    (x << 0)

Definition at line 98 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_BANK_8

#define DMC_MEMCONFIGx_CHIP_BANK_8   (3 << 0)

Definition at line 95 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_COL_10

#define DMC_MEMCONFIGx_CHIP_COL_10   (3 << 8)

Definition at line 92 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED

#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED   (1 << 12)

Definition at line 91 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_ROW_14

#define DMC_MEMCONFIGx_CHIP_ROW_14   (2 << 4)

Definition at line 93 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_ROW_15

#define DMC_MEMCONFIGx_CHIP_ROW_15   (3 << 4)

Definition at line 94 of file setup.h.

◆ DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE

#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE (   x)    (x << 6)

Definition at line 69 of file setup.h.

◆ DMC_MEMCONTROL_BL_4

#define DMC_MEMCONTROL_BL_4   (2 << 20)

Definition at line 81 of file setup.h.

◆ DMC_MEMCONTROL_BL_8

#define DMC_MEMCONTROL_BL_8   (3 << 20)

Definition at line 80 of file setup.h.

◆ DMC_MEMCONTROL_CLK_STOP_DISABLE

#define DMC_MEMCONTROL_CLK_STOP_DISABLE   (0 << 0)

Definition at line 63 of file setup.h.

◆ DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE

#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE   (0 << 2)

Definition at line 65 of file setup.h.

◆ DMC_MEMCONTROL_DPWRDN_DISABLE

#define DMC_MEMCONTROL_DPWRDN_DISABLE   (0 << 1)

Definition at line 64 of file setup.h.

◆ DMC_MEMCONTROL_DSREF_DISABLE

#define DMC_MEMCONTROL_DSREF_DISABLE   (0 << 5)

Definition at line 67 of file setup.h.

◆ DMC_MEMCONTROL_DSREF_ENABLE

#define DMC_MEMCONTROL_DSREF_ENABLE   (1 << 5)

Definition at line 68 of file setup.h.

◆ DMC_MEMCONTROL_MEM_TYPE_DDR3

#define DMC_MEMCONTROL_MEM_TYPE_DDR3   (6 << 8)

Definition at line 72 of file setup.h.

◆ DMC_MEMCONTROL_MEM_TYPE_LPDDR2

#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2   (5 << 8)

Definition at line 73 of file setup.h.

◆ DMC_MEMCONTROL_MEM_TYPE_LPDDR3

#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3   (7 << 8)

Definition at line 71 of file setup.h.

◆ DMC_MEMCONTROL_MEM_WIDTH_32BIT

#define DMC_MEMCONTROL_MEM_WIDTH_32BIT   (2 << 12)

Definition at line 75 of file setup.h.

◆ DMC_MEMCONTROL_MRR_BYTE_15_8

#define DMC_MEMCONTROL_MRR_BYTE_15_8   (1 << 25)

Definition at line 86 of file setup.h.

◆ DMC_MEMCONTROL_MRR_BYTE_23_16

#define DMC_MEMCONTROL_MRR_BYTE_23_16   (2 << 25)

Definition at line 87 of file setup.h.

◆ DMC_MEMCONTROL_MRR_BYTE_31_24

#define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)

Definition at line 88 of file setup.h.

◆ DMC_MEMCONTROL_MRR_BYTE_7_0

#define DMC_MEMCONTROL_MRR_BYTE_7_0   (0 << 25)

Definition at line 85 of file setup.h.

◆ DMC_MEMCONTROL_NUM_CHIP_1

#define DMC_MEMCONTROL_NUM_CHIP_1   (0 << 16)

Definition at line 77 of file setup.h.

◆ DMC_MEMCONTROL_NUM_CHIP_2

#define DMC_MEMCONTROL_NUM_CHIP_2   (1 << 16)

Definition at line 78 of file setup.h.

◆ DMC_MEMCONTROL_PZQ_DISABLE

#define DMC_MEMCONTROL_PZQ_DISABLE   (0 << 24)

Definition at line 83 of file setup.h.

◆ DMC_MEMCONTROL_TP_DISABLE

#define DMC_MEMCONTROL_TP_DISABLE   (0 << 4)

Definition at line 66 of file setup.h.

◆ DMC_PRECHCONFIG_VAL

#define DMC_PRECHCONFIG_VAL   0xFF000000

Definition at line 107 of file setup.h.

◆ DMC_PWRDNCONFIG_VAL

#define DMC_PWRDNCONFIG_VAL   0xFFFF00FF

Definition at line 108 of file setup.h.

◆ DPWRDN_EN

#define DPWRDN_EN   (1 << 1)

Definition at line 122 of file setup.h.

◆ DSREF_EN

#define DSREF_EN   (1 << 5)

Definition at line 123 of file setup.h.

◆ EMPTY

#define EMPTY   (1 << 8)

Definition at line 112 of file setup.h.

◆ EPLL_CON0_LOCKED

#define EPLL_CON0_LOCKED   (1 << 29)

Definition at line 326 of file setup.h.

◆ EPLL_CON1_VAL

#define EPLL_CON1_VAL   0x00000000

Definition at line 39 of file setup.h.

◆ EPLL_CON2_VAL

#define EPLL_CON2_VAL   0x00000080

Definition at line 40 of file setup.h.

◆ EPLL_LOCK_VAL

#define EPLL_LOCK_VAL   (0x3A98)

Definition at line 301 of file setup.h.

◆ FP_RSYNC

#define FP_RSYNC   (1 << 3) /* Force DLL resynchronization */

Definition at line 648 of file setup.h.

◆ GPLL_CON0_LOCKED

#define GPLL_CON0_LOCKED   (1 << 29)

Definition at line 327 of file setup.h.

◆ GPLL_CON1_VAL

#define GPLL_CON1_VAL   (0x00203800)

Definition at line 36 of file setup.h.

◆ GPLL_LOCK_VAL

#define GPLL_LOCK_VAL   (0x546)

Definition at line 299 of file setup.h.

◆ HPM_RATIO

#define HPM_RATIO   0x2

Definition at line 149 of file setup.h.

◆ HPM_SEL_SCLK_MPLL

#define HPM_SEL_SCLK_MPLL   (1 << 21)

Definition at line 321 of file setup.h.

◆ IMP_OUTPUT_DRV_30_OHM

#define IMP_OUTPUT_DRV_30_OHM   0x7

Definition at line 652 of file setup.h.

◆ IMP_OUTPUT_DRV_40_OHM

#define IMP_OUTPUT_DRV_40_OHM   0x5

Definition at line 651 of file setup.h.

◆ INIT_DESKEW_EN

#define INIT_DESKEW_EN   (1 << 6)

Definition at line 623 of file setup.h.

◆ LPDDR3PHY_CTRL_PHY_RESET_DISABLE

#define LPDDR3PHY_CTRL_PHY_RESET_DISABLE   (1 << 0)

Definition at line 611 of file setup.h.

◆ LPDDR3PHY_CTRL_PHY_RESET_ENABLE

#define LPDDR3PHY_CTRL_PHY_RESET_ENABLE   (0 << 0 )

Definition at line 612 of file setup.h.

◆ MCLK_CDREX2_RATIO

#define MCLK_CDREX2_RATIO   0x0

Definition at line 181 of file setup.h.

◆ MCLK_CDREX_RATIO

#define MCLK_CDREX_RATIO   0x1

Definition at line 184 of file setup.h.

◆ MCLK_DPHY_RATIO

#define MCLK_DPHY_RATIO   0x1

Definition at line 183 of file setup.h.

◆ MEM_TERM_EN

#define MEM_TERM_EN   (1 << 31) /* Termination enable for memory */

Definition at line 645 of file setup.h.

◆ MMC2_PRE_RATIO_MASK

#define MMC2_PRE_RATIO_MASK   0xff

Definition at line 398 of file setup.h.

◆ MMC2_PRE_RATIO_OFFSET

#define MMC2_PRE_RATIO_OFFSET   8

Definition at line 400 of file setup.h.

◆ MMC2_PRE_RATIO_VAL

#define MMC2_PRE_RATIO_VAL   0x9

Definition at line 399 of file setup.h.

◆ MMC2_RATIO_MASK

#define MMC2_RATIO_MASK   0xf

Definition at line 394 of file setup.h.

◆ MMC2_RATIO_OFFSET

#define MMC2_RATIO_OFFSET   0

Definition at line 396 of file setup.h.

◆ MMC2_RATIO_VAL

#define MMC2_RATIO_VAL   0x3

Definition at line 395 of file setup.h.

◆ MMC3_PRE_RATIO_MASK

#define MMC3_PRE_RATIO_MASK   0xff

Definition at line 406 of file setup.h.

◆ MMC3_PRE_RATIO_OFFSET

#define MMC3_PRE_RATIO_OFFSET   24

Definition at line 408 of file setup.h.

◆ MMC3_PRE_RATIO_VAL

#define MMC3_PRE_RATIO_VAL   0x0

Definition at line 407 of file setup.h.

◆ MMC3_RATIO_MASK

#define MMC3_RATIO_MASK   0xf

Definition at line 402 of file setup.h.

◆ MMC3_RATIO_OFFSET

#define MMC3_RATIO_OFFSET   16

Definition at line 404 of file setup.h.

◆ MMC3_RATIO_VAL

#define MMC3_RATIO_VAL   0x1

Definition at line 403 of file setup.h.

◆ MPLL_CON0_LOCKED

#define MPLL_CON0_LOCKED   (1 << 29)

Definition at line 323 of file setup.h.

◆ MPLL_CON1_VAL

#define MPLL_CON1_VAL   (0x00203800)

Definition at line 30 of file setup.h.

◆ MPLL_LOCK_VAL

#define MPLL_LOCK_VAL   (0x546)

Definition at line 295 of file setup.h.

◆ MPLL_SEL_MOUT_MPLLFOUT

#define MPLL_SEL_MOUT_MPLLFOUT   (2 << 8)

Definition at line 314 of file setup.h.

◆ MUX_ACLK_166_SEL

#define MUX_ACLK_166_SEL   0x0

Definition at line 203 of file setup.h.

◆ MUX_ACLK_200_DISP1_SUB_SEL

#define MUX_ACLK_200_DISP1_SUB_SEL   0x1

Definition at line 250 of file setup.h.

◆ MUX_ACLK_200_SEL

#define MUX_ACLK_200_SEL   0x0

Definition at line 202 of file setup.h.

◆ MUX_ACLK_266_GPS_SUB_SEL

#define MUX_ACLK_266_GPS_SUB_SEL   0x0

Definition at line 246 of file setup.h.

◆ MUX_ACLK_266_GSCL_SUB_SEL

#define MUX_ACLK_266_GSCL_SUB_SEL   0x1

Definition at line 248 of file setup.h.

◆ MUX_ACLK_266_ISP_SUB_SEL

#define MUX_ACLK_266_ISP_SUB_SEL   0x1

Definition at line 245 of file setup.h.

◆ MUX_ACLK_300_DISP1_MID1_SEL

#define MUX_ACLK_300_DISP1_MID1_SEL   0x0

Definition at line 219 of file setup.h.

◆ MUX_ACLK_300_DISP1_MID_SEL

#define MUX_ACLK_300_DISP1_MID_SEL   0x0

Definition at line 201 of file setup.h.

◆ MUX_ACLK_300_DISP1_SEL

#define MUX_ACLK_300_DISP1_SEL   0x0

Definition at line 200 of file setup.h.

◆ MUX_ACLK_300_DISP1_SUB_SEL

#define MUX_ACLK_300_DISP1_SUB_SEL   0x1

Definition at line 249 of file setup.h.

◆ MUX_ACLK_300_GSCL_MID1_SEL

#define MUX_ACLK_300_GSCL_MID1_SEL   0x0

Definition at line 218 of file setup.h.

◆ MUX_ACLK_300_GSCL_MID_SEL

#define MUX_ACLK_300_GSCL_MID_SEL   0x0

Definition at line 197 of file setup.h.

◆ MUX_ACLK_300_GSCL_SEL

#define MUX_ACLK_300_GSCL_SEL   0x0

Definition at line 196 of file setup.h.

◆ MUX_ACLK_300_GSCL_SUB_SEL

#define MUX_ACLK_300_GSCL_SUB_SEL   0x1

Definition at line 247 of file setup.h.

◆ MUX_ACLK_333_SEL

#define MUX_ACLK_333_SEL   0x0

Definition at line 199 of file setup.h.

◆ MUX_ACLK_333_SUB_SEL

#define MUX_ACLK_333_SUB_SEL   0x1

Definition at line 243 of file setup.h.

◆ MUX_ACLK_400_G3D_MID_SEL

#define MUX_ACLK_400_G3D_MID_SEL   0x0

Definition at line 198 of file setup.h.

◆ MUX_ACLK_400_G3D_SEL

#define MUX_ACLK_400_G3D_SEL   0x1

Definition at line 214 of file setup.h.

◆ MUX_ACLK_400_IOP_SEL

#define MUX_ACLK_400_IOP_SEL   0x0

Definition at line 216 of file setup.h.

◆ MUX_ACLK_400_ISP_SEL

#define MUX_ACLK_400_ISP_SEL   0x0

Definition at line 215 of file setup.h.

◆ MUX_ACLK_400_SUB_SEL

#define MUX_ACLK_400_SUB_SEL   0x1

Definition at line 244 of file setup.h.

◆ MUX_ACLK_MIPI_HSI_TXBASE_SEL

#define MUX_ACLK_MIPI_HSI_TXBASE_SEL   0x0

Definition at line 217 of file setup.h.

◆ MUX_APLL_SEL

#define MUX_APLL_SEL   1

Definition at line 56 of file setup.h.

◆ MUX_APLL_SEL_MASK

#define MUX_APLL_SEL_MASK   (1 << 0)

Definition at line 310 of file setup.h.

◆ MUX_BPLL_FOUT_SEL

#define MUX_BPLL_FOUT_SEL   (1 << 0)

Definition at line 312 of file setup.h.

◆ MUX_BPLL_SEL_MASK

#define MUX_BPLL_SEL_MASK   (1 << 0)

Definition at line 319 of file setup.h.

◆ MUX_BPLL_USER_SEL

#define MUX_BPLL_USER_SEL   0x0

Definition at line 229 of file setup.h.

◆ MUX_CPLL_SEL

#define MUX_CPLL_SEL   0x1

Definition at line 233 of file setup.h.

◆ MUX_CPLL_SEL_MASK

#define MUX_CPLL_SEL_MASK   (1 << 8)

Definition at line 315 of file setup.h.

◆ MUX_CPU_SEL

#define MUX_CPU_SEL   0

Definition at line 55 of file setup.h.

◆ MUX_EPLL_SEL

#define MUX_EPLL_SEL   0x1

Definition at line 232 of file setup.h.

◆ MUX_EPLL_SEL_MASK

#define MUX_EPLL_SEL_MASK   (1 << 12)

Definition at line 316 of file setup.h.

◆ MUX_GPLL_SEL

#define MUX_GPLL_SEL   0x1

Definition at line 228 of file setup.h.

◆ MUX_GPLL_SEL_MASK

#define MUX_GPLL_SEL_MASK   (1 << 28)

Definition at line 318 of file setup.h.

◆ MUX_HPM_SEL

#define MUX_HPM_SEL   0

Definition at line 54 of file setup.h.

◆ MUX_HPM_SEL_MASK

#define MUX_HPM_SEL_MASK   (1 << 20)

Definition at line 320 of file setup.h.

◆ MUX_MCLK_CDREX_SEL

#define MUX_MCLK_CDREX_SEL   (1 << 4)

Definition at line 307 of file setup.h.

◆ MUX_MCLK_DPHY_SEL

#define MUX_MCLK_DPHY_SEL   (1 << 8)

Definition at line 308 of file setup.h.

◆ MUX_MPLL_FOUT_SEL

#define MUX_MPLL_FOUT_SEL   (1 << 4)

Definition at line 311 of file setup.h.

◆ MUX_MPLL_SEL_MASK

#define MUX_MPLL_SEL_MASK   (1 << 8)

Definition at line 313 of file setup.h.

◆ MUX_MPLL_USER_SEL

#define MUX_MPLL_USER_SEL   0x0

Definition at line 230 of file setup.h.

◆ MUX_VPLL_SEL

#define MUX_VPLL_SEL   0x1

Definition at line 231 of file setup.h.

◆ MUX_VPLL_SEL_MASK

#define MUX_VPLL_SEL_MASK   (1 << 16)

Definition at line 317 of file setup.h.

◆ P0_CMD_EN

#define P0_CMD_EN   (1 << 14)

Definition at line 615 of file setup.h.

◆ PCLK_CDREX_RATIO

#define PCLK_CDREX_RATIO   0x1

Definition at line 187 of file setup.h.

◆ PHY_CON0_RESET_VAL

#define PHY_CON0_RESET_VAL   0x17020a40

Definition at line 614 of file setup.h.

◆ PHY_CON16_RESET_VAL

#define PHY_CON16_RESET_VAL   0x08000304

Definition at line 627 of file setup.h.

◆ PHY_CON1_RESET_VAL

#define PHY_CON1_RESET_VAL   0x09210100

Definition at line 619 of file setup.h.

◆ PHY_CON2_RESET_VAL

#define PHY_CON2_RESET_VAL   0x00010004

Definition at line 622 of file setup.h.

◆ PHY_CON42_CTRL_BSTLEN_SHIFT

#define PHY_CON42_CTRL_BSTLEN_SHIFT   8

Definition at line 658 of file setup.h.

◆ PHY_CON42_CTRL_RDLAT_SHIFT

#define PHY_CON42_CTRL_RDLAT_SHIFT   0

Definition at line 659 of file setup.h.

◆ PHY_CONTROL0_RESET_VAL

#define PHY_CONTROL0_RESET_VAL   0x0

Definition at line 644 of file setup.h.

◆ PHY_TERM_EN

#define PHY_TERM_EN   (1 << 30) /* Termination enable for PHY */

Definition at line 646 of file setup.h.

◆ PWM_SEL

#define PWM_SEL   6

Definition at line 333 of file setup.h.

◆ R0SIZE

#define R0SIZE   0x0

Definition at line 603 of file setup.h.

◆ RDLVL_COMPLETE_CH1

#define RDLVL_COMPLETE_CH1   (1 << 15)

Definition at line 119 of file setup.h.

◆ RDLVL_COMPLETE_CHO

#define RDLVL_COMPLETE_CHO   (1 << 14)

Definition at line 118 of file setup.h.

◆ RDLVL_GATE_EN

#define RDLVL_GATE_EN   (1 << 24)

Definition at line 624 of file setup.h.

◆ SCLK_DIV_ISP_VAL

#define SCLK_DIV_ISP_VAL
Value:
(SPI1_ISP_RATIO << 12) \
| (SPI0_ISP_RATIO << 0)
SPI1_ISP_RATIO
#define SPI1_ISP_RATIO
Definition: setup.h:362
SPI0_ISP_RATIO
#define SPI0_ISP_RATIO
Definition: setup.h:361

Definition at line 363 of file setup.h.

◆ SCLK_MPWM_ISP_MASK

#define SCLK_MPWM_ISP_MASK   (1 << 0)

Definition at line 516 of file setup.h.

◆ SCLK_SRC_ISP_VAL

#define SCLK_SRC_ISP_VAL
Value:
(SPI1_ISP_SEL << 4) \
| (SPI0_ISP_SEL << 0)
SPI1_ISP_SEL
#define SPI1_ISP_SEL
Definition: setup.h:356
SPI0_ISP_SEL
#define SPI0_ISP_SEL
Definition: setup.h:355

Definition at line 357 of file setup.h.

◆ set_pll

#define set_pll (   mdiv,
  pdiv,
  sdiv 
)    (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)

Definition at line 50 of file setup.h.

◆ SPI0_ISP_RATIO

#define SPI0_ISP_RATIO   0xf

Definition at line 361 of file setup.h.

◆ SPI0_ISP_SEL

#define SPI0_ISP_SEL   6

Definition at line 355 of file setup.h.

◆ SPI0_RATIO

#define SPI0_RATIO   0xf

Definition at line 380 of file setup.h.

◆ SPI0_SEL

#define SPI0_SEL   6

Definition at line 347 of file setup.h.

◆ SPI0_SUB_RATIO

#define SPI0_SUB_RATIO   0x0

Definition at line 382 of file setup.h.

◆ SPI1_ISP_RATIO

#define SPI1_ISP_RATIO   0xf

Definition at line 362 of file setup.h.

◆ SPI1_ISP_SEL

#define SPI1_ISP_SEL   6

Definition at line 356 of file setup.h.

◆ SPI1_RATIO

#define SPI1_RATIO   0x7

Definition at line 379 of file setup.h.

◆ SPI1_SEL

#define SPI1_SEL   6

Definition at line 348 of file setup.h.

◆ SPI1_SUB_RATIO

#define SPI1_SUB_RATIO   0x0

Definition at line 381 of file setup.h.

◆ SPI2_RATIO

#define SPI2_RATIO   0xf

Definition at line 389 of file setup.h.

◆ SPI2_SEL

#define SPI2_SEL   6

Definition at line 349 of file setup.h.

◆ SPI2_SUB_RATIO

#define SPI2_SUB_RATIO   0x0

Definition at line 390 of file setup.h.

◆ TOP2_VAL

#define TOP2_VAL   0x0110000

Definition at line 330 of file setup.h.

◆ TZPC0_BASE

#define TZPC0_BASE   0x10100000

Definition at line 13 of file setup.h.

◆ TZPC1_BASE

#define TZPC1_BASE   0x10110000

Definition at line 14 of file setup.h.

◆ TZPC2_BASE

#define TZPC2_BASE   0x10120000

Definition at line 15 of file setup.h.

◆ TZPC3_BASE

#define TZPC3_BASE   0x10130000

Definition at line 16 of file setup.h.

◆ TZPC4_BASE

#define TZPC4_BASE   0x10140000

Definition at line 17 of file setup.h.

◆ TZPC5_BASE

#define TZPC5_BASE   0x10150000

Definition at line 18 of file setup.h.

◆ TZPC6_BASE

#define TZPC6_BASE   0x10160000

Definition at line 19 of file setup.h.

◆ TZPC7_BASE

#define TZPC7_BASE   0x10170000

Definition at line 20 of file setup.h.

◆ TZPC8_BASE

#define TZPC8_BASE   0x10180000

Definition at line 21 of file setup.h.

◆ TZPC9_BASE

#define TZPC9_BASE   0x10190000

Definition at line 22 of file setup.h.

◆ UART0_RATIO

#define UART0_RATIO   7

Definition at line 372 of file setup.h.

◆ UART0_SEL

#define UART0_SEL   6

Definition at line 337 of file setup.h.

◆ UART1_RATIO

#define UART1_RATIO   7

Definition at line 371 of file setup.h.

◆ UART1_SEL

#define UART1_SEL   6

Definition at line 336 of file setup.h.

◆ UART2_RATIO

#define UART2_RATIO   7

Definition at line 370 of file setup.h.

◆ UART2_SEL

#define UART2_SEL   6

Definition at line 335 of file setup.h.

◆ UART3_RATIO

#define UART3_RATIO   7

Definition at line 369 of file setup.h.

◆ UART3_SEL

#define UART3_SEL   6

Definition at line 334 of file setup.h.

◆ UART4_RATIO

#define UART4_RATIO   7

Definition at line 368 of file setup.h.

◆ UART5_RATIO

#define UART5_RATIO   7

Definition at line 367 of file setup.h.

◆ VPLL_CON0_LOCKED

#define VPLL_CON0_LOCKED   (1 << 29)

Definition at line 328 of file setup.h.

◆ VPLL_CON1_VAL

#define VPLL_CON1_VAL   0x00000000

Definition at line 43 of file setup.h.

◆ VPLL_CON2_VAL

#define VPLL_CON2_VAL   0x00000080

Definition at line 44 of file setup.h.

◆ VPLL_LOCK_VAL

#define VPLL_LOCK_VAL   (0x3A98)

Definition at line 303 of file setup.h.

◆ VPLLSRC_SEL

#define VPLLSRC_SEL   0x0

Definition at line 234 of file setup.h.

◆ ZQ_CLK_DIV_EN

#define ZQ_CLK_DIV_EN   (1 << 18)

Definition at line 629 of file setup.h.

◆ ZQ_DONE

#define ZQ_DONE   (1 << 0)

Definition at line 631 of file setup.h.

◆ ZQ_MANUAL_STR

#define ZQ_MANUAL_STR   (1 << 1)

Definition at line 630 of file setup.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
SETUP_ERR_OK 
SETUP_ERR_RDLV_COMPLETE_TIMEOUT 
SETUP_ERR_ZQ_CALIBRATION_FAILURE 

Definition at line 664 of file setup.h.

Function Documentation

◆ cpu_info_init()

void cpu_info_init ( void  )

◆ ddr3_mem_ctrl_init()

int ddr3_mem_ctrl_init ( struct mem_timings *  mem,
unsigned long  mem_iv_size,
int  mem_reset 
)

Definition at line 25 of file dmc_init_ddr3.c.

References mem_timings::aref_en, BIOS_EMERG, BYTE_RDLVL_EN, CA_ADR_DRVR_DS_OFFSET, CA_CK_DRVR_DS_OFFSET, CA_CKE_DRVR_DS_OFFSET, CA_CS_DRVR_DS_OFFSET, exynos5_dmc::concontrol, mem_timings::concontrol, CONCONTROL_AREF_EN_SHIFT, CONCONTROL_DFI_INIT_START_SHIFT, CONCONTROL_RD_FETCH_SHIFT, mem_timings::ctrl_bstlen, mem_timings::ctrl_dll_on, mem_timings::ctrl_force, CTRL_GATEDURADJ_MASK, mem_timings::ctrl_inc, mem_timings::ctrl_rdlat, CTRL_RDLVL_GATE_DISABLE, CTRL_RDLVL_GATE_ENABLE, mem_timings::ctrl_ref, CTRL_SHGATE, mem_timings::ctrl_start, mem_timings::ctrl_start_point, DDR_MODE_DDR3, mem_timings::dfi_init_start, dmc_config_mrs(), dmc_config_prech(), dmc_config_zq(), DMC_MEMCONTROL_DSREF_ENABLE, mem_timings::dpwrdn_cyc, mem_timings::dsref_cyc, exynos_dmc, exynos_phy0_control, exynos_phy1_control, mem_timings::gate_leveling_enable, mem_timings::impedance, INIT_DESKEW_EN, mem_timings::iv_size, exynos5_dmc::ivcontrol, exynos5_dmc::membaseconfig0, mem_timings::membaseconfig0, exynos5_dmc::membaseconfig1, mem_timings::membaseconfig1, mem_timings::memconfig, exynos5_dmc::memconfig0, exynos5_dmc::memconfig1, exynos5_dmc::memcontrol, mem_timings::memcontrol, P0_CMD_EN, mem_timings::phy0_dq, mem_timings::phy0_dqs, mem_timings::phy0_pulld_dqs, mem_timings::phy0_tFS, mem_timings::phy1_dq, mem_timings::phy1_dqs, mem_timings::phy1_pulld_dqs, mem_timings::phy1_tFS, exynos5_phy_control::phy_con0, PHY_CON0_RESET_VAL, exynos5_phy_control::phy_con1, exynos5_phy_control::phy_con10, exynos5_phy_control::phy_con12, PHY_CON12_CTRL_DLL_ON_SHIFT, PHY_CON12_CTRL_FORCE_SHIFT, PHY_CON12_CTRL_INC_SHIFT, PHY_CON12_CTRL_REF_SHIFT, PHY_CON12_CTRL_START_POINT_SHIFT, PHY_CON12_CTRL_START_SHIFT, exynos5_phy_control::phy_con14, PHY_CON1_RESET_VAL, exynos5_phy_control::phy_con2, PHY_CON2_RESET_VAL, exynos5_phy_control::phy_con39, exynos5_phy_control::phy_con4, exynos5_phy_control::phy_con42, PHY_CON42_CTRL_BSTLEN_SHIFT, PHY_CON42_CTRL_RDLAT_SHIFT, exynos5_phy_control::phy_con6, exynos5_dmc::phystatus, exynos5_dmc::prechconfig, mem_timings::prechconfig_tp_cnt, PRECHCONFIG_TP_CNT_SHIFT, printk, exynos5_dmc::pwrdnconfig, PWRDNCONFIG_DPWRDN_CYC_SHIFT, PWRDNCONFIG_DSREF_CYC_SHIFT, mem_timings::rd_fetch, RDLVL_COMPLETE_CH1, RDLVL_COMPLETE_CHO, RDLVL_COMPLETE_TIMEOUT, exynos5_dmc::rdlvl_config, RDLVL_GATE_EN, read32(), reset_phy_ctrl(), SETUP_ERR_RDLV_COMPLETE_TIMEOUT, SETUP_ERR_ZQ_CALIBRATION_FAILURE, mem_timings::timing_data, mem_timings::timing_power, mem_timings::timing_ref, mem_timings::timing_row, exynos5_dmc::timingdata, exynos5_dmc::timingpower, exynos5_dmc::timingref, exynos5_dmc::timingrow, udelay(), update_reset_dll(), val, and write32().

Referenced by setup_memory().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ dmc_config_memory()

void dmc_config_memory ( struct mem_timings *  mem,
struct exynos5_dmc *  dmc 
)

Definition at line 157 of file dmc_common.c.

◆ dmc_config_mrs()

void dmc_config_mrs ( struct mem_timings *  mem,
struct exynos5_dmc *  dmc 
)

Definition at line 92 of file dmc_common.c.

◆ dmc_config_prech()

void dmc_config_prech ( struct mem_timings *  mem,
struct exynos5_dmc *  dmc 
)

Definition at line 139 of file dmc_common.c.

◆ dmc_config_zq()

int dmc_config_zq ( struct mem_timings *  mem,
struct exynos5_phy_control *  phy0_ctrl,
struct exynos5_phy_control *  phy1_ctrl 
)

Definition at line 14 of file dmc_common.c.

◆ mem_ctrl_init()

void mem_ctrl_init ( void  )

◆ update_reset_dll()

void update_reset_dll ( struct exynos5_dmc *  dmc,
enum  ddr_mode 
)

Definition at line 72 of file dmc_common.c.