coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Data Structures | Macros | Enumerations | Functions | Variables
dmc.h File Reference
#include <soc/cpu.h>
Include dependency graph for dmc.h:

Go to the source code of this file.

Data Structures

struct  exynos5_dmc
 
struct  exynos5_phy_control
 
struct  mem_timings
 

Macros

#define DMC_INTERLEAVE_SIZE   0x1f
 
#define CONCONTROL_DFI_INIT_START_SHIFT   28
 
#define CONCONTROL_RD_FETCH_SHIFT   12
 
#define CONCONTROL_RD_FETCH_MASK   (0x7 << CONCONTROL_RD_FETCH_SHIFT)
 
#define CONCONTROL_AREF_EN_SHIFT   5
 
#define PRECHCONFIG_TP_CNT_SHIFT   24
 
#define PWRDNCONFIG_DPWRDN_CYC_SHIFT   0
 
#define PWRDNCONFIG_DSREF_CYC_SHIFT   16
 
#define PHY_CON0_T_WRRDCMD_SHIFT   17
 
#define PHY_CON0_T_WRRDCMD_MASK   (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
 
#define PHY_CON0_CTRL_DDR_MODE_SHIFT   11
 
#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT   0
 
#define PHY_CON12_CTRL_START_POINT_SHIFT   24
 
#define PHY_CON12_CTRL_INC_SHIFT   16
 
#define PHY_CON12_CTRL_FORCE_SHIFT   8
 
#define PHY_CON12_CTRL_START_SHIFT   6
 
#define PHY_CON12_CTRL_START_MASK   (1 << PHY_CON12_CTRL_START_SHIFT)
 
#define PHY_CON12_CTRL_DLL_ON_SHIFT   5
 
#define PHY_CON12_CTRL_DLL_ON_MASK   (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
 
#define PHY_CON12_CTRL_REF_SHIFT   1
 
#define PHY_CON16_ZQ_MODE_DDS_SHIFT   24
 
#define PHY_CON16_ZQ_MODE_DDS_MASK   (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
 
#define PHY_CON16_ZQ_MODE_TERM_SHIFT   21
 
#define PHY_CON16_ZQ_MODE_TERM_MASK   (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
 
#define PHY_CON16_ZQ_MODE_NOTERM_MASK   (1 << 19)
 
#define PHY_CON42_CTRL_BSTLEN_SHIFT   8
 
#define PHY_CON42_CTRL_BSTLEN_MASK   (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
 
#define PHY_CON42_CTRL_RDLAT_SHIFT   0
 
#define PHY_CON42_CTRL_RDLAT_MASK   (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
 

Enumerations

enum  ddr_mode {
  DDR_MODE_DDR2 , DDR_MODE_DDR3 , DDR_MODE_LPDDR2 , DDR_MODE_LPDDR3 ,
  DDR_MODE_COUNT , DDR_MODE_DDR2 = 0x0 , DDR_MODE_DDR3 = 0x1 , DDR_MODE_LPDDR2 = 0x2 ,
  DDR_MODE_LPDDR3 = 0x3 , DDR_MODE_COUNT
}
 
enum  mem_manuf {
  MEM_MANUF_AUTODETECT , MEM_MANUF_ELPIDA = 0xe7b1da , MEM_MANUF_SAMSUNG = 0x5a5096 , MEM_MANUF_COUNT = 2 ,
  MEM_MANUF_AUTODETECT , MEM_MANUF_ELPIDA = 0xe7b1da , MEM_MANUF_SAMSUNG = 0x5a5096 , MEM_MANUF_COUNT = 2
}
 
enum  { MEM_TIMINGS_MSR_COUNT = 4 }
 

Functions

 check_member (exynos5_dmc, pmcnt3_ppc_a, 0xe140)
 
 check_member (exynos5_phy_control, phy_con42, 0xac)
 
struct mem_timings * get_mem_timings (void)
 Get the correct memory timings for our selected memory type and speed. More...
 

Variables

static struct exynos5_dmc *const exynos_dmc = (void *)EXYNOS5_DMC_CTRL_BASE
 
static struct exynos5_phy_control *const exynos_phy0_control
 
static struct exynos5_phy_control *const exynos_phy1_control
 

Macro Definition Documentation

◆ CONCONTROL_AREF_EN_SHIFT

#define CONCONTROL_AREF_EN_SHIFT   5

Definition at line 202 of file dmc.h.

◆ CONCONTROL_DFI_INIT_START_SHIFT

#define CONCONTROL_DFI_INIT_START_SHIFT   28

Definition at line 199 of file dmc.h.

◆ CONCONTROL_RD_FETCH_MASK

#define CONCONTROL_RD_FETCH_MASK   (0x7 << CONCONTROL_RD_FETCH_SHIFT)

Definition at line 201 of file dmc.h.

◆ CONCONTROL_RD_FETCH_SHIFT

#define CONCONTROL_RD_FETCH_SHIFT   12

Definition at line 200 of file dmc.h.

◆ DMC_INTERLEAVE_SIZE

#define DMC_INTERLEAVE_SIZE   0x1f

Definition at line 196 of file dmc.h.

◆ PHY_CON0_CTRL_DDR_MODE_SHIFT

#define PHY_CON0_CTRL_DDR_MODE_SHIFT   11

Definition at line 214 of file dmc.h.

◆ PHY_CON0_T_WRRDCMD_MASK

#define PHY_CON0_T_WRRDCMD_MASK   (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)

Definition at line 213 of file dmc.h.

◆ PHY_CON0_T_WRRDCMD_SHIFT

#define PHY_CON0_T_WRRDCMD_SHIFT   17

Definition at line 212 of file dmc.h.

◆ PHY_CON12_CTRL_DLL_ON_MASK

#define PHY_CON12_CTRL_DLL_ON_MASK   (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)

Definition at line 226 of file dmc.h.

◆ PHY_CON12_CTRL_DLL_ON_SHIFT

#define PHY_CON12_CTRL_DLL_ON_SHIFT   5

Definition at line 225 of file dmc.h.

◆ PHY_CON12_CTRL_FORCE_SHIFT

#define PHY_CON12_CTRL_FORCE_SHIFT   8

Definition at line 222 of file dmc.h.

◆ PHY_CON12_CTRL_INC_SHIFT

#define PHY_CON12_CTRL_INC_SHIFT   16

Definition at line 221 of file dmc.h.

◆ PHY_CON12_CTRL_REF_SHIFT

#define PHY_CON12_CTRL_REF_SHIFT   1

Definition at line 227 of file dmc.h.

◆ PHY_CON12_CTRL_START_MASK

#define PHY_CON12_CTRL_START_MASK   (1 << PHY_CON12_CTRL_START_SHIFT)

Definition at line 224 of file dmc.h.

◆ PHY_CON12_CTRL_START_POINT_SHIFT

#define PHY_CON12_CTRL_START_POINT_SHIFT   24

Definition at line 220 of file dmc.h.

◆ PHY_CON12_CTRL_START_SHIFT

#define PHY_CON12_CTRL_START_SHIFT   6

Definition at line 223 of file dmc.h.

◆ PHY_CON16_ZQ_MODE_DDS_MASK

#define PHY_CON16_ZQ_MODE_DDS_MASK   (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)

Definition at line 231 of file dmc.h.

◆ PHY_CON16_ZQ_MODE_DDS_SHIFT

#define PHY_CON16_ZQ_MODE_DDS_SHIFT   24

Definition at line 230 of file dmc.h.

◆ PHY_CON16_ZQ_MODE_NOTERM_MASK

#define PHY_CON16_ZQ_MODE_NOTERM_MASK   (1 << 19)

Definition at line 236 of file dmc.h.

◆ PHY_CON16_ZQ_MODE_TERM_MASK

#define PHY_CON16_ZQ_MODE_TERM_MASK   (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)

Definition at line 234 of file dmc.h.

◆ PHY_CON16_ZQ_MODE_TERM_SHIFT

#define PHY_CON16_ZQ_MODE_TERM_SHIFT   21

Definition at line 233 of file dmc.h.

◆ PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT

#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT   0

Definition at line 217 of file dmc.h.

◆ PHY_CON42_CTRL_BSTLEN_MASK

#define PHY_CON42_CTRL_BSTLEN_MASK   (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)

Definition at line 240 of file dmc.h.

◆ PHY_CON42_CTRL_BSTLEN_SHIFT

#define PHY_CON42_CTRL_BSTLEN_SHIFT   8

Definition at line 239 of file dmc.h.

◆ PHY_CON42_CTRL_RDLAT_MASK

#define PHY_CON42_CTRL_RDLAT_MASK   (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)

Definition at line 243 of file dmc.h.

◆ PHY_CON42_CTRL_RDLAT_SHIFT

#define PHY_CON42_CTRL_RDLAT_SHIFT   0

Definition at line 242 of file dmc.h.

◆ PRECHCONFIG_TP_CNT_SHIFT

#define PRECHCONFIG_TP_CNT_SHIFT   24

Definition at line 205 of file dmc.h.

◆ PWRDNCONFIG_DPWRDN_CYC_SHIFT

#define PWRDNCONFIG_DPWRDN_CYC_SHIFT   0

Definition at line 208 of file dmc.h.

◆ PWRDNCONFIG_DSREF_CYC_SHIFT

#define PWRDNCONFIG_DSREF_CYC_SHIFT   16

Definition at line 209 of file dmc.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
MEM_TIMINGS_MSR_COUNT 

Definition at line 192 of file dmc.h.

◆ ddr_mode

enum ddr_mode
Enumerator
DDR_MODE_DDR2 
DDR_MODE_DDR3 
DDR_MODE_LPDDR2 
DDR_MODE_LPDDR3 
DDR_MODE_COUNT 
DDR_MODE_DDR2 
DDR_MODE_DDR3 
DDR_MODE_LPDDR2 
DDR_MODE_LPDDR3 
DDR_MODE_COUNT 

Definition at line 160 of file dmc.h.

◆ mem_manuf

enum mem_manuf
Enumerator
MEM_MANUF_AUTODETECT 
MEM_MANUF_ELPIDA 
MEM_MANUF_SAMSUNG 
MEM_MANUF_COUNT 
MEM_MANUF_AUTODETECT 
MEM_MANUF_ELPIDA 
MEM_MANUF_SAMSUNG 
MEM_MANUF_COUNT 

Definition at line 184 of file dmc.h.

Function Documentation

◆ check_member() [1/2]

check_member ( exynos5_dmc  ,
pmcnt3_ppc_a  ,
0xe140   
)

◆ check_member() [2/2]

check_member ( exynos5_phy_control  ,
phy_con42  ,
0xac   
)

◆ get_mem_timings()

struct mem_timings* get_mem_timings ( void  )

Get the correct memory timings for our selected memory type and speed.

Returns
pointer to the memory timings that we should use

Definition at line 483 of file memory.c.

Variable Documentation

◆ exynos_dmc

struct exynos5_dmc* const exynos_dmc = (void *)EXYNOS5_DMC_CTRL_BASE
static

Definition at line 105 of file dmc.h.

Referenced by ddr3_mem_ctrl_init().

◆ exynos_phy0_control

struct exynos5_phy_control* const exynos_phy0_control
static
Initial value:
=
(void *)EXYNOS5_DMC_PHY0_BASE
EXYNOS5_DMC_PHY0_BASE
#define EXYNOS5_DMC_PHY0_BASE
Definition: cpu.h:19

Definition at line 155 of file dmc.h.

Referenced by ddr3_mem_ctrl_init().

◆ exynos_phy1_control

struct exynos5_phy_control* const exynos_phy1_control
static
Initial value:
=
(void *)EXYNOS5_DMC_PHY1_BASE
EXYNOS5_DMC_PHY1_BASE
#define EXYNOS5_DMC_PHY1_BASE
Definition: cpu.h:20

Definition at line 157 of file dmc.h.

Referenced by ddr3_mem_ctrl_init().