clock_common.h File Reference

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Data Structures
struct	clock_rcg
struct	clock_rcg_mnd
struct	clock_rcg_dfsr
struct	clock_freq_config
struct	qupv3_clock
struct	alpha_pll_reg_val_config
struct	aoss
struct	shrm

Macros
#define	QCOM_CLOCK_DIV(div)   (2 * div - 1)
#define	GDSC_ENABLE_BIT   0

Enumerations
enum	clk_ctl_gpll_user_ctl {   PLL_PLLOUT_MAIN_SHFT = 0 , PLL_PLLOUT_EVEN_SHFT = 1 , PLL_PLLOUT_ODD_SHFT = 2 , PLL_POST_DIV_EVEN_SHFT = 8 ,   PLL_POST_DIV_ODD_SHFT = 12 , PLL_PLLOUT_EVEN_BMSK = 0x2 , CLK_CTL_GPLL_PLLOUT_LV_EARLY_BMSK = 0x8 , CLK_CTL_GPLL_PLLOUT_AUX2_BMSK = 0x4 ,   CLK_CTL_GPLL_PLLOUT_AUX_BMSK = 0x2 , CLK_CTL_GPLL_PLLOUT_MAIN_BMSK = 0x1 , CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT = 3 , CLK_CTL_GPLL_PLLOUT_AUX2_SHFT = 2 ,   CLK_CTL_GPLL_PLLOUT_AUX_SHFT = 1 , CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0 }
enum	gpll_mode {   PLL_LOCK_DET_BMSK = 0x80000000 , PLL_BYPASSNL_BMSK = 0x2 , PLL_OUTCTRL_BMSK = 0x1 , PLL_USERCTL_BMSK = 0xF ,   PLL_STANDBY_MODE = 0 , PLL_RUN_MODE = 1 , PLL_OPMODE_SHFT = 0 , PLL_OUTCTRL_SHFT = 0 ,   PLL_BYPASSNL_SHFT = 1 , PLL_RESET_SHFT = 2 , PLL_RESET_N_SHFT = 2 , PLL_FSM_EN_SHFT = 20 }
enum	clk_ctl_cfg_rcgr {   CLK_CTL_CFG_SRC_DIV_SHFT = 0 , CLK_CTL_CFG_SRC_SEL_SHFT = 8 , CLK_CTL_CFG_MODE_SHFT = 12 , CLK_CTL_CFG_MODE_BMSK = 0x3000 ,   CLK_CTL_CFG_MODE_SHFT = 12 , CLK_CTL_CFG_SRC_SEL_BMSK = 0x700 , CLK_CTL_CFG_SRC_SEL_SHFT = 8 , CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F ,   CLK_CTL_CFG_SRC_DIV_SHFT = 0 }
enum	clk_ctl_cmd_rcgr {   CLK_CTL_CMD_UPDATE_SHFT = 0 , CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000 , CLK_CTL_CMD_ROOT_OFF_SHFT = 31 , CLK_CTL_CMD_ROOT_EN_BMSK = 0x2 ,   CLK_CTL_CMD_ROOT_EN_SHFT = 1 , CLK_CTL_CMD_UPDATE_BMSK = 0x1 , CLK_CTL_CMD_UPDATE_SHFT = 0 }
enum	clk_ctl_cbcr {   CLK_CTL_EN_SHFT = 0 , CLK_CTL_OFF_SHFT = 31 , CLK_CTL_EN_BMSK = 0x1 , CLK_CTL_OFF_BMSK = 0x80000000 ,   CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000 , CLK_CTL_CBC_CLK_OFF_SHFT = 31 , CLK_CTL_CBC_CLK_EN_BMSK = 0x1 , CLK_CTL_CBC_CLK_EN_SHFT = 0 }
enum	clk_ctl_rcg_mnd {   RCG_MODE_DUAL_EDGE = 2 , CLK_CTL_RCG_MND_SHFT = 0 , CLK_CTL_RCG_MND_BMSK = 0xFFFF , CLK_CTL_RCG_MND_BMSK = 0xFFFF ,   CLK_CTL_RCG_MND_SHFT = 0 }
enum	clk_ctl_bcr { CLK_CTL_BCR_BLK_SHFT = 0 , CLK_CTL_BCR_BLK_BMSK = 0x1 , CLK_CTL_BCR_BLK_ARES_BMSK = 0x1 , CLK_CTL_BCR_BLK_ARES_SHFT = 0 }
enum	clk_ctl_dfsr { CLK_CTL_CMD_DFSR_SHFT = 0 , CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15 , CLK_CTL_CMD_DFSR_BMSK = 0x1 }

Functions
enum cb_err	clock_enable_vote (void *cbcr_addr, void *vote_addr, uint32_t vote_bit)
enum cb_err	clock_enable (void *cbcr_addr)
enum cb_err	enable_and_poll_gdsc_status (void *gdscr_addr)
void	clock_reset_bcr (void *bcr_addr, bool assert)
enum cb_err	clock_configure (struct clock_rcg *clk, struct clock_freq_config *clk_cfg, uint32_t hz, uint32_t num_perfs)
void	clock_configure_dfsr_table (int qup, struct clock_freq_config *clk_cfg, uint32_t num_perfs)
enum cb_err	clock_configure_enable_gpll (struct alpha_pll_reg_val_config *cfg, bool enable, int br_enable)
enum cb_err	agera_pll_enable (struct alpha_pll_reg_val_config *cfg)
enum cb_err	zonda_pll_enable (struct alpha_pll_reg_val_config *cfg)
	check_member (aoss, aoss_cc_reset_status, 0x50020)
	check_member (aoss, aoss_cc_apcs_misc, 0x5002c)
void	clock_reset_subsystem (u32 *misc, u32 shft)

Macro Definition Documentation

GDSC_ENABLE_BIT

#define GDSC_ENABLE_BIT   0

Definition at line 137 of file clock_common.h.

QCOM_CLOCK_DIV

#define QCOM_CLOCK_DIV

(

div

)

(2 * div - 1)

Definition at line 6 of file clock_common.h.

Enumeration Type Documentation

clk_ctl_bcr

enum clk_ctl_bcr

Enumerator
CLK_CTL_BCR_BLK_SHFT
CLK_CTL_BCR_BLK_BMSK
CLK_CTL_BCR_BLK_ARES_BMSK
CLK_CTL_BCR_BLK_ARES_SHFT

Definition at line 126 of file clock_common.h.

clk_ctl_cbcr

enum clk_ctl_cbcr

Enumerator
CLK_CTL_EN_SHFT
CLK_CTL_OFF_SHFT
CLK_CTL_EN_BMSK
CLK_CTL_OFF_BMSK
CLK_CTL_CBC_CLK_OFF_BMSK
CLK_CTL_CBC_CLK_OFF_SHFT
CLK_CTL_CBC_CLK_EN_BMSK
CLK_CTL_CBC_CLK_EN_SHFT

Definition at line 113 of file clock_common.h.

clk_ctl_cfg_rcgr

enum clk_ctl_cfg_rcgr

Enumerator
CLK_CTL_CFG_SRC_DIV_SHFT
CLK_CTL_CFG_SRC_SEL_SHFT
CLK_CTL_CFG_MODE_SHFT
CLK_CTL_CFG_MODE_BMSK
CLK_CTL_CFG_MODE_SHFT
CLK_CTL_CFG_SRC_SEL_BMSK
CLK_CTL_CFG_SRC_SEL_SHFT
CLK_CTL_CFG_SRC_DIV_BMSK
CLK_CTL_CFG_SRC_DIV_SHFT

Definition at line 103 of file clock_common.h.

clk_ctl_cmd_rcgr

enum clk_ctl_cmd_rcgr

Enumerator
CLK_CTL_CMD_UPDATE_SHFT
CLK_CTL_CMD_ROOT_OFF_BMSK
CLK_CTL_CMD_ROOT_OFF_SHFT
CLK_CTL_CMD_ROOT_EN_BMSK
CLK_CTL_CMD_ROOT_EN_SHFT
CLK_CTL_CMD_UPDATE_BMSK
CLK_CTL_CMD_UPDATE_SHFT

Definition at line 109 of file clock_common.h.

clk_ctl_dfsr

enum clk_ctl_dfsr

Enumerator
CLK_CTL_CMD_DFSR_SHFT
CLK_CTL_CMD_RCG_SW_CTL_SHFT
CLK_CTL_CMD_DFSR_BMSK

Definition at line 131 of file clock_common.h.

clk_ctl_gpll_user_ctl

enum clk_ctl_gpll_user_ctl

Enumerator
PLL_PLLOUT_MAIN_SHFT
PLL_PLLOUT_EVEN_SHFT
PLL_PLLOUT_ODD_SHFT
PLL_POST_DIV_EVEN_SHFT
PLL_POST_DIV_ODD_SHFT
PLL_PLLOUT_EVEN_BMSK
CLK_CTL_GPLL_PLLOUT_LV_EARLY_BMSK
CLK_CTL_GPLL_PLLOUT_AUX2_BMSK
CLK_CTL_GPLL_PLLOUT_AUX_BMSK
CLK_CTL_GPLL_PLLOUT_MAIN_BMSK
CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT
CLK_CTL_GPLL_PLLOUT_AUX2_SHFT
CLK_CTL_GPLL_PLLOUT_AUX_SHFT
CLK_CTL_GPLL_PLLOUT_MAIN_SHFT

Definition at line 79 of file clock_common.h.

clk_ctl_rcg_mnd

enum clk_ctl_rcg_mnd

Enumerator
RCG_MODE_DUAL_EDGE
CLK_CTL_RCG_MND_SHFT
CLK_CTL_RCG_MND_BMSK
CLK_CTL_RCG_MND_BMSK
CLK_CTL_RCG_MND_SHFT

Definition at line 120 of file clock_common.h.

gpll_mode

enum gpll_mode

Enumerator
PLL_LOCK_DET_BMSK
PLL_BYPASSNL_BMSK
PLL_OUTCTRL_BMSK
PLL_USERCTL_BMSK
PLL_STANDBY_MODE
PLL_RUN_MODE
PLL_OPMODE_SHFT
PLL_OUTCTRL_SHFT
PLL_BYPASSNL_SHFT
PLL_RESET_SHFT
PLL_RESET_N_SHFT
PLL_FSM_EN_SHFT

Definition at line 88 of file clock_common.h.

Function Documentation

agera_pll_enable()

enum cb_err agera_pll_enable

(

struct alpha_pll_reg_val_config *

cfg

)

Definition at line 124 of file clock.c.

References BIT, CLK_CTL_CFG_MODE_SHFT, CLK_CTL_CFG_SRC_DIV_SHFT, CLK_CTL_CFG_SRC_SEL_SHFT, CLK_CTL_CMD_DFSR_SHFT, CLK_CTL_CMD_RCG_SW_CTL_SHFT, CLK_CTL_RCG_MND_BMSK, clrsetbits32, clock_rcg_dfsr::cmd_dfsr, clock_freq_config::d_2, qupv3_clock::dfsr_clk, gcc, m, clock_freq_config::m, clock_freq_config::n, clock_rcg_dfsr::perf_d_dfsr, clock_rcg_dfsr::perf_dfsr, clock_rcg_dfsr::perf_m_dfsr, clock_rcg_dfsr::perf_n_dfsr, QUP_WRAP1_S0, RCG_MODE_DUAL_EDGE, s, setbits32, clock_freq_config::src, and write32().

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check_member() [1/2]

check_member	(	aoss	,
		aoss_cc_apcs_misc	,
		0x5002c
	)

check_member() [2/2]

check_member	(	aoss	,
		aoss_cc_reset_status	,
		0x50020
	)

clock_configure()

enum cb_err clock_configure	(	struct clock_rcg *	clk,
		struct clock_freq_config *	clk_cfg,
		uint32_t	hz,
		uint32_t	num_perfs
	)

Definition at line 78 of file clock.c.

References CLK_CTL_CFG_MODE_SHFT, CLK_CTL_RCG_MND_BMSK, clock_rcg_mnd::d_2, m, clock_rcg_mnd::m, clock_rcg_mnd::n, clock_rcg::rcg_cfg, RCG_MODE_DUAL_EDGE, setbits32, and write32().

Referenced by clock_configure_i2c(), clock_configure_qspi(), clock_configure_sdcc1(), clock_configure_sdcc2(), clock_configure_spi(), and clock_configure_uart().

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clock_configure_dfsr_table()

void clock_configure_dfsr_table	(	int	qup,
		struct clock_freq_config *	clk_cfg,
		uint32_t	num_perfs
	)

Definition at line 124 of file clock.c.

Referenced by clock_configure_dfsr().

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clock_configure_enable_gpll()

enum cb_err clock_configure_enable_gpll	(	struct alpha_pll_reg_val_config *	cfg,
		bool	enable,
		int	br_enable
	)

Definition at line 124 of file clock.c.

Referenced by clock_configure_gpll0(), clock_configure_sdcc1(), and clock_configure_sdcc2().

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clock_enable()

enum cb_err clock_enable

(

void *

cbcr_addr

)

Definition at line 12 of file clock.c.

References CLK_CTL_OFF_BMSK, and read32().

Referenced by clock_configure_qspi(), clock_configure_sdcc1(), clock_configure_sdcc2(), clock_disable_spi(), clock_enable_clear_reset(), clock_enable_i2c(), clock_enable_spi(), clock_enable_uart(), and mdss_clock_enable().

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clock_enable_vote()

enum cb_err clock_enable_vote	(	void *	cbcr_addr,
		void *	vote_addr,
		uint32_t	vote_bit
	)

Definition at line 12 of file clock.c.

Referenced by clock_enable_qup(), and clock_init().

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clock_reset_bcr()

void clock_reset_bcr	(	void *	bcr_addr,
		bool	assert
	)

Definition at line 54 of file clock.c.

clock_reset_subsystem()

void clock_reset_subsystem	(	u32 *	misc,
		u32	shft
	)

Definition at line 268 of file clock.c.

References BIT, clrbits32, and misc.

enable_and_poll_gdsc_status()

enum cb_err enable_and_poll_gdsc_status

(

void *

gdscr_addr

)

Definition at line 54 of file clock.c.

zonda_pll_enable()

enum cb_err zonda_pll_enable

(

struct alpha_pll_reg_val_config *

cfg

)

Definition at line 124 of file clock.c.