7 #include <soc/addressmap.h>
8 #include <soc/clk_rst.h>
13 #include <soc/maincpu.h>
15 #include <soc/sysctr.h>
50 .n_shift = 8, .m_shift = 0, .p_shift = 20,
51 .kcp_shift = 1, .kvco_shift = 0, },
56 .n_shift = 10, .m_shift = 0, .p_shift = 20, },
63 .n_shift = 8, .m_shift = 0, .p_shift = 16,
64 .kcp_shift = 25, .kvco_shift = 24, },
71 .n_shift = 8, .m_shift = 0, .p_shift = 19,
72 .kcp_shift = 25, .kvco_shift = 24, },
79 .n_shift = 11, .m_shift = 0, .p_shift = 20,
80 .kcp_shift = 23, .kvco_shift = 22, },
92 #define PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco) \
93 {.n = _n, .m = _m, .p = _p, .kcp = _kcp, .kvco = _kvco,}
94 #define PLL_NO_KCP_KVCO(_n, _m, _p) \
95 {.n = _n, .m = _m, .p = _p,}
97 #define PLLX(_n, _m, _p, _kcp, _kvco) \
98 [PLLX_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)
99 #define PLLC(_n, _m, _p) \
100 [PLLC_INDEX] = PLL_NO_KCP_KVCO(_n, _m, _p)
101 #define PLLU(_n, _m, _p, _kcp, _kvco) \
102 [PLLU_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)
103 #define PLLDP(_n, _m, _p, _kcp, _kvco) \
104 [PLLDP_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)
105 #define PLLD(_n, _m, _p, _kcp, _kvco) \
106 [PLLD_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)
139 PLLU(40, 1, 1, 0, 0),
140 PLLDP(90, 1, 2, 0, 0),
148 PLLU(74, 2, 1, 0, 0),
149 PLLDP(83, 1, 3, 0, 0),
157 PLLU(115, 4, 1, 0, 0),
158 PLLDP(64, 1, 2, 0, 0),
166 PLLU(25, 1, 1, 0, 0),
167 PLLDP(56, 1, 2, 0, 0),
175 PLLU(37, 2, 1, 0, 0),
176 PLLDP(83, 2, 2, 0, 0),
184 PLLU(25, 2, 1, 0, 0),
185 PLLDP(56, 2, 2, 0, 0),
193 PLLU(40, 4, 1, 0, 0),
194 PLLDP(90, 2, 3, 0, 0),
218 return osc_table[osc_bits].khz >> pll_ref_div;
233 #define SOR0_CLK_SEL0 (1 << 14)
234 #define SOR0_CLK_SEL1 (1 << 15)
370 u32 scfg = (1<<28) | (1<<24) | (1<<22);
374 scfg = (1<<28) | (1<<24);
402 u32 cf, vco, rounded_rate = frequency;
404 const u32 max_m = 1 << 8, max_n = 1 << 8, max_p = 1 << 3,
405 mhz = 1000 * 1000, min_vco = 500 *
mhz, max_vco = 1000 *
mhz,
406 min_cf = 1 *
mhz, max_cf = 6 *
mhz;
411 for (vco = frequency; vco < min_vco &&
p < max_p;
p++)
414 if (vco < min_vco || vco > max_vco) {
416 " for Frequency (%u).\n", __func__, frequency);
423 for (
m = 1;
m < max_m && best_diff;
m++) {
435 if (
n + 1 < max_n && diff > cf / 2) {
440 if (diff >= best_diff)
450 "best difference is %u.\n", __func__, frequency,
452 rounded_rate = (ref / plld->
m * plld->
n) >> plld->
p;
456 __func__, rounded_rate, ref, plld->
m, plld->
n, plld->
p);
465 if (rounded_rate != frequency)
513 u32 stable_time,
u32 emc_source,
u32 same_freq)
635 u32 *rst_dev_clr_reg)
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
#define assert(statement)
#define DIV_ROUND_UP(x, y)
#define printk(level,...)
static enum console_uart_id console_uart_get_id(void)
static void console_uart_clock_enable_clear_reset(void)
static uint32_t console_uart_clk_src_dev_id(void)
static void * console_uart_clk_rst_reg(void)
#define setbits32(addr, set)
#define clrsetbits32(addr, clear, set)
#define clrbits32(addr, clear)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_CRIT
BIOS_CRIT - Recovery unlikely.
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
#define BIOS_WARNING
BIOS_WARNING - Bad configuration.
@ PMC_OSC_EDPD_OVER_XOFS_SHIFT
@ PMC_OSC_EDPD_OVER_XOFS_MASK
int clock_get_pll_input_khz(void)
void clock_external_output(int clk_id)
void clock_halt_avp(void)
void clock_reset_l(u32 bit)
void sor_clock_stop(void)
int clock_get_osc_khz(void)
void clock_early_uart(void)
void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq)
void clock_reset_x(u32 bit)
void sor_clock_start(void)
void clock_reset_u(u32 bit)
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
void clock_reset_v(u32 bit)
void clock_reset_w(u32 bit)
void clock_init_arm_generic_timer(void)
void clock_reset_h(u32 bit)
struct @1216 osc_table[16]
#define IO_STABILIZATION_DELAY
#define CLK_DIVIDER(REF, FREQ)
void clock_enable_audio(void)
static void init_utmip_pll(void)
void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS])
static void clock_reset_dev(u32 *setaddr, u32 *clraddr, u32 bit)
static void init_pllu(u32 osc)
static u32 *const clk_enb_set_arr[DEV_CONFIG_BLOCKS]
static u32 *const rst_dev_clr_arr[DEV_CONFIG_BLOCKS]
void clock_reset_y(u32 bit)
void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS])
static u32 *const rst_dev_set_arr[DEV_CONFIG_BLOCKS]
static void graphics_pll(void)
u32 clock_configure_plld(u32 frequency)
static struct sysctr_regs * sysctr
void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS])
static void clock_write_regs(u32 *const regs[DEV_CONFIG_BLOCKS], u32 bits[DEV_CONFIG_BLOCKS])
#define PLLX(_n, _m, _p, _kcp, _kvco)
static struct tegra_pmc_regs * pmc
#define PLLU(_n, _m, _p, _kcp, _kvco)
static void init_pll(u32 index, u32 osc)
static u32 *const clk_enb_clr_arr[DEV_CONFIG_BLOCKS]
#define PLLDP(_n, _m, _p, _kcp, _kvco)
static u32 clock_get_osc_bits(void)
struct pll_reg_info pll_reg_table[]
static void init_pllc(u32 osc)
struct pll_fields plls[PLL_MAX_INDEX]
void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg, u32 *rst_dev_clr_reg)
static struct flow_ctlr * flow
void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS])
#define clock_clr_reset(l, h, u, v, w, x, y)
#define LOGIC_STABILIZATION_DELAY
#define TEGRA_PLLP_OUT3_KHZ
enum cb_err clock_enable(void *cbcr_addr)
#define PLLPAXS_MISC_LOCK_ENABLE
#define PLLM_MISC2_KCP_SHIFT
#define PLLM_MISC2_KVCO_SHIFT
#define PCLK_DIVISOR_SHIFT
#define PLL_BASE_DIVP_SHIFT
#define CLK_UART_DIV_OVERRIDE
#define HCLK_DIVISOR_SHIFT
#define PLLM_BASE_DIVP_MASK
#define PLL_BASE_DIVM_SHIFT
#define PLLD_MISC_CLK_ENABLE
#define PLLM_MISC1_SETUP_SHIFT
#define SCLK_SYS_STATE_SHIFT
#define PLLCMX_BASE_DIVM_MASK
#define PLLCMX_BASE_DIVN_MASK
#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ
#define OSC_DRIVE_STRENGTH
#define PLLDPD2_MISC_LOCK_ENABLE
#define PLL_OUT_RATIO_SHIFT
#define PLL_BASE_DIVN_SHIFT
#define m(clkreg, src_bits, pmcreg, dst_bits)
#define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERDOWN_DISABLE
#define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERUP_ENABLE
#define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE
#define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERUP_ENABLE
#define UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT
#define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERDOWN_DISABLE
#define CLK_RST_REG(field_)
#define PLLU_MISC_LOCK_ENABLE
#define UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT
#define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERUP_ENABLE
#define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE
#define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERUP_ENABLE
#define UTMIP_CFG1_FORCE_PLL_ACTIVE_POWERDOWN_DISABLE
#define CCLK_BURST_POLICY_VAL
#define TIMERUS_USEC_CFG_19P2_CLK_M
#define UTMIP_CFG1_XTAL_FREQ_COUNT_SHIFT
#define DEV_CONFIG_BLOCKS
#define PLLD_MISC_SDM_DIN
#define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE
#define PLLD_MISC_LOCK_ENABLE
#define UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT
#define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE
#define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERUP_ENABLE