coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Data Structures | Macros | Enumerations | Functions | Variables
clock.h File Reference
#include <soc/addressmap.h>
#include <types.h>
Include dependency graph for clock.h:

Go to the source code of this file.

Data Structures

struct  qcs405_rcg
 
struct  qcs405_clock
 
struct  qcs405_bcr
 
struct  qcs405_gpll
 
struct  qcs405_gcc
 
struct  mdss_clock_config
 
struct  clock_config
 

Macros

#define BLSP1_AHB_CLK_ENA   10
 
#define BLSP2_AHB_CLK_ENA   20
 
#define SRC_XO_19_2MHZ   0
 
#define SRC_GPLL0_MAIN_800MHZ   1
 
#define GCC_USB_HS_PHY_CFG_AHB_BCR   0x180000C
 USB BCR registers. More...
 
#define GCC_USB_HS_BCR   0x1841000
 
#define GCC_USB_30_BCR   0x1839000
 
#define GCC_USB2A_PHY_BCR   0x180000C
 
#define GCC_USB2_HS_PHY_ONLY_BCR   0x1841034
 
#define GCC_QUSB2_PHY_BCR   0x184103C
 

Enumerations

enum  clk_ctl_gpll_user_ctl {
  PLL_PLLOUT_MAIN_SHFT = 0 , PLL_PLLOUT_EVEN_SHFT = 1 , PLL_PLLOUT_ODD_SHFT = 2 , PLL_POST_DIV_EVEN_SHFT = 8 ,
  PLL_POST_DIV_ODD_SHFT = 12 , PLL_PLLOUT_EVEN_BMSK = 0x2 , CLK_CTL_GPLL_PLLOUT_LV_EARLY_BMSK = 0x8 , CLK_CTL_GPLL_PLLOUT_AUX2_BMSK = 0x4 ,
  CLK_CTL_GPLL_PLLOUT_AUX_BMSK = 0x2 , CLK_CTL_GPLL_PLLOUT_MAIN_BMSK = 0x1 , CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT = 3 , CLK_CTL_GPLL_PLLOUT_AUX2_SHFT = 2 ,
  CLK_CTL_GPLL_PLLOUT_AUX_SHFT = 1 , CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0
}
 
enum  clk_ctl_cfg_rcgr {
  CLK_CTL_CFG_SRC_DIV_SHFT = 0 , CLK_CTL_CFG_SRC_SEL_SHFT = 8 , CLK_CTL_CFG_MODE_SHFT = 12 , CLK_CTL_CFG_MODE_BMSK = 0x3000 ,
  CLK_CTL_CFG_MODE_SHFT = 12 , CLK_CTL_CFG_SRC_SEL_BMSK = 0x700 , CLK_CTL_CFG_SRC_SEL_SHFT = 8 , CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F ,
  CLK_CTL_CFG_SRC_DIV_SHFT = 0
}
 
enum  clk_ctl_cmd_rcgr {
  CLK_CTL_CMD_UPDATE_SHFT = 0 , CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000 , CLK_CTL_CMD_ROOT_OFF_SHFT = 31 , CLK_CTL_CMD_ROOT_EN_BMSK = 0x2 ,
  CLK_CTL_CMD_ROOT_EN_SHFT = 1 , CLK_CTL_CMD_UPDATE_BMSK = 0x1 , CLK_CTL_CMD_UPDATE_SHFT = 0
}
 
enum  clk_ctl_cbcr {
  CLK_CTL_EN_SHFT = 0 , CLK_CTL_OFF_SHFT = 31 , CLK_CTL_EN_BMSK = 0x1 , CLK_CTL_OFF_BMSK = 0x80000000 ,
  CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000 , CLK_CTL_CBC_CLK_OFF_SHFT = 31 , CLK_CTL_CBC_CLK_EN_BMSK = 0x1 , CLK_CTL_CBC_CLK_EN_SHFT = 0
}
 
enum  clk_ctl_rcg_mnd {
  RCG_MODE_DUAL_EDGE = 2 , CLK_CTL_RCG_MND_SHFT = 0 , CLK_CTL_RCG_MND_BMSK = 0xFFFF , CLK_CTL_RCG_MND_BMSK = 0xFFFF ,
  CLK_CTL_RCG_MND_SHFT = 0
}
 
enum  clk_ctl_bcr { CLK_CTL_BCR_BLK_SHFT = 0 , CLK_CTL_BCR_BLK_BMSK = 0x1 , CLK_CTL_BCR_BLK_ARES_BMSK = 0x1 , CLK_CTL_BCR_BLK_ARES_SHFT = 0 }
 

Functions

void clock_init (void)
 
void clock_reset_aop (void)
 
int clock_configure_qspi (uint32_t hz)
 
int clock_reset_bcr (void *bcr_addr, bool reset)
 
void clock_configure_uart (uint32_t hz)
 
void clock_configure_i2c (uint32_t hz)
 
void clock_configure_spi (int blsp, int qup, uint32_t hz)
 
void clock_enable_uart (void)
 
void clock_disable_uart (void)
 
void clock_enable_spi (int blsp, int qup)
 
void clock_disable_spi (int blsp, int qup)
 
void clock_enable_i2c (void)
 
void clock_disable_i2c (void)
 

Variables

static struct qcs405_gcc *const gcc = (void *)GCC_BASE
 

Macro Definition Documentation

◆ BLSP1_AHB_CLK_ENA

#define BLSP1_AHB_CLK_ENA   10

Definition at line 8 of file clock.h.

◆ BLSP2_AHB_CLK_ENA

#define BLSP2_AHB_CLK_ENA   20

Definition at line 9 of file clock.h.

◆ GCC_QUSB2_PHY_BCR

#define GCC_QUSB2_PHY_BCR   0x184103C

Definition at line 21 of file clock.h.

◆ GCC_USB2_HS_PHY_ONLY_BCR

#define GCC_USB2_HS_PHY_ONLY_BCR   0x1841034

Definition at line 20 of file clock.h.

◆ GCC_USB2A_PHY_BCR

#define GCC_USB2A_PHY_BCR   0x180000C

Definition at line 19 of file clock.h.

◆ GCC_USB_30_BCR

#define GCC_USB_30_BCR   0x1839000

Definition at line 18 of file clock.h.

◆ GCC_USB_HS_BCR

#define GCC_USB_HS_BCR   0x1841000

Definition at line 17 of file clock.h.

◆ GCC_USB_HS_PHY_CFG_AHB_BCR

#define GCC_USB_HS_PHY_CFG_AHB_BCR   0x180000C

USB BCR registers.

Definition at line 16 of file clock.h.

◆ SRC_GPLL0_MAIN_800MHZ

#define SRC_GPLL0_MAIN_800MHZ   1

Definition at line 11 of file clock.h.

◆ SRC_XO_19_2MHZ

#define SRC_XO_19_2MHZ   0

Definition at line 10 of file clock.h.

Enumeration Type Documentation

◆ clk_ctl_bcr

enum clk_ctl_bcr
Enumerator
CLK_CTL_BCR_BLK_SHFT 
CLK_CTL_BCR_BLK_BMSK 
CLK_CTL_BCR_BLK_ARES_BMSK 
CLK_CTL_BCR_BLK_ARES_SHFT 

Definition at line 150 of file clock.h.

◆ clk_ctl_cbcr

enum clk_ctl_cbcr
Enumerator
CLK_CTL_EN_SHFT 
CLK_CTL_OFF_SHFT 
CLK_CTL_EN_BMSK 
CLK_CTL_OFF_BMSK 
CLK_CTL_CBC_CLK_OFF_BMSK 
CLK_CTL_CBC_CLK_OFF_SHFT 
CLK_CTL_CBC_CLK_EN_BMSK 
CLK_CTL_CBC_CLK_EN_SHFT 

Definition at line 138 of file clock.h.

◆ clk_ctl_cfg_rcgr

enum clk_ctl_cfg_rcgr
Enumerator
CLK_CTL_CFG_SRC_DIV_SHFT 
CLK_CTL_CFG_SRC_SEL_SHFT 
CLK_CTL_CFG_MODE_SHFT 
CLK_CTL_CFG_MODE_BMSK 
CLK_CTL_CFG_MODE_SHFT 
CLK_CTL_CFG_SRC_SEL_BMSK 
CLK_CTL_CFG_SRC_SEL_SHFT 
CLK_CTL_CFG_SRC_DIV_BMSK 
CLK_CTL_CFG_SRC_DIV_SHFT 

Definition at line 120 of file clock.h.

◆ clk_ctl_cmd_rcgr

enum clk_ctl_cmd_rcgr
Enumerator
CLK_CTL_CMD_UPDATE_SHFT 
CLK_CTL_CMD_ROOT_OFF_BMSK 
CLK_CTL_CMD_ROOT_OFF_SHFT 
CLK_CTL_CMD_ROOT_EN_BMSK 
CLK_CTL_CMD_ROOT_EN_SHFT 
CLK_CTL_CMD_UPDATE_BMSK 
CLK_CTL_CMD_UPDATE_SHFT 

Definition at line 129 of file clock.h.

◆ clk_ctl_gpll_user_ctl

enum clk_ctl_gpll_user_ctl
Enumerator
PLL_PLLOUT_MAIN_SHFT 
PLL_PLLOUT_EVEN_SHFT 
PLL_PLLOUT_ODD_SHFT 
PLL_POST_DIV_EVEN_SHFT 
PLL_POST_DIV_ODD_SHFT 
PLL_PLLOUT_EVEN_BMSK 
CLK_CTL_GPLL_PLLOUT_LV_EARLY_BMSK 
CLK_CTL_GPLL_PLLOUT_AUX2_BMSK 
CLK_CTL_GPLL_PLLOUT_AUX_BMSK 
CLK_CTL_GPLL_PLLOUT_MAIN_BMSK 
CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT 
CLK_CTL_GPLL_PLLOUT_AUX2_SHFT 
CLK_CTL_GPLL_PLLOUT_AUX_SHFT 
CLK_CTL_GPLL_PLLOUT_MAIN_SHFT 

Definition at line 109 of file clock.h.

◆ clk_ctl_rcg_mnd

enum clk_ctl_rcg_mnd
Enumerator
RCG_MODE_DUAL_EDGE 
CLK_CTL_RCG_MND_SHFT 
CLK_CTL_RCG_MND_BMSK 
CLK_CTL_RCG_MND_BMSK 
CLK_CTL_RCG_MND_SHFT 

Definition at line 145 of file clock.h.

Function Documentation

◆ clock_configure_i2c()

void clock_configure_i2c ( uint32_t  hz)

Definition at line 238 of file clock.c.

References ARRAY_SIZE, qcs405_gcc::blsp1_qup1_i2c_clk, clock_configure(), gcc, and i2c_cfg.

Referenced by blsp_i2c_init().

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◆ clock_configure_qspi()

int clock_configure_qspi ( uint32_t  hz)

Definition at line 117 of file clock.c.

References ARRAY_SIZE, clock_configure(), clock_enable(), gcc, and qspi_core_cfg.

Referenced by quadspi_init().

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◆ clock_configure_spi()

void clock_configure_spi ( int  blsp,
int  qup,
uint32_t  hz 
)

Definition at line 198 of file clock.c.

References ARRAY_SIZE, BIOS_ERR, qcs405_gcc::blsp1_qup0_spi_clk, qcs405_gcc::blsp1_qup1_spi_clk, qcs405_gcc::blsp1_qup2_spi_clk, qcs405_gcc::blsp1_qup3_spi_clk, qcs405_gcc::blsp1_qup4_spi_clk, qcs405_gcc::blsp2_qup0_spi_clk, clock_configure(), gcc, and printk.

Referenced by spi_ctrlr_setup().

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◆ clock_configure_uart()

void clock_configure_uart ( uint32_t  hz)

Definition at line 190 of file clock.c.

References ARRAY_SIZE, qcs405_gcc::blsp1_uart2_apps_clk, clock_configure(), gcc, and uart_cfg.

Referenced by uart_init().

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◆ clock_disable_i2c()

void clock_disable_i2c ( void  )

Definition at line 314 of file clock.c.

References qcs405_gcc::blsp1_qup1_i2c_apps_cbcr, clock_disable(), and gcc.

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◆ clock_disable_spi()

void clock_disable_spi ( int  blsp,
int  qup 
)

Definition at line 282 of file clock.c.

References BIOS_ERR, qcs405_gcc::blsp1_qup0_spi_apps_cbcr, qcs405_gcc::blsp1_qup1_spi_apps_cbcr, qcs405_gcc::blsp1_qup2_spi_apps_cbcr, qcs405_gcc::blsp1_qup3_spi_apps_cbcr, qcs405_gcc::blsp1_qup4_spi_apps_cbcr, qcs405_gcc::blsp2_qup0_spi_apps_cbcr, clock_enable(), gcc, and printk.

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◆ clock_disable_uart()

void clock_disable_uart ( void  )

Definition at line 251 of file clock.c.

References qcs405_gcc::blsp1_uart2_apps_cbcr, clock_disable(), and gcc.

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◆ clock_enable_i2c()

void clock_enable_i2c ( void  )

Definition at line 309 of file clock.c.

References qcs405_gcc::blsp1_qup1_i2c_apps_cbcr, clock_enable(), and gcc.

Referenced by blsp_i2c_init().

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◆ clock_enable_spi()

void clock_enable_spi ( int  blsp,
int  qup 
)

Definition at line 256 of file clock.c.

References BIOS_ERR, qcs405_gcc::blsp1_qup0_spi_apps_cbcr, qcs405_gcc::blsp1_qup1_spi_apps_cbcr, qcs405_gcc::blsp1_qup2_spi_apps_cbcr, qcs405_gcc::blsp1_qup3_spi_apps_cbcr, qcs405_gcc::blsp1_qup4_spi_apps_cbcr, qcs405_gcc::blsp2_qup0_spi_apps_cbcr, clock_enable(), gcc, and printk.

Referenced by spi_ctrlr_setup().

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◆ clock_enable_uart()

void clock_enable_uart ( void  )

Definition at line 246 of file clock.c.

References qcs405_gcc::blsp1_uart2_apps_cbcr, clock_enable(), and gcc.

Referenced by uart_init().

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◆ clock_init()

void clock_init ( void  )

Definition at line 539 of file clock.c.

◆ clock_reset_aop()

void clock_reset_aop ( void  )

Referenced by aop_fw_load_reset().

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◆ clock_reset_bcr()

int clock_reset_bcr ( void *  bcr_addr,
bool  reset 
)

Definition at line 54 of file clock.c.

References assert, qcs405_bcr::bcr, BIT, CLK_CTL_BCR_BLK_ARES_SHFT, CLK_CTL_BCR_BLK_SHFT, clrbits32, reset(), and setbits32.

Referenced by reset_usb(), and setup_usb_host().

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Variable Documentation

◆ gcc

struct qcs405_gcc* const gcc = (void *)GCC_BASE
static

Definition at line 165 of file clock.h.

Referenced by agera_pll_enable(), clock_configure_gpll0(), clock_configure_i2c(), clock_configure_qspi(), clock_configure_sdcc1(), clock_configure_sdcc2(), clock_configure_spi(), clock_configure_uart(), clock_disable_i2c(), clock_disable_spi(), clock_disable_uart(), clock_enable_i2c(), clock_enable_qup(), clock_enable_spi(), clock_enable_uart(), and clock_init().