Macros
#define	NOT_AVAILABLE 0

#define	DATA_MASK 0xFFFFF

#define	ENABLE_BIT 0x1

#define	DISABLE_BIT 0x0

#define	CA_SWAP_EN (1 << 0)

#define	TZPC0_BASE 0x10100000

#define	TZPC1_BASE 0x10110000

#define	TZPC2_BASE 0x10120000

#define	TZPC3_BASE 0x10130000

#define	TZPC4_BASE 0x10140000

#define	TZPC5_BASE 0x10150000

#define	TZPC6_BASE 0x10160000

#define	TZPC7_BASE 0x10170000

#define	TZPC8_BASE 0x10180000

#define	TZPC9_BASE 0x10190000

#define	APLL_FOUT (1 << 0)

#define	KPLL_FOUT (1 << 0)

#define	CLK_DIV_CPERI1_VAL 0x3f3f0000

#define	APLL_CON1_VAL (0x0020f300)

#define	MPLL_CON1_VAL (0x0020f300)

#define	CPLL_CON1_VAL (0x0020f300)

#define	DPLL_CON1_VAL (0x0020f300)

#define	GPLL_CON1_VAL (NOT_AVAILABLE)

#define	EPLL_CON1_VAL 0x00000000

#define	EPLL_CON2_VAL 0x00000080

#define	VPLL_CON1_VAL 0x0020f300

#define	VPLL_CON2_VAL NOT_AVAILABLE

#define	RPLL_CON1_VAL 0x00000000

#define	RPLL_CON2_VAL 0x00000080

#define	BPLL_CON1_VAL 0x0020f300

#define	SPLL_CON1_VAL 0x0020f300

#define	IPLL_CON1_VAL 0x00000080

#define	KPLL_CON1_VAL 0x200000

#define	set_pll(mdiv, pdiv, sdiv) (1<<31 \| mdiv<<16 \| pdiv<<8 \| sdiv)

#define	MUX_HPM_SEL 1

#define	MUX_CPU_SEL 0

#define	MUX_APLL_SEL 1

#define	CLK_SRC_CPU_VAL

#define	DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)

#define	DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)

#define	DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)

#define	DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)

#define	DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)

#define	DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)

#define	DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)

#define	DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)

#define	DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)

#define	DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)

#define	DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)

#define	DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)

#define	DMC_MEMCONTROL_BL_8 (3 << 20)

#define	DMC_MEMCONTROL_BL_4 (2 << 20)

#define	DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)

#define	DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)

#define	DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)

#define	DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)

#define	DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)

#define	DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12)

#define	DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)

#define	DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)

#define	DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)

#define	DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)

#define	DMC_MEMCONFIGx_CHIP_ROW_16 (4 << 4)

#define	DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)

#define	DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)

#define	DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)

#define	DMC_PRECHCONFIG_VAL 0xFF000000

#define	DMC_PWRDNCONFIG_VAL 0xFFFF00FF

#define	DMC_CONCONTROL_RESET_VAL 0x0FFF0000

#define	DFI_INIT_START (1 << 28)

#define	EMPTY (1 << 8)

#define	AREF_EN (1 << 5)

#define	DFI_INIT_COMPLETE_CHO (1 << 2)

#define	DFI_INIT_COMPLETE_CH1 (1 << 3)

#define	RDLVL_COMPLETE_CHO (1 << 14)

#define	RDLVL_COMPLETE_CH1 (1 << 15)

#define	CLK_STOP_EN (1 << 0)

#define	DPWRDN_EN (1 << 1)

#define	DSREF_EN (1 << 5)

#define	DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)

#define	DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)

#define	DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)

#define	DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)

#define	DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)

#define	CLK_SRC_FSYS0_VAL 0x33033300

#define	CLK_DIV_FSYS0_VAL 0x0

#define	CLK_DIV_FSYS1_VAL 0x04f13c4f

#define	CLK_DIV_FSYS2_VAL 0x041d0000

#define	DMC_CONCONTROL_IO_PD_CON(x) (x << 6)

#define	HPM_RATIO 0x2

#define	COPY_RATIO 0x0

#define	CLK_DIV_CPU1_VAL

#define	CLK_SRC_CORE0_VAL 0x00000000

#define	CLK_SRC_CORE1_VAL 0x100

#define	CLK_DIV_CORE0_VAL 0x00120000

#define	CLK_DIV_CORE1_VAL 0x07070700

#define	CLK_DIV_SYSRGT_VAL 0x00000111

#define	CLK_DIV_ACP_VAL 0x12

#define	CLK_DIV_SYSLFT_VAL 0x00000311

#define	CLK_SRC_CDREX_VAL 0x00000001

#define	MUX_MCLK_CDR_MSPLL (1 << 4)

#define	MUX_BPLL_SEL_FOUTBPLL (1 << 0)

#define	BPLL_SEL_MASK 0x7

#define	FOUTBPLL 2

#define	CLK_DIV_CDREX0_VAL 0x30010100

#define	CLK_DIV_CDREX1_VAL 0x300

#define	CLK_DIV_CDREX_VAL 0x17010100

#define	CLK_DIV_CPU0_VAL 0x01440020

#define	CLK_SRC_TOP0_VAL 0x11101102

#define	CLK_SRC_TOP1_VAL 0x00200000

#define	CLK_SRC_TOP2_VAL 0x11101010

#define	CLK_SRC_TOP3_VAL 0x11111111

#define	CLK_SRC_TOP4_VAL 0x11110111

#define	CLK_SRC_TOP5_VAL 0x11111111

#define	CLK_SRC_TOP6_VAL 0x11110111

#define	CLK_SRC_TOP7_VAL 0x00022200

#define	CLK_DIV_TOP0_VAL 0x22512211

#define	CLK_DIV_TOP1_VAL 0x13200900

#define	CLK_DIV_TOP2_VAL 0x11101110

#define	APLL_LOCK_VAL (0x320)

#define	MPLL_LOCK_VAL (0x258)

#define	BPLL_LOCK_VAL (0x258)

#define	CPLL_LOCK_VAL (0x190)

#define	DPLL_LOCK_VAL (0x190)

#define	GPLL_LOCK_VAL NOT_AVAILABLE

#define	IPLL_LOCK_VAL (0x320)

#define	KPLL_LOCK_VAL (0x258)

#define	SPLL_LOCK_VAL (0x320)

#define	RPLL_LOCK_VAL (0x2328)

#define	EPLL_LOCK_VAL (0x2328)

#define	VPLL_LOCK_VAL (0x258)

#define	MUX_APLL_SEL_MASK (1 << 0)

#define	MUX_MPLL_SEL_MASK (1 << 8)

#define	MPLL_SEL_MOUT_MPLLFOUT (2 << 8)

#define	MUX_CPLL_SEL_MASK (1 << 8)

#define	MUX_EPLL_SEL_MASK (1 << 12)

#define	MUX_VPLL_SEL_MASK (1 << 16)

#define	MUX_GPLL_SEL_MASK (1 << 28)

#define	MUX_BPLL_SEL_MASK (1 << 0)

#define	MUX_HPM_SEL_MASK (1 << 20)

#define	HPM_SEL_SCLK_MPLL (1 << 21)

#define	PLL_LOCKED (1 << 29)

#define	APLL_CON0_LOCKED (1 << 29)

#define	MPLL_CON0_LOCKED (1 << 29)

#define	BPLL_CON0_LOCKED (1 << 29)

#define	CPLL_CON0_LOCKED (1 << 29)

#define	EPLL_CON0_LOCKED (1 << 29)

#define	GPLL_CON0_LOCKED (1 << 29)

#define	VPLL_CON0_LOCKED (1 << 29)

#define	CLK_REG_DISABLE 0x0

#define	TOP2_VAL 0x0110000

#define	CLK_SRC_LEX_VAL 0x0

#define	CLK_DIV_LEX_VAL 0x10

#define	CLK_DIV_R0X_VAL 0x10

#define	CLK_DIV_R1X_VAL 0x10

#define	CLK_DIV_ISP2_VAL 0x1

#define	SRC_KFC_HPM_SEL (1 << 15)

#define	CLK_SRC_KFC_VAL 0x00008001

#define	CLK_DIV_KFC_VAL 0x03300110

#define	CLK_DIV2_RATIO 0x10111150

#define	CLK_DIV4_RATIO 0x00000003

#define	CLK_DIV_G2D 0x00000010

#define	SPDIF_SEL 1

#define	PWM_SEL 3

#define	UART4_SEL 3

#define	UART3_SEL 3

#define	UART2_SEL 3

#define	UART1_SEL 3

#define	UART0_SEL 3

#define	CLK_SRC_PERIC0_VAL

#define	SPI0_SEL 3

#define	SPI1_SEL 3

#define	SPI2_SEL 3

#define	AUDIO0_SEL 6

#define	AUDIO1_SEL 6

#define	AUDIO2_SEL 6

#define	CLK_SRC_PERIC1_VAL

#define	CLK_SRC_ISP_VAL 0x33366000

#define	CLK_DIV_ISP0_VAL 0x13131300

#define	CLK_DIV_ISP1_VAL 0xbb110202

#define	SPI0_ISP_RATIO 0xf

#define	SPI1_ISP_RATIO 0xf

#define	SCLK_DIV_ISP_VAL

#define	PWM_RATIO 8

#define	UART4_RATIO 9

#define	UART3_RATIO 9

#define	UART2_RATIO 9

#define	UART1_RATIO 9

#define	UART0_RATIO 9

#define	CLK_DIV_PERIC0_VAL

#define	SPI2_RATIO 0x1

#define	SPI1_RATIO 0x1

#define	SPI0_RATIO 0x1

#define	CLK_DIV_PERIC1_VAL

#define	PCM2_RATIO 0x3

#define	PCM1_RATIO 0x3

#define	CLK_DIV_PERIC2_VAL

#define	AUDIO2_RATIO 0x5

#define	AUDIO1_RATIO 0x5

#define	AUDIO0_RATIO 0x5

#define	CLK_DIV_PERIC3_VAL

#define	SPI2_PRE_RATIO 0x3

#define	SPI1_PRE_RATIO 0x3

#define	SPI0_PRE_RATIO 0x3

#define	CLK_DIV_PERIC4_VAL

#define	MMC2_RATIO_MASK 0xf

#define	MMC2_RATIO_VAL 0x3

#define	MMC2_RATIO_OFFSET 0

#define	MMC2_PRE_RATIO_MASK 0xff

#define	MMC2_PRE_RATIO_VAL 0x9

#define	MMC2_PRE_RATIO_OFFSET 8

#define	MMC3_RATIO_MASK 0xf

#define	MMC3_RATIO_VAL 0x1

#define	MMC3_RATIO_OFFSET 16

#define	MMC3_PRE_RATIO_MASK 0xff

#define	MMC3_PRE_RATIO_VAL 0x0

#define	MMC3_PRE_RATIO_OFFSET 24

#define	CLK_SRC_LEX_VAL 0x0

#define	CLK_DIV_LEX_VAL 0x10

#define	CLK_DIV_R0X_VAL 0x10

#define	CLK_DIV_R1X_VAL 0x10

#define	CLK_DIV_ISP2_VAL 0x1

#define	CLK_SRC_DISP1_0_VAL 0x10006000

#define	CLK_DIV_DISP1_0_VAL 0x01050210

#define	CLK_DIV_DISP1_0_FIMD1 (2 << 0)

#define	CLK_GATE_DP1_ALLOW (1 << 4)

#define	CLK_C2C_MASK (1 << 1)

#define	CLK_SMMUG2D_MASK (1 << 7)

#define	CLK_SMMUSSS_MASK (1 << 6)

#define	CLK_SMMUMDMA_MASK (1 << 5)

#define	CLK_ID_REMAPPER_MASK (1 << 4)

#define	CLK_G2D_MASK (1 << 3)

#define	CLK_SSS_MASK (1 << 2)

#define	CLK_MDMA_MASK (1 << 1)

#define	CLK_SECJTAG_MASK (1 << 0)

#define	CLK_EFCLK_MASK (1 << 16)

#define	CLK_UART_ISP_MASK (1 << 31)

#define	CLK_WDT_ISP_MASK (1 << 30)

#define	CLK_PWM_ISP_MASK (1 << 28)

#define	CLK_MTCADC_ISP_MASK (1 << 27)

#define	CLK_I2C1_ISP_MASK (1 << 26)

#define	CLK_I2C0_ISP_MASK (1 << 25)

#define	CLK_MPWM_ISP_MASK (1 << 24)

#define	CLK_MCUCTL_ISP_MASK (1 << 23)

#define	CLK_INT_COMB_ISP_MASK (1 << 22)

#define	CLK_SMMU_MCUISP_MASK (1 << 13)

#define	CLK_SMMU_SCALERP_MASK (1 << 12)

#define	CLK_SMMU_SCALERC_MASK (1 << 11)

#define	CLK_SMMU_FD_MASK (1 << 10)

#define	CLK_SMMU_DRC_MASK (1 << 9)

#define	CLK_SMMU_ISP_MASK (1 << 8)

#define	CLK_GICISP_MASK (1 << 7)

#define	CLK_ARM9S_MASK (1 << 6)

#define	CLK_MCUISP_MASK (1 << 5)

#define	CLK_SCALERP_MASK (1 << 4)

#define	CLK_SCALERC_MASK (1 << 3)

#define	CLK_FD_MASK (1 << 2)

#define	CLK_DRC_MASK (1 << 1)

#define	CLK_ISP_MASK (1 << 0)

#define	CLK_SPI1_ISP_MASK (1 << 13)

#define	CLK_SPI0_ISP_MASK (1 << 12)

#define	CLK_SMMU3DNR_MASK (1 << 7)

#define	CLK_SMMUDIS1_MASK (1 << 6)

#define	CLK_SMMUDIS0_MASK (1 << 5)

#define	CLK_SMMUODC_MASK (1 << 4)

#define	CLK_3DNR_MASK (1 << 2)

#define	CLK_DIS_MASK (1 << 1)

#define	CLK_ODC_MASK (1 << 0)

#define	CLK_SMMUFIMC_LITE2_MASK (1 << 20)

#define	CLK_SMMUFIMC_LITE1_MASK (1 << 12)

#define	CLK_SMMUFIMC_LITE0_MASK (1 << 11)

#define	CLK_SMMUGSCL3_MASK (1 << 10)

#define	CLK_SMMUGSCL2_MASK (1 << 9)

#define	CLK_SMMUGSCL1_MASK (1 << 8)

#define	CLK_SMMUGSCL0_MASK (1 << 7)

#define	CLK_GSCL_WRAP_B_MASK (1 << 6)

#define	CLK_GSCL_WRAP_A_MASK (1 << 5)

#define	CLK_CAMIF_TOP_MASK (1 << 4)

#define	CLK_GSCL3_MASK (1 << 3)

#define	CLK_GSCL2_MASK (1 << 2)

#define	CLK_GSCL1_MASK (1 << 1)

#define	CLK_GSCL0_MASK (1 << 0)

#define	CLK_SMMUMFCR_MASK (1 << 2)

#define	CLK_SMMUMFCL_MASK (1 << 1)

#define	CLK_MFC_MASK (1 << 0)

#define	SCLK_MPWM_ISP_MASK (1 << 0)

#define	CLK_SMMUTVX_MASK (1 << 9)

#define	CLK_ASYNCTVX_MASK (1 << 7)

#define	CLK_HDMI_MASK (1 << 6)

#define	CLK_MIXER_MASK (1 << 5)

#define	CLK_DSIM1_MASK (1 << 3)

#define	AUDIO0_SEL_EPLL (0x6 << 28)

#define	AUDIO0_RATIO 0x5

#define	PCM0_RATIO 0x3

#define	DIV_MAU_VAL (PCM0_RATIO << 24 \| AUDIO0_RATIO << 20)

#define	CLK_SMMUMDMA1_MASK (1 << 9)

#define	CLK_SMMUJPEG_MASK (1 << 7)

#define	CLK_SMMUROTATOR_MASK (1 << 6)

#define	CLK_MDMA1_MASK (1 << 4)

#define	CLK_JPEG_MASK (1 << 2)

#define	CLK_ROTATOR_MASK (1 << 1)

#define	CLK_WDT_IOP_MASK (1 << 30)

#define	CLK_SMMUMCU_IOP_MASK (1 << 26)

#define	CLK_SATA_PHY_I2C_MASK (1 << 25)

#define	CLK_SATA_PHY_CTRL_MASK (1 << 24)

#define	CLK_MCUCTL_MASK (1 << 23)

#define	CLK_NFCON_MASK (1 << 22)

#define	CLK_SMMURTIC_MASK (1 << 11)

#define	CLK_RTIC_MASK (1 << 9)

#define	CLK_MIPI_HSI_MASK (1 << 8)

#define	CLK_USBOTG_MASK (1 << 7)

#define	CLK_SATA_MASK (1 << 6)

#define	CLK_PDMA1_MASK (1 << 2)

#define	CLK_PDMA0_MASK (1 << 1)

#define	CLK_MCU_IOP_MASK (1 << 0)

#define	CLK_HS_I2C3_MASK (1 << 31)

#define	CLK_HS_I2C2_MASK (1 << 30)

#define	CLK_HS_I2C1_MASK (1 << 29)

#define	CLK_HS_I2C0_MASK (1 << 28)

#define	CLK_AC97_MASK (1 << 27)

#define	CLK_SPDIF_MASK (1 << 26)

#define	CLK_PCM2_MASK (1 << 23)

#define	CLK_PCM1_MASK (1 << 22)

#define	CLK_I2S2_MASK (1 << 21)

#define	CLK_I2S1_MASK (1 << 20)

#define	CLK_SPI2_MASK (1 << 18)

#define	CLK_SPI0_MASK (1 << 16)

#define	CLK_I2CHDMI_MASK (1 << 14)

#define	CLK_I2C7_MASK (1 << 13)

#define	CLK_I2C6_MASK (1 << 12)

#define	CLK_I2C5_MASK (1 << 11)

#define	CLK_I2C4_MASK (1 << 10)

#define	CLK_I2C3_MASK (1 << 9)

#define	CLK_I2C2_MASK (1 << 8)

#define	CLK_I2C1_MASK (1 << 7)

#define	CLK_I2C0_MASK (1 << 6)

#define	CLK_RTC_MASK (1 << 20)

#define	CLK_TZPC9_MASK (1 << 15)

#define	CLK_TZPC8_MASK (1 << 14)

#define	CLK_TZPC7_MASK (1 << 13)

#define	CLK_TZPC6_MASK (1 << 12)

#define	CLK_TZPC5_MASK (1 << 11)

#define	CLK_TZPC4_MASK (1 << 10)

#define	CLK_TZPC3_MASK (1 << 9)

#define	CLK_TZPC2_MASK (1 << 8)

#define	CLK_TZPC1_MASK (1 << 7)

#define	CLK_TZPC0_MASK (1 << 6)

#define	CLK_CHIPID_MASK (1 << 0)

#define	CLK_ACP_MASK (1 << 7)

#define	CLK_TZASC_DRBXW_MASK (1 << 23)

#define	CLK_TZASC_DRBXR_MASK (1 << 22)

#define	CLK_TZASC_XLBXW_MASK (1 << 21)

#define	CLK_TZASC_XLBXR_MASK (1 << 20)

#define	CLK_TZASC_XR1BXW_MASK (1 << 19)

#define	CLK_TZASC_XR1BXR_MASK (1 << 18)

#define	CLK_DPHY1_MASK (1 << 5)

#define	CLK_DPHY0_MASK (1 << 4)

#define	R0SIZE 0x0

#define	DECPROTXSET 0xFF

#define	LPDDR3PHY_CTRL_PHY_RESET (1 << 0)

#define	LPDDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)

#define	PHY_CON0_RESET_VAL 0x17020a40

#define	P0_CMD_EN (1 << 14)

#define	BYTE_RDLVL_EN (1 << 13)

#define	CTRL_SHGATE (1 << 8)

#define	PHY_CON1_RESET_VAL 0x09210100

#define	RDLVL_PASS_ADJ_VAL 0x6

#define	RDLVL_PASS_ADJ_OFFSET 16

#define	CTRL_GATEDURADJ_MASK (0xf << 20)

#define	READ_LEVELLING_DDR3 0x0100

#define	PHY_CON2_RESET_VAL 0x00010004

#define	INIT_DESKEW_EN (1 << 6)

#define	DLL_DESKEW_EN (1 << 12)

#define	RDLVL_GATE_EN (1 << 24)

#define	RDLVL_EN (1 << 25)

#define	RDLVL_INCR_ADJ (0x1 << 16)

#define	DREX_PAUSE_EN (1 << 0)

#define	BYPASS_EN (1 << 22)

#define	PHY_CON0_VAL 0x17021A00

#define	PHY_CON12_RESET_VAL 0x10100070

#define	PHY_CON12_VAL 0x10107F50

#define	CTRL_START (1 << 6)

#define	CTRL_DLL_ON (1 << 5)

#define	CTRL_FORCE_MASK (0x7F << 8)

#define	CTRL_LOCK_COARSE_MASK (0x7F << 10)

#define	CTRL_OFFSETD_RESET_VAL 0x8

#define	CTRL_OFFSETD_VAL 0x7F

#define	CTRL_OFFSETR0 0x7F

#define	CTRL_OFFSETR1 0x7F

#define	CTRL_OFFSETR2 0x7F

#define	CTRL_OFFSETR3 0x7F

#define	PHY_CON4_VAL

#define	PHY_CON4_RESET_VAL 0x08080808

#define	CTRL_OFFSETW0 0x7F

#define	CTRL_OFFSETW1 0x7F

#define	CTRL_OFFSETW2 0x7F

#define	CTRL_OFFSETW3 0x7F

#define	PHY_CON6_VAL

#define	PHY_CON6_RESET_VAL 0x08080808

#define	PHY_CON14_RESET_VAL 0x001F0000

#define	CTRL_PULLD_DQS 0xF

#define	CTRL_PULLD_DQS_OFFSET 0

#define	PHY_CON16_RESET_VAL 0x08000304

#define	ZQ_CLK_EN (1 << 27)

#define	ZQ_CLK_DIV_EN (1 << 18)

#define	ZQ_MANUAL_MODE_OFFSET 2

#define	ZQ_LONG_CALIBRATION 0x1

#define	ZQ_MANUAL_STR (1 << 1)

#define	ZQ_DONE (1 << 0)

#define	ZQ_MODE_DDS_OFFSET 24

#define	LONG_CALIBRATION (ZQ_LONG_CALIBRATION << ZQ_MANUAL_MODE_OFFSET)

#define	CTRL_RDLVL_GATE_ENABLE 1

#define	CTRL_RDLVL_GATE_DISABLE 0

#define	CTRL_RDLVL_DATA_ENABLE (1 << 1)

#define	DIRECT_CMD_NOP 0x07000000

#define	DIRECT_CMD_PALL 0x01000000

#define	DIRECT_CMD_ZQINIT 0x0a000000

#define	DIRECT_CMD_CHANNEL_SHIFT 28

#define	DIRECT_CMD_CHIP_SHIFT 20

#define	DIRECT_CMD_BANK_SHIFT 16

#define	DIRECT_CMD_REFA (5 << 24)

#define	DIRECT_CMD_MRS1 0x71C00

#define	DIRECT_CMD_MRS2 0x10BFC

#define	DIRECT_CMD_MRS3 0x0050C

#define	DIRECT_CMD_MRS4 0x00868

#define	DIRECT_CMD_MRS5 0x00C04

#define	IMPEDANCE_48_OHM 4

#define	IMPEDANCE_40_OHM 5

#define	IMPEDANCE_34_OHM 6

#define	IMPEDANCE_30_OHM 7

#define	PHY_CON39_VAL_48_OHM 0x09240924

#define	PHY_CON39_VAL_40_OHM 0x0B6D0B6D

#define	PHY_CON39_VAL_34_OHM 0x0DB60DB6

#define	PHY_CON39_VAL_30_OHM 0x0FFF0FFF

#define	CTRL_BSTLEN_OFFSET 8

#define	CTRL_RDLAT_OFFSET 0

#define	CMD_DEFAULT_LPDDR3 0xF

#define	CMD_DEFAULT_OFFSET 0

#define	T_WRDATA_EN 0x7

#define	T_WRDATA_EN_DDR3 0x8 /* FIXME(dhendrix): 6 for DDR3? see T_wrdata_en */

#define	T_WRDATA_EN_OFFSET 16

#define	T_WRDATA_EN_MASK 0x1f

#define	PHY_CON31_VAL 0x0C183060

#define	PHY_CON32_VAL 0x60C18306

#define	PHY_CON33_VAL 0x00000030

#define	PHY_CON31_RESET_VAL 0x0

#define	PHY_CON32_RESET_VAL 0x0

#define	PHY_CON33_RESET_VAL 0x0

#define	SL_DLL_DYN_CON_EN (1 << 1)

#define	FP_RESYNC (1 << 3)

#define	CTRL_START (1 << 6)

#define	DMC_AREF_EN (1 << 5)

#define	DMC_CONCONTROL_EMPTY (1 << 8)

#define	DFI_INIT_START (1 << 28)

#define	DMC_MEMCONTROL_VAL 0x00312700

#define	CLK_STOP_EN (1 << 0)

#define	DPWRDN_EN (1 << 1)

#define	DSREF_EN (1 << 5)

#define	DMC_CHIP_MASK_256MB 0x7f0

#define	DMC_CHIP_MASK_512MB 0x7e0

#define	DMC_CHIP_MASK_1GB 0x7c0

#define	DMC_CHIP_MASK_2GB 0x780

#define	DMC_CHIP_MASK_4GB 0x700

#define	MEMCONFIG_VAL 0x1323

#define	PRECHCONFIG_DEFAULT_VAL 0xFF000000

#define	PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF

#define	DFI_INIT_COMPLETE (1 << 3)

#define	BRBRSVCONTROL_VAL 0x00000033

#define	BRBRSVCONFIG_VAL 0x88778877

#define	MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */

#define	SCG_CG_EN (1 << 2) /* Scheduler clock gating */

#define	BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */

#define	BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */

#define	DMC_INTERNAL_CG

#define	PHY_CONTROL0_RESET_VAL 0x0

#define	MEM_TERM_EN (1 << 31) /* Termination enable for memory */

#define	PHY_TERM_EN (1 << 30) /* Termination enable for PHY */

#define	DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */

#define	CTRL_ATGATE (1 << 6)

#define	FP_RSYNC (1 << 3) /* Force DLL resynchronization */

#define	IMP_OUTPUT_DRV_40_OHM 0x5

#define	IMP_OUTPUT_DRV_30_OHM 0x7

#define	DA_3_DS_OFFSET 25

#define	DA_2_DS_OFFSET 22

#define	DA_1_DS_OFFSET 19

#define	DA_0_DS_OFFSET 16

#define	CA_CK_DRVR_DS_OFFSET 9

#define	CA_CKE_DRVR_DS_OFFSET 6

#define	CA_CS_DRVR_DS_OFFSET 3

#define	CA_ADR_DRVR_DS_OFFSET 0

#define	PHY_CON42_CTRL_BSTLEN_SHIFT 8

#define	PHY_CON42_CTRL_RDLAT_SHIFT 0

Enumerations
enum	{ SETUP_ERR_OK , SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1 , SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2 }

Functions
void	cpu_info_init (void)

void	mem_ctrl_init (void)

int	ddr3_mem_ctrl_init (struct mem_timings *mem, int interleave_size, int reset)

int	lpddr3_mem_ctrl_init (int reset)

int	dmc_config_zq (struct mem_timings mem, struct exynos5_phy_control phy0_ctrl, struct exynos5_phy_control *phy1_ctrl)

void	dmc_config_mrs (struct mem_timings mem, struct exynos5_dmc dmc)

void	dmc_config_prech (struct mem_timings mem, struct exynos5_dmc dmc)

void	dmc_config_memory (struct mem_timings mem, struct exynos5_dmc dmc)

void	update_reset_dll (struct exynos5_dmc *, enum ddr_mode)

Macro Definition Documentation

◆ APLL_CON0_LOCKED

#define APLL_CON0_LOCKED (1 << 29)

Definition at line 256 of file setup.h.

◆ APLL_CON1_VAL

#define APLL_CON1_VAL (0x0020f300)

Definition at line 37 of file setup.h.

◆ APLL_FOUT

#define APLL_FOUT (1 << 0)

Definition at line 31 of file setup.h.

◆ APLL_LOCK_VAL

#define APLL_LOCK_VAL (0x320)

Definition at line 221 of file setup.h.

◆ AREF_EN

#define AREF_EN (1 << 5)

Definition at line 133 of file setup.h.

◆ AUDIO0_RATIO [1/2]

#define AUDIO0_RATIO 0x5

Definition at line 517 of file setup.h.

◆ AUDIO0_RATIO [2/2]

#define AUDIO0_RATIO 0x5

Definition at line 517 of file setup.h.

◆ AUDIO0_SEL

#define AUDIO0_SEL 6

Definition at line 322 of file setup.h.

◆ AUDIO0_SEL_EPLL

#define AUDIO0_SEL_EPLL (0x6 << 28)

Definition at line 516 of file setup.h.

◆ AUDIO1_RATIO

#define AUDIO1_RATIO 0x5

Definition at line 374 of file setup.h.

◆ AUDIO1_SEL

#define AUDIO1_SEL 6

Definition at line 323 of file setup.h.

◆ AUDIO2_RATIO

#define AUDIO2_RATIO 0x5

Definition at line 373 of file setup.h.

◆ AUDIO2_SEL

#define AUDIO2_SEL 6

Definition at line 324 of file setup.h.

◆ BPLL_CON0_LOCKED

#define BPLL_CON0_LOCKED (1 << 29)

Definition at line 258 of file setup.h.

◆ BPLL_CON1_VAL

#define BPLL_CON1_VAL 0x0020f300

Definition at line 64 of file setup.h.

◆ BPLL_LOCK_VAL

#define BPLL_LOCK_VAL (0x258)

Definition at line 225 of file setup.h.

◆ BPLL_SEL_MASK

#define BPLL_SEL_MASK 0x7

Definition at line 193 of file setup.h.

◆ BRBRSVCONFIG_VAL

#define BRBRSVCONFIG_VAL 0x88778877

Definition at line 758 of file setup.h.

◆ BRBRSVCONTROL_VAL

#define BRBRSVCONTROL_VAL 0x00000033

Definition at line 757 of file setup.h.

◆ BUSIF_RD_CG_EN

#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */

Definition at line 764 of file setup.h.

◆ BUSIF_WR_CG_EN

#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */

Definition at line 763 of file setup.h.

◆ BYPASS_EN

#define BYPASS_EN (1 << 22)

Definition at line 633 of file setup.h.

◆ BYTE_RDLVL_EN

#define BYTE_RDLVL_EN (1 << 13)

Definition at line 614 of file setup.h.

◆ CA_ADR_DRVR_DS_OFFSET

#define CA_ADR_DRVR_DS_OFFSET 0

Definition at line 786 of file setup.h.

◆ CA_CK_DRVR_DS_OFFSET

#define CA_CK_DRVR_DS_OFFSET 9

Definition at line 783 of file setup.h.

◆ CA_CKE_DRVR_DS_OFFSET

#define CA_CKE_DRVR_DS_OFFSET 6

Definition at line 784 of file setup.h.

◆ CA_CS_DRVR_DS_OFFSET

#define CA_CS_DRVR_DS_OFFSET 3

Definition at line 785 of file setup.h.

◆ CA_SWAP_EN

#define CA_SWAP_EN (1 << 0)

Definition at line 17 of file setup.h.

◆ CLK_3DNR_MASK

#define CLK_3DNR_MASK (1 << 2)

Definition at line 481 of file setup.h.

◆ CLK_AC97_MASK

#define CLK_AC97_MASK (1 << 27)

Definition at line 550 of file setup.h.

◆ CLK_ACP_MASK

#define CLK_ACP_MASK (1 << 7)

Definition at line 583 of file setup.h.

◆ CLK_ARM9S_MASK

#define CLK_ARM9S_MASK (1 << 6)

Definition at line 466 of file setup.h.

◆ CLK_ASYNCTVX_MASK

#define CLK_ASYNCTVX_MASK (1 << 7)

Definition at line 510 of file setup.h.

◆ CLK_C2C_MASK

#define CLK_C2C_MASK (1 << 1)

Definition at line 434 of file setup.h.

◆ CLK_CAMIF_TOP_MASK

#define CLK_CAMIF_TOP_MASK (1 << 4)

Definition at line 495 of file setup.h.

◆ CLK_CHIPID_MASK

#define CLK_CHIPID_MASK (1 << 0)

Definition at line 580 of file setup.h.

◆ CLK_DIS_MASK

#define CLK_DIS_MASK (1 << 1)

Definition at line 482 of file setup.h.

◆ CLK_DIV2_RATIO

#define CLK_DIV2_RATIO 0x10111150

Definition at line 291 of file setup.h.

◆ CLK_DIV4_RATIO

#define CLK_DIV4_RATIO 0x00000003

Definition at line 294 of file setup.h.

◆ CLK_DIV_ACP_VAL

#define CLK_DIV_ACP_VAL 0x12

Definition at line 184 of file setup.h.

◆ CLK_DIV_CDREX0_VAL

#define CLK_DIV_CDREX0_VAL 0x30010100

Definition at line 197 of file setup.h.

◆ CLK_DIV_CDREX1_VAL

#define CLK_DIV_CDREX1_VAL 0x300

Definition at line 198 of file setup.h.

◆ CLK_DIV_CDREX_VAL

#define CLK_DIV_CDREX_VAL 0x17010100

Definition at line 200 of file setup.h.

◆ CLK_DIV_CORE0_VAL

#define CLK_DIV_CORE0_VAL 0x00120000

Definition at line 175 of file setup.h.

◆ CLK_DIV_CORE1_VAL

#define CLK_DIV_CORE1_VAL 0x07070700

Definition at line 178 of file setup.h.

◆ CLK_DIV_CPERI1_VAL

#define CLK_DIV_CPERI1_VAL 0x3f3f0000

Definition at line 34 of file setup.h.

◆ CLK_DIV_CPU0_VAL

#define CLK_DIV_CPU0_VAL 0x01440020

Definition at line 203 of file setup.h.

◆ CLK_DIV_CPU1_VAL

#define CLK_DIV_CPU1_VAL

Value:

((HPM_RATIO << 4) \

| (COPY_RATIO))

HPM_RATIO

#define HPM_RATIO

Definition: setup.h:161

COPY_RATIO

#define COPY_RATIO

Definition: setup.h:162

Definition at line 165 of file setup.h.

◆ CLK_DIV_DISP1_0_FIMD1

#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)

Definition at line 428 of file setup.h.

◆ CLK_DIV_DISP1_0_VAL

#define CLK_DIV_DISP1_0_VAL 0x01050210

Definition at line 422 of file setup.h.

◆ CLK_DIV_FSYS0_VAL

#define CLK_DIV_FSYS0_VAL 0x0

Definition at line 154 of file setup.h.

◆ CLK_DIV_FSYS1_VAL

#define CLK_DIV_FSYS1_VAL 0x04f13c4f

Definition at line 155 of file setup.h.

◆ CLK_DIV_FSYS2_VAL

#define CLK_DIV_FSYS2_VAL 0x041d0000

Definition at line 156 of file setup.h.

◆ CLK_DIV_G2D

#define CLK_DIV_G2D 0x00000010

Definition at line 297 of file setup.h.

◆ CLK_DIV_ISP0_VAL

#define CLK_DIV_ISP0_VAL 0x13131300

Definition at line 334 of file setup.h.

◆ CLK_DIV_ISP1_VAL

#define CLK_DIV_ISP1_VAL 0xbb110202

Definition at line 335 of file setup.h.

◆ CLK_DIV_ISP2_VAL [1/2]

#define CLK_DIV_ISP2_VAL 0x1

Definition at line 418 of file setup.h.

◆ CLK_DIV_ISP2_VAL [2/2]

#define CLK_DIV_ISP2_VAL 0x1

Definition at line 418 of file setup.h.

◆ CLK_DIV_KFC_VAL

#define CLK_DIV_KFC_VAL 0x03300110

Definition at line 288 of file setup.h.

◆ CLK_DIV_LEX_VAL [1/2]

#define CLK_DIV_LEX_VAL 0x10

Definition at line 409 of file setup.h.

◆ CLK_DIV_LEX_VAL [2/2]

#define CLK_DIV_LEX_VAL 0x10

Definition at line 409 of file setup.h.

◆ CLK_DIV_PERIC0_VAL

#define CLK_DIV_PERIC0_VAL

Value:

                                ((PWM_RATIO << 28)      \
                                | (UART4_RATIO << 24)   \
                                | (UART3_RATIO << 20)    \
                                | (UART2_RATIO << 16)    \
                                | (UART1_RATIO << 12)    \
                                | (UART0_RATIO << 8))

Definition at line 351 of file setup.h.

◆ CLK_DIV_PERIC1_VAL

#define CLK_DIV_PERIC1_VAL

Value:

                                ((SPI2_RATIO << 28)     \
                                | (SPI1_RATIO << 24)    \
                                | (SPI0_RATIO << 20))

Definition at line 362 of file setup.h.

◆ CLK_DIV_PERIC2_VAL

#define CLK_DIV_PERIC2_VAL

Value:

((PCM2_RATIO << 24) \

| (PCM1_RATIO << 16))

PCM1_RATIO

#define PCM1_RATIO

Definition: setup.h:368

PCM2_RATIO

#define PCM2_RATIO

Definition: setup.h:367

Definition at line 369 of file setup.h.

◆ CLK_DIV_PERIC3_VAL

#define CLK_DIV_PERIC3_VAL

Value:

                                ((AUDIO2_RATIO << 28)   \
                                | (AUDIO1_RATIO << 24)  \
                                | (AUDIO0_RATIO << 20))

Definition at line 376 of file setup.h.

◆ CLK_DIV_PERIC4_VAL

#define CLK_DIV_PERIC4_VAL

Value:

                                ((SPI2_PRE_RATIO << 24) \
                                | (SPI1_PRE_RATIO << 16) \
                                | (SPI0_PRE_RATIO << 8))

Definition at line 384 of file setup.h.

◆ CLK_DIV_R0X_VAL [1/2]

#define CLK_DIV_R0X_VAL 0x10

Definition at line 412 of file setup.h.

◆ CLK_DIV_R0X_VAL [2/2]

#define CLK_DIV_R0X_VAL 0x10

Definition at line 412 of file setup.h.

◆ CLK_DIV_R1X_VAL [1/2]

#define CLK_DIV_R1X_VAL 0x10

Definition at line 415 of file setup.h.

◆ CLK_DIV_R1X_VAL [2/2]

#define CLK_DIV_R1X_VAL 0x10

Definition at line 415 of file setup.h.

◆ CLK_DIV_SYSLFT_VAL

#define CLK_DIV_SYSLFT_VAL 0x00000311

Definition at line 187 of file setup.h.

◆ CLK_DIV_SYSRGT_VAL

#define CLK_DIV_SYSRGT_VAL 0x00000111

Definition at line 181 of file setup.h.

◆ CLK_DIV_TOP0_VAL

#define CLK_DIV_TOP0_VAL 0x22512211

Definition at line 216 of file setup.h.

◆ CLK_DIV_TOP1_VAL

#define CLK_DIV_TOP1_VAL 0x13200900

Definition at line 217 of file setup.h.

◆ CLK_DIV_TOP2_VAL

#define CLK_DIV_TOP2_VAL 0x11101110

Definition at line 218 of file setup.h.

◆ CLK_DPHY0_MASK

#define CLK_DPHY0_MASK (1 << 4)

Definition at line 593 of file setup.h.

◆ CLK_DPHY1_MASK

#define CLK_DPHY1_MASK (1 << 5)

Definition at line 592 of file setup.h.

◆ CLK_DRC_MASK

#define CLK_DRC_MASK (1 << 1)

Definition at line 471 of file setup.h.

◆ CLK_DSIM1_MASK

#define CLK_DSIM1_MASK (1 << 3)

Definition at line 513 of file setup.h.

◆ CLK_EFCLK_MASK

#define CLK_EFCLK_MASK (1 << 16)

Definition at line 447 of file setup.h.

◆ CLK_FD_MASK

#define CLK_FD_MASK (1 << 2)

Definition at line 470 of file setup.h.

◆ CLK_G2D_MASK

#define CLK_G2D_MASK (1 << 3)

Definition at line 441 of file setup.h.

◆ CLK_GATE_DP1_ALLOW

#define CLK_GATE_DP1_ALLOW (1 << 4)

Definition at line 431 of file setup.h.

◆ CLK_GICISP_MASK

#define CLK_GICISP_MASK (1 << 7)

Definition at line 465 of file setup.h.

◆ CLK_GSCL0_MASK

#define CLK_GSCL0_MASK (1 << 0)

Definition at line 499 of file setup.h.

◆ CLK_GSCL1_MASK

#define CLK_GSCL1_MASK (1 << 1)

Definition at line 498 of file setup.h.

◆ CLK_GSCL2_MASK

#define CLK_GSCL2_MASK (1 << 2)

Definition at line 497 of file setup.h.

◆ CLK_GSCL3_MASK

#define CLK_GSCL3_MASK (1 << 3)

Definition at line 496 of file setup.h.

◆ CLK_GSCL_WRAP_A_MASK

#define CLK_GSCL_WRAP_A_MASK (1 << 5)

Definition at line 494 of file setup.h.

◆ CLK_GSCL_WRAP_B_MASK

#define CLK_GSCL_WRAP_B_MASK (1 << 6)

Definition at line 493 of file setup.h.

◆ CLK_HDMI_MASK

#define CLK_HDMI_MASK (1 << 6)

Definition at line 511 of file setup.h.

◆ CLK_HS_I2C0_MASK

#define CLK_HS_I2C0_MASK (1 << 28)

Definition at line 549 of file setup.h.

◆ CLK_HS_I2C1_MASK

#define CLK_HS_I2C1_MASK (1 << 29)

Definition at line 548 of file setup.h.

◆ CLK_HS_I2C2_MASK

#define CLK_HS_I2C2_MASK (1 << 30)

Definition at line 547 of file setup.h.

◆ CLK_HS_I2C3_MASK

#define CLK_HS_I2C3_MASK (1 << 31)

Definition at line 546 of file setup.h.

◆ CLK_I2C0_ISP_MASK

#define CLK_I2C0_ISP_MASK (1 << 25)

Definition at line 455 of file setup.h.

◆ CLK_I2C0_MASK

#define CLK_I2C0_MASK (1 << 6)

Definition at line 566 of file setup.h.

◆ CLK_I2C1_ISP_MASK

#define CLK_I2C1_ISP_MASK (1 << 26)

Definition at line 454 of file setup.h.

◆ CLK_I2C1_MASK

#define CLK_I2C1_MASK (1 << 7)

Definition at line 565 of file setup.h.

◆ CLK_I2C2_MASK

#define CLK_I2C2_MASK (1 << 8)

Definition at line 564 of file setup.h.

◆ CLK_I2C3_MASK

#define CLK_I2C3_MASK (1 << 9)

Definition at line 563 of file setup.h.

◆ CLK_I2C4_MASK

#define CLK_I2C4_MASK (1 << 10)

Definition at line 562 of file setup.h.

◆ CLK_I2C5_MASK

#define CLK_I2C5_MASK (1 << 11)

Definition at line 561 of file setup.h.

◆ CLK_I2C6_MASK

#define CLK_I2C6_MASK (1 << 12)

Definition at line 560 of file setup.h.

◆ CLK_I2C7_MASK

#define CLK_I2C7_MASK (1 << 13)

Definition at line 559 of file setup.h.

◆ CLK_I2CHDMI_MASK

#define CLK_I2CHDMI_MASK (1 << 14)

Definition at line 558 of file setup.h.

◆ CLK_I2S1_MASK

#define CLK_I2S1_MASK (1 << 20)

Definition at line 555 of file setup.h.

◆ CLK_I2S2_MASK

#define CLK_I2S2_MASK (1 << 21)

Definition at line 554 of file setup.h.

◆ CLK_ID_REMAPPER_MASK

#define CLK_ID_REMAPPER_MASK (1 << 4)

Definition at line 440 of file setup.h.

◆ CLK_INT_COMB_ISP_MASK

#define CLK_INT_COMB_ISP_MASK (1 << 22)

Definition at line 458 of file setup.h.

◆ CLK_ISP_MASK

#define CLK_ISP_MASK (1 << 0)

Definition at line 472 of file setup.h.

◆ CLK_JPEG_MASK

#define CLK_JPEG_MASK (1 << 2)

Definition at line 526 of file setup.h.

◆ CLK_MCU_IOP_MASK

#define CLK_MCU_IOP_MASK (1 << 0)

Definition at line 543 of file setup.h.

◆ CLK_MCUCTL_ISP_MASK

#define CLK_MCUCTL_ISP_MASK (1 << 23)

Definition at line 457 of file setup.h.

◆ CLK_MCUCTL_MASK

#define CLK_MCUCTL_MASK (1 << 23)

Definition at line 534 of file setup.h.

◆ CLK_MCUISP_MASK

#define CLK_MCUISP_MASK (1 << 5)

Definition at line 467 of file setup.h.

◆ CLK_MDMA1_MASK

#define CLK_MDMA1_MASK (1 << 4)

Definition at line 525 of file setup.h.

◆ CLK_MDMA_MASK

#define CLK_MDMA_MASK (1 << 1)

Definition at line 443 of file setup.h.

◆ CLK_MFC_MASK

#define CLK_MFC_MASK (1 << 0)

Definition at line 504 of file setup.h.

◆ CLK_MIPI_HSI_MASK

#define CLK_MIPI_HSI_MASK (1 << 8)

Definition at line 538 of file setup.h.

◆ CLK_MIXER_MASK

#define CLK_MIXER_MASK (1 << 5)

Definition at line 512 of file setup.h.

◆ CLK_MPWM_ISP_MASK

#define CLK_MPWM_ISP_MASK (1 << 24)

Definition at line 456 of file setup.h.

◆ CLK_MTCADC_ISP_MASK

#define CLK_MTCADC_ISP_MASK (1 << 27)

Definition at line 453 of file setup.h.

◆ CLK_NFCON_MASK

#define CLK_NFCON_MASK (1 << 22)

Definition at line 535 of file setup.h.

◆ CLK_ODC_MASK

#define CLK_ODC_MASK (1 << 0)

Definition at line 483 of file setup.h.

◆ CLK_PCM1_MASK

#define CLK_PCM1_MASK (1 << 22)

Definition at line 553 of file setup.h.

◆ CLK_PCM2_MASK

#define CLK_PCM2_MASK (1 << 23)

Definition at line 552 of file setup.h.

◆ CLK_PDMA0_MASK

#define CLK_PDMA0_MASK (1 << 1)

Definition at line 542 of file setup.h.

◆ CLK_PDMA1_MASK

#define CLK_PDMA1_MASK (1 << 2)

Definition at line 541 of file setup.h.

◆ CLK_PWM_ISP_MASK

#define CLK_PWM_ISP_MASK (1 << 28)

Definition at line 452 of file setup.h.

◆ CLK_REG_DISABLE

#define CLK_REG_DISABLE 0x0

Definition at line 263 of file setup.h.

◆ CLK_ROTATOR_MASK

#define CLK_ROTATOR_MASK (1 << 1)

Definition at line 527 of file setup.h.

◆ CLK_RTC_MASK

#define CLK_RTC_MASK (1 << 20)

Definition at line 569 of file setup.h.

◆ CLK_RTIC_MASK

#define CLK_RTIC_MASK (1 << 9)

Definition at line 537 of file setup.h.

◆ CLK_SATA_MASK

#define CLK_SATA_MASK (1 << 6)

Definition at line 540 of file setup.h.

◆ CLK_SATA_PHY_CTRL_MASK

#define CLK_SATA_PHY_CTRL_MASK (1 << 24)

Definition at line 533 of file setup.h.

◆ CLK_SATA_PHY_I2C_MASK

#define CLK_SATA_PHY_I2C_MASK (1 << 25)

Definition at line 532 of file setup.h.

◆ CLK_SCALERC_MASK

#define CLK_SCALERC_MASK (1 << 3)

Definition at line 469 of file setup.h.

◆ CLK_SCALERP_MASK

#define CLK_SCALERP_MASK (1 << 4)

Definition at line 468 of file setup.h.

◆ CLK_SECJTAG_MASK

#define CLK_SECJTAG_MASK (1 << 0)

Definition at line 444 of file setup.h.

◆ CLK_SMMU3DNR_MASK

#define CLK_SMMU3DNR_MASK (1 << 7)

Definition at line 477 of file setup.h.

◆ CLK_SMMU_DRC_MASK

#define CLK_SMMU_DRC_MASK (1 << 9)

Definition at line 463 of file setup.h.

◆ CLK_SMMU_FD_MASK

#define CLK_SMMU_FD_MASK (1 << 10)

Definition at line 462 of file setup.h.

◆ CLK_SMMU_ISP_MASK

#define CLK_SMMU_ISP_MASK (1 << 8)

Definition at line 464 of file setup.h.

◆ CLK_SMMU_MCUISP_MASK

#define CLK_SMMU_MCUISP_MASK (1 << 13)

Definition at line 459 of file setup.h.

◆ CLK_SMMU_SCALERC_MASK

#define CLK_SMMU_SCALERC_MASK (1 << 11)

Definition at line 461 of file setup.h.

◆ CLK_SMMU_SCALERP_MASK

#define CLK_SMMU_SCALERP_MASK (1 << 12)

Definition at line 460 of file setup.h.

◆ CLK_SMMUDIS0_MASK

#define CLK_SMMUDIS0_MASK (1 << 5)

Definition at line 479 of file setup.h.

◆ CLK_SMMUDIS1_MASK

#define CLK_SMMUDIS1_MASK (1 << 6)

Definition at line 478 of file setup.h.

◆ CLK_SMMUFIMC_LITE0_MASK

#define CLK_SMMUFIMC_LITE0_MASK (1 << 11)

Definition at line 488 of file setup.h.

◆ CLK_SMMUFIMC_LITE1_MASK

#define CLK_SMMUFIMC_LITE1_MASK (1 << 12)

Definition at line 487 of file setup.h.

◆ CLK_SMMUFIMC_LITE2_MASK

#define CLK_SMMUFIMC_LITE2_MASK (1 << 20)

Definition at line 486 of file setup.h.

◆ CLK_SMMUG2D_MASK

#define CLK_SMMUG2D_MASK (1 << 7)

Definition at line 437 of file setup.h.

◆ CLK_SMMUGSCL0_MASK

#define CLK_SMMUGSCL0_MASK (1 << 7)

Definition at line 492 of file setup.h.

◆ CLK_SMMUGSCL1_MASK

#define CLK_SMMUGSCL1_MASK (1 << 8)

Definition at line 491 of file setup.h.

◆ CLK_SMMUGSCL2_MASK

#define CLK_SMMUGSCL2_MASK (1 << 9)

Definition at line 490 of file setup.h.

◆ CLK_SMMUGSCL3_MASK

#define CLK_SMMUGSCL3_MASK (1 << 10)

Definition at line 489 of file setup.h.

◆ CLK_SMMUJPEG_MASK

#define CLK_SMMUJPEG_MASK (1 << 7)

Definition at line 523 of file setup.h.

◆ CLK_SMMUMCU_IOP_MASK

#define CLK_SMMUMCU_IOP_MASK (1 << 26)

Definition at line 531 of file setup.h.

◆ CLK_SMMUMDMA1_MASK

#define CLK_SMMUMDMA1_MASK (1 << 9)

Definition at line 522 of file setup.h.

◆ CLK_SMMUMDMA_MASK

#define CLK_SMMUMDMA_MASK (1 << 5)

Definition at line 439 of file setup.h.

◆ CLK_SMMUMFCL_MASK

#define CLK_SMMUMFCL_MASK (1 << 1)

Definition at line 503 of file setup.h.

◆ CLK_SMMUMFCR_MASK

#define CLK_SMMUMFCR_MASK (1 << 2)

Definition at line 502 of file setup.h.

◆ CLK_SMMUODC_MASK

#define CLK_SMMUODC_MASK (1 << 4)

Definition at line 480 of file setup.h.

◆ CLK_SMMUROTATOR_MASK

#define CLK_SMMUROTATOR_MASK (1 << 6)

Definition at line 524 of file setup.h.

◆ CLK_SMMURTIC_MASK

#define CLK_SMMURTIC_MASK (1 << 11)

Definition at line 536 of file setup.h.

◆ CLK_SMMUSSS_MASK

#define CLK_SMMUSSS_MASK (1 << 6)

Definition at line 438 of file setup.h.

◆ CLK_SMMUTVX_MASK

#define CLK_SMMUTVX_MASK (1 << 9)

Definition at line 509 of file setup.h.

◆ CLK_SPDIF_MASK

#define CLK_SPDIF_MASK (1 << 26)

Definition at line 551 of file setup.h.

◆ CLK_SPI0_ISP_MASK

#define CLK_SPI0_ISP_MASK (1 << 12)

Definition at line 476 of file setup.h.

◆ CLK_SPI0_MASK

#define CLK_SPI0_MASK (1 << 16)

Definition at line 557 of file setup.h.

◆ CLK_SPI1_ISP_MASK

#define CLK_SPI1_ISP_MASK (1 << 13)

Definition at line 475 of file setup.h.

◆ CLK_SPI2_MASK

#define CLK_SPI2_MASK (1 << 18)

Definition at line 556 of file setup.h.

◆ CLK_SRC_CDREX_VAL

#define CLK_SRC_CDREX_VAL 0x00000001

Definition at line 190 of file setup.h.

◆ CLK_SRC_CORE0_VAL

#define CLK_SRC_CORE0_VAL 0x00000000

Definition at line 169 of file setup.h.

◆ CLK_SRC_CORE1_VAL

#define CLK_SRC_CORE1_VAL 0x100

Definition at line 172 of file setup.h.

◆ CLK_SRC_CPU_VAL

#define CLK_SRC_CPU_VAL

Value:

                                ((MUX_HPM_SEL << 20)    \
                                | (MUX_CPU_SEL << 16)  \
                                | (MUX_APLL_SEL))

Definition at line 84 of file setup.h.

◆ CLK_SRC_DISP1_0_VAL

#define CLK_SRC_DISP1_0_VAL 0x10006000

Definition at line 421 of file setup.h.

◆ CLK_SRC_FSYS0_VAL

#define CLK_SRC_FSYS0_VAL 0x33033300

Definition at line 153 of file setup.h.

◆ CLK_SRC_ISP_VAL

#define CLK_SRC_ISP_VAL 0x33366000

Definition at line 333 of file setup.h.

◆ CLK_SRC_KFC_VAL

#define CLK_SRC_KFC_VAL 0x00008001

Definition at line 285 of file setup.h.

◆ CLK_SRC_LEX_VAL [1/2]

#define CLK_SRC_LEX_VAL 0x0

Definition at line 406 of file setup.h.

◆ CLK_SRC_LEX_VAL [2/2]

#define CLK_SRC_LEX_VAL 0x0

Definition at line 406 of file setup.h.

◆ CLK_SRC_PERIC0_VAL

#define CLK_SRC_PERIC0_VAL

Value:

                                ((SPDIF_SEL << 28)      \
                                | (PWM_SEL << 24)       \
                                | (UART4_SEL << 20)     \
                                | (UART3_SEL << 16)     \
                                | (UART2_SEL << 12)     \
                                | (UART1_SEL << 8)      \
                                | (UART0_SEL << 4))

Definition at line 308 of file setup.h.

◆ CLK_SRC_PERIC1_VAL

#define CLK_SRC_PERIC1_VAL

Value:

                                ((SPI2_SEL << 28)       \
                                | (SPI1_SEL << 24)      \
                                | (SPI0_SEL << 20)      \
                                | (AUDIO2_SEL << 16)    \
                                | (AUDIO2_SEL << 12)    \
                                | (AUDIO2_SEL << 8))

Definition at line 325 of file setup.h.

◆ CLK_SRC_TOP0_VAL

#define CLK_SRC_TOP0_VAL 0x11101102

Definition at line 206 of file setup.h.

◆ CLK_SRC_TOP1_VAL

#define CLK_SRC_TOP1_VAL 0x00200000

Definition at line 207 of file setup.h.

◆ CLK_SRC_TOP2_VAL

#define CLK_SRC_TOP2_VAL 0x11101010

Definition at line 208 of file setup.h.

◆ CLK_SRC_TOP3_VAL

#define CLK_SRC_TOP3_VAL 0x11111111

Definition at line 209 of file setup.h.

◆ CLK_SRC_TOP4_VAL

#define CLK_SRC_TOP4_VAL 0x11110111

Definition at line 210 of file setup.h.

◆ CLK_SRC_TOP5_VAL

#define CLK_SRC_TOP5_VAL 0x11111111

Definition at line 211 of file setup.h.

◆ CLK_SRC_TOP6_VAL

#define CLK_SRC_TOP6_VAL 0x11110111

Definition at line 212 of file setup.h.

◆ CLK_SRC_TOP7_VAL

#define CLK_SRC_TOP7_VAL 0x00022200

Definition at line 213 of file setup.h.

◆ CLK_SSS_MASK

#define CLK_SSS_MASK (1 << 2)

Definition at line 442 of file setup.h.

◆ CLK_STOP_EN [1/2]

#define CLK_STOP_EN (1 << 0)

Definition at line 740 of file setup.h.

◆ CLK_STOP_EN [2/2]

#define CLK_STOP_EN (1 << 0)

Definition at line 740 of file setup.h.

◆ CLK_TZASC_DRBXR_MASK

#define CLK_TZASC_DRBXR_MASK (1 << 22)

Definition at line 587 of file setup.h.

◆ CLK_TZASC_DRBXW_MASK

#define CLK_TZASC_DRBXW_MASK (1 << 23)

Definition at line 586 of file setup.h.

◆ CLK_TZASC_XLBXR_MASK

#define CLK_TZASC_XLBXR_MASK (1 << 20)

Definition at line 589 of file setup.h.

◆ CLK_TZASC_XLBXW_MASK

#define CLK_TZASC_XLBXW_MASK (1 << 21)

Definition at line 588 of file setup.h.

◆ CLK_TZASC_XR1BXR_MASK

#define CLK_TZASC_XR1BXR_MASK (1 << 18)

Definition at line 591 of file setup.h.

◆ CLK_TZASC_XR1BXW_MASK

#define CLK_TZASC_XR1BXW_MASK (1 << 19)

Definition at line 590 of file setup.h.

◆ CLK_TZPC0_MASK

#define CLK_TZPC0_MASK (1 << 6)

Definition at line 579 of file setup.h.

◆ CLK_TZPC1_MASK

#define CLK_TZPC1_MASK (1 << 7)

Definition at line 578 of file setup.h.

◆ CLK_TZPC2_MASK

#define CLK_TZPC2_MASK (1 << 8)

Definition at line 577 of file setup.h.

◆ CLK_TZPC3_MASK

#define CLK_TZPC3_MASK (1 << 9)

Definition at line 576 of file setup.h.

◆ CLK_TZPC4_MASK

#define CLK_TZPC4_MASK (1 << 10)

Definition at line 575 of file setup.h.

◆ CLK_TZPC5_MASK

#define CLK_TZPC5_MASK (1 << 11)

Definition at line 574 of file setup.h.

◆ CLK_TZPC6_MASK

#define CLK_TZPC6_MASK (1 << 12)

Definition at line 573 of file setup.h.

◆ CLK_TZPC7_MASK

#define CLK_TZPC7_MASK (1 << 13)

Definition at line 572 of file setup.h.

◆ CLK_TZPC8_MASK

#define CLK_TZPC8_MASK (1 << 14)

Definition at line 571 of file setup.h.

◆ CLK_TZPC9_MASK

#define CLK_TZPC9_MASK (1 << 15)

Definition at line 570 of file setup.h.

◆ CLK_UART_ISP_MASK

#define CLK_UART_ISP_MASK (1 << 31)

Definition at line 450 of file setup.h.

◆ CLK_USBOTG_MASK

#define CLK_USBOTG_MASK (1 << 7)

Definition at line 539 of file setup.h.

◆ CLK_WDT_IOP_MASK

#define CLK_WDT_IOP_MASK (1 << 30)

Definition at line 530 of file setup.h.

◆ CLK_WDT_ISP_MASK

#define CLK_WDT_ISP_MASK (1 << 30)

Definition at line 451 of file setup.h.

◆ CMD_DEFAULT_LPDDR3

#define CMD_DEFAULT_LPDDR3 0xF

Definition at line 716 of file setup.h.

◆ CMD_DEFAULT_OFFSET

#define CMD_DEFAULT_OFFSET 0

Definition at line 717 of file setup.h.

◆ COPY_RATIO

#define COPY_RATIO 0x0

Definition at line 162 of file setup.h.

◆ CPLL_CON0_LOCKED

#define CPLL_CON0_LOCKED (1 << 29)

Definition at line 259 of file setup.h.

◆ CPLL_CON1_VAL

#define CPLL_CON1_VAL (0x0020f300)

Definition at line 43 of file setup.h.

◆ CPLL_LOCK_VAL

#define CPLL_LOCK_VAL (0x190)

Definition at line 227 of file setup.h.

◆ CTRL_ATGATE

#define CTRL_ATGATE (1 << 6)

Definition at line 773 of file setup.h.

◆ CTRL_BSTLEN_OFFSET

#define CTRL_BSTLEN_OFFSET 8

Definition at line 713 of file setup.h.

◆ CTRL_DLL_ON

#define CTRL_DLL_ON (1 << 5)

Definition at line 641 of file setup.h.

◆ CTRL_FORCE_MASK

#define CTRL_FORCE_MASK (0x7F << 8)

Definition at line 642 of file setup.h.

◆ CTRL_GATEDURADJ_MASK

#define CTRL_GATEDURADJ_MASK (0xf << 20)

Definition at line 620 of file setup.h.

◆ CTRL_LOCK_COARSE_MASK

#define CTRL_LOCK_COARSE_MASK (0x7F << 10)

Definition at line 643 of file setup.h.

◆ CTRL_OFFSETD_RESET_VAL

#define CTRL_OFFSETD_RESET_VAL 0x8

Definition at line 645 of file setup.h.

◆ CTRL_OFFSETD_VAL

#define CTRL_OFFSETD_VAL 0x7F

Definition at line 646 of file setup.h.

◆ CTRL_OFFSETR0

#define CTRL_OFFSETR0 0x7F

Definition at line 648 of file setup.h.

◆ CTRL_OFFSETR1

#define CTRL_OFFSETR1 0x7F

Definition at line 649 of file setup.h.

◆ CTRL_OFFSETR2

#define CTRL_OFFSETR2 0x7F

Definition at line 650 of file setup.h.

◆ CTRL_OFFSETR3

#define CTRL_OFFSETR3 0x7F

Definition at line 651 of file setup.h.

◆ CTRL_OFFSETW0

#define CTRL_OFFSETW0 0x7F

Definition at line 658 of file setup.h.

◆ CTRL_OFFSETW1

#define CTRL_OFFSETW1 0x7F

Definition at line 659 of file setup.h.

◆ CTRL_OFFSETW2

#define CTRL_OFFSETW2 0x7F

Definition at line 660 of file setup.h.

◆ CTRL_OFFSETW3

#define CTRL_OFFSETW3 0x7F

Definition at line 661 of file setup.h.

◆ CTRL_PULLD_DQS

#define CTRL_PULLD_DQS 0xF

Definition at line 669 of file setup.h.

◆ CTRL_PULLD_DQS_OFFSET

#define CTRL_PULLD_DQS_OFFSET 0

Definition at line 670 of file setup.h.

◆ CTRL_RDLAT_OFFSET

#define CTRL_RDLAT_OFFSET 0

Definition at line 714 of file setup.h.

◆ CTRL_RDLVL_DATA_ENABLE

#define CTRL_RDLVL_DATA_ENABLE (1 << 1)

Definition at line 688 of file setup.h.

◆ CTRL_RDLVL_GATE_DISABLE

#define CTRL_RDLVL_GATE_DISABLE 0

Definition at line 686 of file setup.h.

◆ CTRL_RDLVL_GATE_ENABLE

#define CTRL_RDLVL_GATE_ENABLE 1

Definition at line 685 of file setup.h.

◆ CTRL_SHGATE

#define CTRL_SHGATE (1 << 8)

Definition at line 615 of file setup.h.

◆ CTRL_START [1/2]

#define CTRL_START (1 << 6)

Definition at line 733 of file setup.h.

◆ CTRL_START [2/2]

#define CTRL_START (1 << 6)

Definition at line 733 of file setup.h.

◆ DA_0_DS_OFFSET

#define DA_0_DS_OFFSET 16

Definition at line 782 of file setup.h.

◆ DA_1_DS_OFFSET

#define DA_1_DS_OFFSET 19

Definition at line 781 of file setup.h.

◆ DA_2_DS_OFFSET

#define DA_2_DS_OFFSET 22

Definition at line 780 of file setup.h.

◆ DA_3_DS_OFFSET

#define DA_3_DS_OFFSET 25

Definition at line 779 of file setup.h.

◆ DATA_MASK

#define DATA_MASK 0xFFFFF

Definition at line 13 of file setup.h.

◆ DECPROTXSET

#define DECPROTXSET 0xFF

Definition at line 605 of file setup.h.

◆ DFI_INIT_COMPLETE

#define DFI_INIT_COMPLETE (1 << 3)

Definition at line 755 of file setup.h.

◆ DFI_INIT_COMPLETE_CH1

#define DFI_INIT_COMPLETE_CH1 (1 << 3)

Definition at line 136 of file setup.h.

◆ DFI_INIT_COMPLETE_CHO

#define DFI_INIT_COMPLETE_CHO (1 << 2)

Definition at line 135 of file setup.h.

◆ DFI_INIT_START [1/2]

#define DFI_INIT_START (1 << 28)

Definition at line 737 of file setup.h.

◆ DFI_INIT_START [2/2]

#define DFI_INIT_START (1 << 28)

Definition at line 737 of file setup.h.

◆ DIRECT_CMD_BANK_SHIFT

#define DIRECT_CMD_BANK_SHIFT 16

Definition at line 695 of file setup.h.

◆ DIRECT_CMD_CHANNEL_SHIFT

#define DIRECT_CMD_CHANNEL_SHIFT 28

Definition at line 693 of file setup.h.

◆ DIRECT_CMD_CHIP_SHIFT

#define DIRECT_CMD_CHIP_SHIFT 20

Definition at line 694 of file setup.h.

◆ DIRECT_CMD_MRS1

#define DIRECT_CMD_MRS1 0x71C00

Definition at line 697 of file setup.h.

◆ DIRECT_CMD_MRS2

#define DIRECT_CMD_MRS2 0x10BFC

Definition at line 698 of file setup.h.

◆ DIRECT_CMD_MRS3

#define DIRECT_CMD_MRS3 0x0050C

Definition at line 699 of file setup.h.

◆ DIRECT_CMD_MRS4

#define DIRECT_CMD_MRS4 0x00868

Definition at line 700 of file setup.h.

◆ DIRECT_CMD_MRS5

#define DIRECT_CMD_MRS5 0x00C04

Definition at line 701 of file setup.h.

◆ DIRECT_CMD_NOP

#define DIRECT_CMD_NOP 0x07000000

Definition at line 690 of file setup.h.

◆ DIRECT_CMD_PALL

#define DIRECT_CMD_PALL 0x01000000

Definition at line 691 of file setup.h.

◆ DIRECT_CMD_REFA

#define DIRECT_CMD_REFA (5 << 24)

Definition at line 696 of file setup.h.

◆ DIRECT_CMD_ZQINIT

#define DIRECT_CMD_ZQINIT 0x0a000000

Definition at line 692 of file setup.h.

◆ DISABLE_BIT

#define DISABLE_BIT 0x0

Definition at line 16 of file setup.h.

◆ DIV_MAU_VAL

#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)

Definition at line 519 of file setup.h.

◆ DLL_DESKEW_EN

#define DLL_DESKEW_EN (1 << 12)

Definition at line 625 of file setup.h.

◆ DMC_AREF_EN

#define DMC_AREF_EN (1 << 5)

Definition at line 735 of file setup.h.

◆ DMC_CHIP_MASK_1GB

#define DMC_CHIP_MASK_1GB 0x7c0

Definition at line 747 of file setup.h.

◆ DMC_CHIP_MASK_256MB

#define DMC_CHIP_MASK_256MB 0x7f0

Definition at line 745 of file setup.h.

◆ DMC_CHIP_MASK_2GB

#define DMC_CHIP_MASK_2GB 0x780

Definition at line 748 of file setup.h.

◆ DMC_CHIP_MASK_4GB

#define DMC_CHIP_MASK_4GB 0x700

Definition at line 749 of file setup.h.

◆ DMC_CHIP_MASK_512MB

#define DMC_CHIP_MASK_512MB 0x7e0

Definition at line 746 of file setup.h.

◆ DMC_CONCONTROL_AREF_EN_DISABLE

#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)

Definition at line 147 of file setup.h.

◆ DMC_CONCONTROL_DFI_INIT_START_DISABLE

#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)

Definition at line 150 of file setup.h.

◆ DMC_CONCONTROL_EMPTY

#define DMC_CONCONTROL_EMPTY (1 << 8)

Definition at line 736 of file setup.h.

◆ DMC_CONCONTROL_IO_PD_CON

#define DMC_CONCONTROL_IO_PD_CON ( x ) (x << 6)

Definition at line 158 of file setup.h.

◆ DMC_CONCONTROL_IO_PD_CON_DISABLE

#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)

Definition at line 146 of file setup.h.

◆ DMC_CONCONTROL_RD_FETCH_DISABLE

#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)

Definition at line 148 of file setup.h.

◆ DMC_CONCONTROL_RESET_VAL

#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000

Definition at line 130 of file setup.h.

◆ DMC_CONCONTROL_TIMEOUT_LEVEL0

#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)

Definition at line 149 of file setup.h.

◆ DMC_CTRL_SHGATE

#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */

Definition at line 772 of file setup.h.

◆ DMC_INTERNAL_CG

#define DMC_INTERNAL_CG

Value:

(MEMIF_CG_EN | SCG_CG_EN | \

BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)

BUSIF_RD_CG_EN

#define BUSIF_RD_CG_EN

Definition: setup.h:764

SCG_CG_EN

#define SCG_CG_EN

Definition: setup.h:762

MEMIF_CG_EN

#define MEMIF_CG_EN

Definition: setup.h:761

Definition at line 765 of file setup.h.

◆ DMC_MEMBASECONFIG0_VAL

#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)

Definition at line 124 of file setup.h.

◆ DMC_MEMBASECONFIG1_VAL

#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)

Definition at line 125 of file setup.h.

◆ DMC_MEMCONFIG_CHIP_MAP_SPLIT

#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)

Definition at line 117 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_BANK_8

#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)

Definition at line 122 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_COL_10

#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)

Definition at line 118 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED

#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12)

Definition at line 116 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_ROW_14

#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)

Definition at line 119 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_ROW_15

#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)

Definition at line 120 of file setup.h.

◆ DMC_MEMCONFIGx_CHIP_ROW_16

#define DMC_MEMCONFIGx_CHIP_ROW_16 (4 << 4)

Definition at line 121 of file setup.h.

◆ DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE

#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE ( x ) (x << 6)

Definition at line 94 of file setup.h.

◆ DMC_MEMCONTROL_BL_4

#define DMC_MEMCONTROL_BL_4 (2 << 20)

Definition at line 106 of file setup.h.

◆ DMC_MEMCONTROL_BL_8

#define DMC_MEMCONTROL_BL_8 (3 << 20)

Definition at line 105 of file setup.h.

◆ DMC_MEMCONTROL_CLK_STOP_DISABLE

#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)

Definition at line 89 of file setup.h.

◆ DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE

#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)

Definition at line 91 of file setup.h.

◆ DMC_MEMCONTROL_DPWRDN_DISABLE

#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)

Definition at line 90 of file setup.h.

◆ DMC_MEMCONTROL_DSREF_DISABLE

#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)

Definition at line 92 of file setup.h.

◆ DMC_MEMCONTROL_DSREF_ENABLE

#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)

Definition at line 93 of file setup.h.

◆ DMC_MEMCONTROL_MEM_TYPE_DDR3

#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)

Definition at line 97 of file setup.h.

◆ DMC_MEMCONTROL_MEM_TYPE_LPDDR2

#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)

Definition at line 98 of file setup.h.

◆ DMC_MEMCONTROL_MEM_TYPE_LPDDR3

#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)

Definition at line 96 of file setup.h.

◆ DMC_MEMCONTROL_MEM_WIDTH_32BIT

#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)

Definition at line 100 of file setup.h.

◆ DMC_MEMCONTROL_MRR_BYTE_15_8

#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)

Definition at line 111 of file setup.h.

◆ DMC_MEMCONTROL_MRR_BYTE_23_16

#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)

Definition at line 112 of file setup.h.

◆ DMC_MEMCONTROL_MRR_BYTE_31_24

#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)

Definition at line 113 of file setup.h.

◆ DMC_MEMCONTROL_MRR_BYTE_7_0

#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)

Definition at line 110 of file setup.h.

◆ DMC_MEMCONTROL_NUM_CHIP_1

#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)

Definition at line 102 of file setup.h.

◆ DMC_MEMCONTROL_NUM_CHIP_2

#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)

Definition at line 103 of file setup.h.

◆ DMC_MEMCONTROL_PZQ_DISABLE

#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)

Definition at line 108 of file setup.h.

◆ DMC_MEMCONTROL_VAL

#define DMC_MEMCONTROL_VAL 0x00312700

Definition at line 739 of file setup.h.

◆ DMC_PRECHCONFIG_VAL

#define DMC_PRECHCONFIG_VAL 0xFF000000

Definition at line 127 of file setup.h.

◆ DMC_PWRDNCONFIG_VAL

#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF

Definition at line 128 of file setup.h.

◆ DPLL_CON1_VAL

#define DPLL_CON1_VAL (0x0020f300)

Definition at line 46 of file setup.h.

◆ DPLL_LOCK_VAL

#define DPLL_LOCK_VAL (0x190)

Definition at line 229 of file setup.h.

◆ DPWRDN_EN [1/2]

#define DPWRDN_EN (1 << 1)

Definition at line 741 of file setup.h.

◆ DPWRDN_EN [2/2]

#define DPWRDN_EN (1 << 1)

Definition at line 741 of file setup.h.

◆ DREX_PAUSE_EN

#define DREX_PAUSE_EN (1 << 0)

Definition at line 631 of file setup.h.

◆ DSREF_EN [1/2]

#define DSREF_EN (1 << 5)

Definition at line 742 of file setup.h.

◆ DSREF_EN [2/2]

#define DSREF_EN (1 << 5)

Definition at line 742 of file setup.h.

◆ EMPTY

#define EMPTY (1 << 8)

Definition at line 132 of file setup.h.

◆ ENABLE_BIT

#define ENABLE_BIT 0x1

Definition at line 15 of file setup.h.

◆ EPLL_CON0_LOCKED

#define EPLL_CON0_LOCKED (1 << 29)

Definition at line 260 of file setup.h.

◆ EPLL_CON1_VAL

#define EPLL_CON1_VAL 0x00000000

Definition at line 52 of file setup.h.

◆ EPLL_CON2_VAL

#define EPLL_CON2_VAL 0x00000080

Definition at line 53 of file setup.h.

◆ EPLL_LOCK_VAL

#define EPLL_LOCK_VAL (0x2328)

Definition at line 241 of file setup.h.

◆ FOUTBPLL

#define FOUTBPLL 2

Definition at line 194 of file setup.h.

◆ FP_RESYNC

#define FP_RESYNC (1 << 3)

Definition at line 732 of file setup.h.

◆ FP_RSYNC

#define FP_RSYNC (1 << 3) /* Force DLL resynchronization */

Definition at line 774 of file setup.h.

◆ GPLL_CON0_LOCKED

#define GPLL_CON0_LOCKED (1 << 29)

Definition at line 261 of file setup.h.

◆ GPLL_CON1_VAL

#define GPLL_CON1_VAL (NOT_AVAILABLE)

Definition at line 49 of file setup.h.

◆ GPLL_LOCK_VAL

#define GPLL_LOCK_VAL NOT_AVAILABLE

Definition at line 231 of file setup.h.

◆ HPM_RATIO

#define HPM_RATIO 0x2

Definition at line 161 of file setup.h.

◆ HPM_SEL_SCLK_MPLL

#define HPM_SEL_SCLK_MPLL (1 << 21)

Definition at line 254 of file setup.h.

◆ IMP_OUTPUT_DRV_30_OHM

#define IMP_OUTPUT_DRV_30_OHM 0x7

Definition at line 778 of file setup.h.

◆ IMP_OUTPUT_DRV_40_OHM

#define IMP_OUTPUT_DRV_40_OHM 0x5

Definition at line 777 of file setup.h.

◆ IMPEDANCE_30_OHM

#define IMPEDANCE_30_OHM 7

Definition at line 707 of file setup.h.

◆ IMPEDANCE_34_OHM

#define IMPEDANCE_34_OHM 6

Definition at line 706 of file setup.h.

◆ IMPEDANCE_40_OHM

#define IMPEDANCE_40_OHM 5

Definition at line 705 of file setup.h.

◆ IMPEDANCE_48_OHM

#define IMPEDANCE_48_OHM 4

Definition at line 704 of file setup.h.

◆ INIT_DESKEW_EN

#define INIT_DESKEW_EN (1 << 6)

Definition at line 624 of file setup.h.

◆ IPLL_CON1_VAL

#define IPLL_CON1_VAL 0x00000080

Definition at line 70 of file setup.h.

◆ IPLL_LOCK_VAL

#define IPLL_LOCK_VAL (0x320)

Definition at line 233 of file setup.h.

◆ KPLL_CON1_VAL

#define KPLL_CON1_VAL 0x200000

Definition at line 73 of file setup.h.

◆ KPLL_FOUT

#define KPLL_FOUT (1 << 0)

Definition at line 32 of file setup.h.

◆ KPLL_LOCK_VAL

#define KPLL_LOCK_VAL (0x258)

Definition at line 235 of file setup.h.

◆ LONG_CALIBRATION

#define LONG_CALIBRATION (ZQ_LONG_CALIBRATION << ZQ_MANUAL_MODE_OFFSET)

Definition at line 683 of file setup.h.

◆ LPDDR3PHY_CTRL_PHY_RESET

#define LPDDR3PHY_CTRL_PHY_RESET (1 << 0)

Definition at line 607 of file setup.h.

◆ LPDDR3PHY_CTRL_PHY_RESET_OFF

#define LPDDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)

Definition at line 608 of file setup.h.

◆ MEM_TERM_EN

#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */

Definition at line 770 of file setup.h.

◆ MEMCONFIG_VAL

#define MEMCONFIG_VAL 0x1323

Definition at line 751 of file setup.h.

◆ MEMIF_CG_EN

#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */

Definition at line 761 of file setup.h.

◆ MMC2_PRE_RATIO_MASK

#define MMC2_PRE_RATIO_MASK 0xff

Definition at line 393 of file setup.h.

◆ MMC2_PRE_RATIO_OFFSET

#define MMC2_PRE_RATIO_OFFSET 8

Definition at line 395 of file setup.h.

◆ MMC2_PRE_RATIO_VAL

#define MMC2_PRE_RATIO_VAL 0x9

Definition at line 394 of file setup.h.

◆ MMC2_RATIO_MASK

#define MMC2_RATIO_MASK 0xf

Definition at line 389 of file setup.h.

◆ MMC2_RATIO_OFFSET

#define MMC2_RATIO_OFFSET 0

Definition at line 391 of file setup.h.

◆ MMC2_RATIO_VAL

#define MMC2_RATIO_VAL 0x3

Definition at line 390 of file setup.h.

◆ MMC3_PRE_RATIO_MASK

#define MMC3_PRE_RATIO_MASK 0xff

Definition at line 401 of file setup.h.

◆ MMC3_PRE_RATIO_OFFSET

#define MMC3_PRE_RATIO_OFFSET 24

Definition at line 403 of file setup.h.

◆ MMC3_PRE_RATIO_VAL

#define MMC3_PRE_RATIO_VAL 0x0

Definition at line 402 of file setup.h.

◆ MMC3_RATIO_MASK

#define MMC3_RATIO_MASK 0xf

Definition at line 397 of file setup.h.

◆ MMC3_RATIO_OFFSET

#define MMC3_RATIO_OFFSET 16

Definition at line 399 of file setup.h.

◆ MMC3_RATIO_VAL

#define MMC3_RATIO_VAL 0x1

Definition at line 398 of file setup.h.

◆ MPLL_CON0_LOCKED

#define MPLL_CON0_LOCKED (1 << 29)

Definition at line 257 of file setup.h.

◆ MPLL_CON1_VAL

#define MPLL_CON1_VAL (0x0020f300)

Definition at line 40 of file setup.h.

◆ MPLL_LOCK_VAL

#define MPLL_LOCK_VAL (0x258)

Definition at line 223 of file setup.h.

◆ MPLL_SEL_MOUT_MPLLFOUT

#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)

Definition at line 247 of file setup.h.

◆ MUX_APLL_SEL

#define MUX_APLL_SEL 1

Definition at line 82 of file setup.h.

◆ MUX_APLL_SEL_MASK

#define MUX_APLL_SEL_MASK (1 << 0)

Definition at line 245 of file setup.h.

◆ MUX_BPLL_SEL_FOUTBPLL

#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)

Definition at line 192 of file setup.h.

◆ MUX_BPLL_SEL_MASK

#define MUX_BPLL_SEL_MASK (1 << 0)

Definition at line 252 of file setup.h.

◆ MUX_CPLL_SEL_MASK

#define MUX_CPLL_SEL_MASK (1 << 8)

Definition at line 248 of file setup.h.

◆ MUX_CPU_SEL

#define MUX_CPU_SEL 0

Definition at line 81 of file setup.h.

◆ MUX_EPLL_SEL_MASK

#define MUX_EPLL_SEL_MASK (1 << 12)

Definition at line 249 of file setup.h.

◆ MUX_GPLL_SEL_MASK

#define MUX_GPLL_SEL_MASK (1 << 28)

Definition at line 251 of file setup.h.

◆ MUX_HPM_SEL

#define MUX_HPM_SEL 1

Definition at line 80 of file setup.h.

◆ MUX_HPM_SEL_MASK

#define MUX_HPM_SEL_MASK (1 << 20)

Definition at line 253 of file setup.h.

◆ MUX_MCLK_CDR_MSPLL

#define MUX_MCLK_CDR_MSPLL (1 << 4)

Definition at line 191 of file setup.h.

◆ MUX_MPLL_SEL_MASK

#define MUX_MPLL_SEL_MASK (1 << 8)

Definition at line 246 of file setup.h.

◆ MUX_VPLL_SEL_MASK

#define MUX_VPLL_SEL_MASK (1 << 16)

Definition at line 250 of file setup.h.

◆ NOT_AVAILABLE

#define NOT_AVAILABLE 0

Definition at line 12 of file setup.h.

◆ P0_CMD_EN

#define P0_CMD_EN (1 << 14)

Definition at line 613 of file setup.h.

◆ PCM0_RATIO

#define PCM0_RATIO 0x3

Definition at line 518 of file setup.h.

◆ PCM1_RATIO

#define PCM1_RATIO 0x3

Definition at line 368 of file setup.h.

◆ PCM2_RATIO

#define PCM2_RATIO 0x3

Definition at line 367 of file setup.h.

◆ PHY_CON0_RESET_VAL

#define PHY_CON0_RESET_VAL 0x17020a40

Definition at line 612 of file setup.h.

◆ PHY_CON0_VAL

#define PHY_CON0_VAL 0x17021A00

Definition at line 636 of file setup.h.

◆ PHY_CON12_RESET_VAL

#define PHY_CON12_RESET_VAL 0x10100070

Definition at line 638 of file setup.h.

◆ PHY_CON12_VAL

#define PHY_CON12_VAL 0x10107F50

Definition at line 639 of file setup.h.

◆ PHY_CON14_RESET_VAL

#define PHY_CON14_RESET_VAL 0x001F0000

Definition at line 668 of file setup.h.

◆ PHY_CON16_RESET_VAL

#define PHY_CON16_RESET_VAL 0x08000304

Definition at line 673 of file setup.h.

◆ PHY_CON1_RESET_VAL

#define PHY_CON1_RESET_VAL 0x09210100

Definition at line 617 of file setup.h.

◆ PHY_CON2_RESET_VAL

#define PHY_CON2_RESET_VAL 0x00010004

Definition at line 623 of file setup.h.

◆ PHY_CON31_RESET_VAL

#define PHY_CON31_RESET_VAL 0x0

Definition at line 727 of file setup.h.

◆ PHY_CON31_VAL

#define PHY_CON31_VAL 0x0C183060

Definition at line 723 of file setup.h.

◆ PHY_CON32_RESET_VAL

#define PHY_CON32_RESET_VAL 0x0

Definition at line 728 of file setup.h.

◆ PHY_CON32_VAL

#define PHY_CON32_VAL 0x60C18306

Definition at line 724 of file setup.h.

◆ PHY_CON33_RESET_VAL

#define PHY_CON33_RESET_VAL 0x0

Definition at line 729 of file setup.h.

◆ PHY_CON33_VAL

#define PHY_CON33_VAL 0x00000030

Definition at line 725 of file setup.h.

◆ PHY_CON39_VAL_30_OHM

#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF

Definition at line 711 of file setup.h.

◆ PHY_CON39_VAL_34_OHM

#define PHY_CON39_VAL_34_OHM 0x0DB60DB6

Definition at line 710 of file setup.h.

◆ PHY_CON39_VAL_40_OHM

#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D

Definition at line 709 of file setup.h.

◆ PHY_CON39_VAL_48_OHM

#define PHY_CON39_VAL_48_OHM 0x09240924

Definition at line 708 of file setup.h.

◆ PHY_CON42_CTRL_BSTLEN_SHIFT

#define PHY_CON42_CTRL_BSTLEN_SHIFT 8

Definition at line 788 of file setup.h.

◆ PHY_CON42_CTRL_RDLAT_SHIFT

#define PHY_CON42_CTRL_RDLAT_SHIFT 0

Definition at line 789 of file setup.h.

◆ PHY_CON4_RESET_VAL

#define PHY_CON4_RESET_VAL 0x08080808

Definition at line 656 of file setup.h.

◆ PHY_CON4_VAL

#define PHY_CON4_VAL

Value:

                                (CTRL_OFFSETR0 << 0 | \
                                CTRL_OFFSETR1 << 8 | \
                                CTRL_OFFSETR2 << 16 | \
                                CTRL_OFFSETR3 << 24)

Definition at line 652 of file setup.h.

◆ PHY_CON6_RESET_VAL

#define PHY_CON6_RESET_VAL 0x08080808

Definition at line 666 of file setup.h.

◆ PHY_CON6_VAL

#define PHY_CON6_VAL

Value:

                                (CTRL_OFFSETW0 << 0 | \
                                CTRL_OFFSETW1 << 8 | \
                                CTRL_OFFSETW2 << 16 | \
                                CTRL_OFFSETW3 << 24)

Definition at line 662 of file setup.h.

◆ PHY_CONTROL0_RESET_VAL

#define PHY_CONTROL0_RESET_VAL 0x0

Definition at line 769 of file setup.h.

◆ PHY_TERM_EN

#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */

Definition at line 771 of file setup.h.

◆ PLL_LOCKED

#define PLL_LOCKED (1 << 29)

Definition at line 255 of file setup.h.

◆ PRECHCONFIG_DEFAULT_VAL

#define PRECHCONFIG_DEFAULT_VAL 0xFF000000

Definition at line 752 of file setup.h.

◆ PWM_RATIO

#define PWM_RATIO 8

Definition at line 344 of file setup.h.

◆ PWM_SEL

#define PWM_SEL 3

Definition at line 301 of file setup.h.

◆ PWRDNCONFIG_DEFAULT_VAL

#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF

Definition at line 753 of file setup.h.

◆ R0SIZE

#define R0SIZE 0x0

Definition at line 599 of file setup.h.

◆ RDLVL_COMPLETE_CH1

#define RDLVL_COMPLETE_CH1 (1 << 15)

Definition at line 139 of file setup.h.

◆ RDLVL_COMPLETE_CHO

#define RDLVL_COMPLETE_CHO (1 << 14)

Definition at line 138 of file setup.h.

◆ RDLVL_EN

#define RDLVL_EN (1 << 25)

Definition at line 627 of file setup.h.

◆ RDLVL_GATE_EN

#define RDLVL_GATE_EN (1 << 24)

Definition at line 626 of file setup.h.

◆ RDLVL_INCR_ADJ

#define RDLVL_INCR_ADJ (0x1 << 16)

Definition at line 628 of file setup.h.

◆ RDLVL_PASS_ADJ_OFFSET

#define RDLVL_PASS_ADJ_OFFSET 16

Definition at line 619 of file setup.h.

◆ RDLVL_PASS_ADJ_VAL

#define RDLVL_PASS_ADJ_VAL 0x6

Definition at line 618 of file setup.h.

◆ READ_LEVELLING_DDR3

#define READ_LEVELLING_DDR3 0x0100

Definition at line 621 of file setup.h.

◆ RPLL_CON1_VAL

#define RPLL_CON1_VAL 0x00000000

Definition at line 60 of file setup.h.

◆ RPLL_CON2_VAL

#define RPLL_CON2_VAL 0x00000080

Definition at line 61 of file setup.h.

◆ RPLL_LOCK_VAL

#define RPLL_LOCK_VAL (0x2328)

Definition at line 239 of file setup.h.

◆ SCG_CG_EN

#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */

Definition at line 762 of file setup.h.

◆ SCLK_DIV_ISP_VAL

#define SCLK_DIV_ISP_VAL

Value:

(SPI1_ISP_RATIO << 12) \

| (SPI0_ISP_RATIO << 0)

SPI1_ISP_RATIO

#define SPI1_ISP_RATIO

Definition: setup.h:339

SPI0_ISP_RATIO

#define SPI0_ISP_RATIO

Definition: setup.h:338

Definition at line 340 of file setup.h.

◆ SCLK_MPWM_ISP_MASK

#define SCLK_MPWM_ISP_MASK (1 << 0)

Definition at line 506 of file setup.h.

◆ set_pll

#define set_pll	(	mdiv,
		pdiv,
		sdiv
	)	(1<<31 \| mdiv<<16 \| pdiv<<8 \| sdiv)

Definition at line 76 of file setup.h.

◆ SL_DLL_DYN_CON_EN

#define SL_DLL_DYN_CON_EN (1 << 1)

Definition at line 731 of file setup.h.

◆ SPDIF_SEL

#define SPDIF_SEL 1

Definition at line 300 of file setup.h.

◆ SPI0_ISP_RATIO

#define SPI0_ISP_RATIO 0xf

Definition at line 338 of file setup.h.

◆ SPI0_PRE_RATIO

#define SPI0_PRE_RATIO 0x3

Definition at line 383 of file setup.h.

◆ SPI0_RATIO

#define SPI0_RATIO 0x1

Definition at line 361 of file setup.h.

◆ SPI0_SEL

#define SPI0_SEL 3

Definition at line 318 of file setup.h.

◆ SPI1_ISP_RATIO

#define SPI1_ISP_RATIO 0xf

Definition at line 339 of file setup.h.

◆ SPI1_PRE_RATIO

#define SPI1_PRE_RATIO 0x3

Definition at line 382 of file setup.h.

◆ SPI1_RATIO

#define SPI1_RATIO 0x1

Definition at line 360 of file setup.h.

◆ SPI1_SEL

#define SPI1_SEL 3

Definition at line 319 of file setup.h.

◆ SPI2_PRE_RATIO

#define SPI2_PRE_RATIO 0x3

Definition at line 381 of file setup.h.

◆ SPI2_RATIO

#define SPI2_RATIO 0x1

Definition at line 359 of file setup.h.

◆ SPI2_SEL

#define SPI2_SEL 3

Definition at line 320 of file setup.h.

◆ SPLL_CON1_VAL

#define SPLL_CON1_VAL 0x0020f300

Definition at line 67 of file setup.h.

◆ SPLL_LOCK_VAL

#define SPLL_LOCK_VAL (0x320)

Definition at line 237 of file setup.h.

◆ SRC_KFC_HPM_SEL

#define SRC_KFC_HPM_SEL (1 << 15)

Definition at line 282 of file setup.h.

◆ T_WRDATA_EN

#define T_WRDATA_EN 0x7

Definition at line 718 of file setup.h.

◆ T_WRDATA_EN_DDR3

#define T_WRDATA_EN_DDR3 0x8 /* FIXME(dhendrix): 6 for DDR3? see T_wrdata_en */

Definition at line 719 of file setup.h.

◆ T_WRDATA_EN_MASK

#define T_WRDATA_EN_MASK 0x1f

Definition at line 721 of file setup.h.

◆ T_WRDATA_EN_OFFSET

#define T_WRDATA_EN_OFFSET 16

Definition at line 720 of file setup.h.

◆ TOP2_VAL

#define TOP2_VAL 0x0110000

Definition at line 264 of file setup.h.

◆ TZPC0_BASE

#define TZPC0_BASE 0x10100000

Definition at line 20 of file setup.h.

◆ TZPC1_BASE

#define TZPC1_BASE 0x10110000

Definition at line 21 of file setup.h.

◆ TZPC2_BASE

#define TZPC2_BASE 0x10120000

Definition at line 22 of file setup.h.

◆ TZPC3_BASE

#define TZPC3_BASE 0x10130000

Definition at line 23 of file setup.h.

◆ TZPC4_BASE

#define TZPC4_BASE 0x10140000

Definition at line 24 of file setup.h.

◆ TZPC5_BASE

#define TZPC5_BASE 0x10150000

Definition at line 25 of file setup.h.

◆ TZPC6_BASE

#define TZPC6_BASE 0x10160000

Definition at line 26 of file setup.h.

◆ TZPC7_BASE

#define TZPC7_BASE 0x10170000

Definition at line 27 of file setup.h.

◆ TZPC8_BASE

#define TZPC8_BASE 0x10180000

Definition at line 28 of file setup.h.

◆ TZPC9_BASE

#define TZPC9_BASE 0x10190000

Definition at line 29 of file setup.h.

◆ UART0_RATIO

#define UART0_RATIO 9

Definition at line 349 of file setup.h.

◆ UART0_SEL

#define UART0_SEL 3

Definition at line 306 of file setup.h.

◆ UART1_RATIO

#define UART1_RATIO 9

Definition at line 348 of file setup.h.

◆ UART1_SEL

#define UART1_SEL 3

Definition at line 305 of file setup.h.

◆ UART2_RATIO

#define UART2_RATIO 9

Definition at line 347 of file setup.h.

◆ UART2_SEL

#define UART2_SEL 3

Definition at line 304 of file setup.h.

◆ UART3_RATIO

#define UART3_RATIO 9

Definition at line 346 of file setup.h.

◆ UART3_SEL

#define UART3_SEL 3

Definition at line 303 of file setup.h.

◆ UART4_RATIO

#define UART4_RATIO 9

Definition at line 345 of file setup.h.

◆ UART4_SEL

#define UART4_SEL 3

Definition at line 302 of file setup.h.

◆ VPLL_CON0_LOCKED

#define VPLL_CON0_LOCKED (1 << 29)

Definition at line 262 of file setup.h.

◆ VPLL_CON1_VAL

#define VPLL_CON1_VAL 0x0020f300

Definition at line 56 of file setup.h.

◆ VPLL_CON2_VAL

#define VPLL_CON2_VAL NOT_AVAILABLE

Definition at line 57 of file setup.h.

◆ VPLL_LOCK_VAL

#define VPLL_LOCK_VAL (0x258)

Definition at line 243 of file setup.h.

◆ ZQ_CLK_DIV_EN

#define ZQ_CLK_DIV_EN (1 << 18)

Definition at line 676 of file setup.h.

◆ ZQ_CLK_EN

#define ZQ_CLK_EN (1 << 27)

Definition at line 675 of file setup.h.

◆ ZQ_DONE

#define ZQ_DONE (1 << 0)

Definition at line 680 of file setup.h.

◆ ZQ_LONG_CALIBRATION

#define ZQ_LONG_CALIBRATION 0x1

Definition at line 678 of file setup.h.

◆ ZQ_MANUAL_MODE_OFFSET

#define ZQ_MANUAL_MODE_OFFSET 2

Definition at line 677 of file setup.h.

◆ ZQ_MANUAL_STR

#define ZQ_MANUAL_STR (1 << 1)

Definition at line 679 of file setup.h.

◆ ZQ_MODE_DDS_OFFSET

#define ZQ_MODE_DDS_OFFSET 24

Definition at line 681 of file setup.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
SETUP_ERR_OK
SETUP_ERR_RDLV_COMPLETE_TIMEOUT
SETUP_ERR_ZQ_CALIBRATION_FAILURE

Definition at line 794 of file setup.h.

Function Documentation

◆ cpu_info_init()

void cpu_info_init ( void )

◆ ddr3_mem_ctrl_init()

int ddr3_mem_ctrl_init	(	struct mem_timings *	mem,
		int	interleave_size,
		int	reset
	)

Definition at line 15 of file dmc_init_ddr3.c.

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◆ dmc_config_memory()

void dmc_config_memory	(	struct mem_timings *	mem,
		struct exynos5_dmc *	dmc
	)

Definition at line 157 of file dmc_common.c.

References DMC_MEMBASECONFIG0_VAL, DMC_MEMBASECONFIG1_VAL, exynos5_dmc::membaseconfig0, exynos5_dmc::membaseconfig1, mem_timings::memconfig, exynos5_dmc::memconfig0, exynos5_dmc::memconfig1, and write32().

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◆ dmc_config_mrs()

void dmc_config_mrs	(	struct mem_timings *	mem,
		struct exynos5_dmc *	dmc
	)

Definition at line 92 of file dmc_common.c.

References chip, mem_timings::chips_to_configure, DIRECT_CMD_CHANNEL_SHIFT, DIRECT_CMD_CHIP_SHIFT, mem_timings::direct_cmd_msr, DIRECT_CMD_NOP, DIRECT_CMD_ZQINIT, exynos5_dmc::directcmd, mem_timings::dmc_channels, mask, MEM_TIMINGS_MSR_COUNT, mem_timings::send_zq_init, udelay(), and write32().

Referenced by ddr3_mem_ctrl_init().

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◆ dmc_config_prech()

void dmc_config_prech	(	struct mem_timings *	mem,
		struct exynos5_dmc *	dmc
	)

Definition at line 139 of file dmc_common.c.

References chip, mem_timings::chips_per_channel, DIRECT_CMD_CHANNEL_SHIFT, DIRECT_CMD_CHIP_SHIFT, DIRECT_CMD_PALL, exynos5_dmc::directcmd, mem_timings::dmc_channels, mask, udelay(), and write32().

Referenced by ddr3_mem_ctrl_init().

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◆ dmc_config_zq()

int dmc_config_zq	(	struct mem_timings *	mem,
		struct exynos5_phy_control *	phy0_ctrl,
		struct exynos5_phy_control *	phy1_ctrl
	)

Definition at line 14 of file dmc_common.c.

References exynos5_phy_control::phy_con16, PHY_CON16_RESET_VAL, PHY_CON16_ZQ_MODE_DDS_SHIFT, PHY_CON16_ZQ_MODE_NOTERM_MASK, PHY_CON16_ZQ_MODE_TERM_SHIFT, exynos5_phy_control::phy_con17, read32(), udelay(), val, write32(), ZQ_CLK_DIV_EN, ZQ_DONE, ZQ_INIT_TIMEOUT, ZQ_MANUAL_STR, mem_timings::zq_mode_dds, mem_timings::zq_mode_noterm, and mem_timings::zq_mode_term.

Referenced by ddr3_mem_ctrl_init().

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◆ lpddr3_mem_ctrl_init()

int lpddr3_mem_ctrl_init ( int reset )

◆ mem_ctrl_init()

void mem_ctrl_init ( void )

◆ update_reset_dll()

void update_reset_dll	(	struct exynos5_dmc *	dmc,
		enum	ddr_mode
	)

Definition at line 72 of file dmc_common.c.

References DDR_MODE_DDR3, DMC_CTRL_SHGATE, FP_RSYNC, MEM_TERM_EN, PHY_TERM_EN, exynos5_dmc::phycontrol0, read32(), val, and write32().

Referenced by ddr3_mem_ctrl_init().

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Macros

Enumerations

Functions

Macro Definition Documentation

◆ APLL_CON0_LOCKED

◆ APLL_CON1_VAL

◆ APLL_FOUT

◆ APLL_LOCK_VAL

◆ AREF_EN

◆ AUDIO0_RATIO [1/2]

◆ AUDIO0_RATIO [2/2]

◆ AUDIO0_SEL

◆ AUDIO0_SEL_EPLL

◆ AUDIO1_RATIO

◆ AUDIO1_SEL

◆ AUDIO2_RATIO

◆ AUDIO2_SEL

◆ BPLL_CON0_LOCKED

◆ BPLL_CON1_VAL

◆ BPLL_LOCK_VAL

◆ BPLL_SEL_MASK

◆ BRBRSVCONFIG_VAL

◆ BRBRSVCONTROL_VAL

◆ BUSIF_RD_CG_EN

◆ BUSIF_WR_CG_EN

◆ BYPASS_EN

◆ BYTE_RDLVL_EN

◆ CA_ADR_DRVR_DS_OFFSET

◆ CA_CK_DRVR_DS_OFFSET

◆ CA_CKE_DRVR_DS_OFFSET

◆ CA_CS_DRVR_DS_OFFSET

◆ CA_SWAP_EN

◆ CLK_3DNR_MASK

◆ CLK_AC97_MASK

◆ CLK_ACP_MASK

◆ CLK_ARM9S_MASK

◆ CLK_ASYNCTVX_MASK

◆ CLK_C2C_MASK

◆ CLK_CAMIF_TOP_MASK

◆ CLK_CHIPID_MASK

◆ CLK_DIS_MASK

◆ CLK_DIV2_RATIO

◆ CLK_DIV4_RATIO

◆ CLK_DIV_ACP_VAL

◆ CLK_DIV_CDREX0_VAL

◆ CLK_DIV_CDREX1_VAL

◆ CLK_DIV_CDREX_VAL

◆ CLK_DIV_CORE0_VAL

◆ CLK_DIV_CORE1_VAL

◆ CLK_DIV_CPERI1_VAL

◆ CLK_DIV_CPU0_VAL

◆ CLK_DIV_CPU1_VAL

◆ CLK_DIV_DISP1_0_FIMD1

◆ CLK_DIV_DISP1_0_VAL

◆ CLK_DIV_FSYS0_VAL

◆ CLK_DIV_FSYS1_VAL

◆ CLK_DIV_FSYS2_VAL

◆ CLK_DIV_G2D

◆ CLK_DIV_ISP0_VAL

◆ CLK_DIV_ISP1_VAL

◆ CLK_DIV_ISP2_VAL [1/2]

◆ CLK_DIV_ISP2_VAL [2/2]

◆ CLK_DIV_KFC_VAL

◆ CLK_DIV_LEX_VAL [1/2]

◆ CLK_DIV_LEX_VAL [2/2]

◆ CLK_DIV_PERIC0_VAL

◆ CLK_DIV_PERIC1_VAL

◆ CLK_DIV_PERIC2_VAL

◆ CLK_DIV_PERIC3_VAL

◆ CLK_DIV_PERIC4_VAL

◆ CLK_DIV_R0X_VAL [1/2]

◆ CLK_DIV_R0X_VAL [2/2]

◆ CLK_DIV_R1X_VAL [1/2]

◆ CLK_DIV_R1X_VAL [2/2]

◆ CLK_DIV_SYSLFT_VAL

◆ CLK_DIV_SYSRGT_VAL

◆ CLK_DIV_TOP0_VAL

◆ CLK_DIV_TOP1_VAL

◆ CLK_DIV_TOP2_VAL

◆ CLK_DPHY0_MASK