dmc_common.c File Reference

#include <device/mmio.h>
#include <delay.h>
#include <soc/clk.h>
#include <soc/dmc.h>
#include <soc/setup.h>

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Macros
#define	ZQ_INIT_TIMEOUT   10000

Functions
int	dmc_config_zq (struct mem_timings *mem, struct exynos5_phy_control *phy0_ctrl, struct exynos5_phy_control *phy1_ctrl)
void	update_reset_dll (struct exynos5_dmc *dmc, enum ddr_mode mode)
void	dmc_config_mrs (struct mem_timings *mem, struct exynos5_dmc *dmc)
void	dmc_config_prech (struct mem_timings *mem, struct exynos5_dmc *dmc)
void	dmc_config_memory (struct mem_timings *mem, struct exynos5_dmc *dmc)

Macro Definition Documentation

ZQ_INIT_TIMEOUT

#define ZQ_INIT_TIMEOUT   10000

Definition at line 12 of file dmc_common.c.

Function Documentation

dmc_config_memory()

void dmc_config_memory	(	struct mem_timings *	mem,
		struct exynos5_dmc *	dmc
	)

Definition at line 157 of file dmc_common.c.

References DMC_MEMBASECONFIG0_VAL, DMC_MEMBASECONFIG1_VAL, exynos5_dmc::membaseconfig0, exynos5_dmc::membaseconfig1, mem_timings::memconfig, exynos5_dmc::memconfig0, exynos5_dmc::memconfig1, and write32().

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dmc_config_mrs()

void dmc_config_mrs	(	struct mem_timings *	mem,
		struct exynos5_dmc *	dmc
	)

Definition at line 92 of file dmc_common.c.

References chip, mem_timings::chips_to_configure, DIRECT_CMD_CHANNEL_SHIFT, DIRECT_CMD_CHIP_SHIFT, mem_timings::direct_cmd_msr, DIRECT_CMD_NOP, DIRECT_CMD_ZQINIT, exynos5_dmc::directcmd, mem_timings::dmc_channels, mask, MEM_TIMINGS_MSR_COUNT, mem_timings::send_zq_init, udelay(), and write32().

Referenced by ddr3_mem_ctrl_init().

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dmc_config_prech()

void dmc_config_prech	(	struct mem_timings *	mem,
		struct exynos5_dmc *	dmc
	)

Definition at line 139 of file dmc_common.c.

References chip, mem_timings::chips_per_channel, DIRECT_CMD_CHANNEL_SHIFT, DIRECT_CMD_CHIP_SHIFT, DIRECT_CMD_PALL, exynos5_dmc::directcmd, mem_timings::dmc_channels, mask, udelay(), and write32().

Referenced by ddr3_mem_ctrl_init().

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dmc_config_zq()

int dmc_config_zq	(	struct mem_timings *	mem,
		struct exynos5_phy_control *	phy0_ctrl,
		struct exynos5_phy_control *	phy1_ctrl
	)

Definition at line 14 of file dmc_common.c.

References exynos5_phy_control::phy_con16, PHY_CON16_RESET_VAL, PHY_CON16_ZQ_MODE_DDS_SHIFT, PHY_CON16_ZQ_MODE_NOTERM_MASK, PHY_CON16_ZQ_MODE_TERM_SHIFT, exynos5_phy_control::phy_con17, read32(), udelay(), val, write32(), ZQ_CLK_DIV_EN, ZQ_DONE, ZQ_INIT_TIMEOUT, ZQ_MANUAL_STR, mem_timings::zq_mode_dds, mem_timings::zq_mode_noterm, and mem_timings::zq_mode_term.

Referenced by ddr3_mem_ctrl_init().

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update_reset_dll()

void update_reset_dll	(	struct exynos5_dmc *	dmc,
		enum ddr_mode	mode
	)

Definition at line 72 of file dmc_common.c.

References DDR_MODE_DDR3, DMC_CTRL_SHGATE, FP_RSYNC, MEM_TERM_EN, PHY_TERM_EN, exynos5_dmc::phycontrol0, read32(), val, and write32().

Referenced by ddr3_mem_ctrl_init().

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