coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
qcom_qup_se.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/qcom_qup_se.h>
4 
5 struct qup qup[QUPV3_SE_MAX] = {
6  [QUPV3_0_SE0] = { .regs = (void *)QUP_SERIAL0_BASE,
7  .pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3) },
8  .func = { GPIO0_FUNC_QUP0_L0, GPIO1_FUNC_QUP0_L1,
9  GPIO2_FUNC_QUP0_L2, GPIO3_FUNC_QUP0_L3 }
10  },
11  [QUPV3_0_SE1] = { .regs = (void *)QUP_SERIAL1_BASE,
12  .pin = { GPIO(4), GPIO(5), GPIO(6), GPIO(7) },
13  .func = { GPIO4_FUNC_QUP0_L0, GPIO5_FUNC_QUP0_L1,
14  GPIO6_FUNC_QUP0_L2, GPIO7_FUNC_QUP0_L3 }
15  },
16  [QUPV3_0_SE2] = { .regs = (void *)QUP_SERIAL2_BASE,
17  .pin = { GPIO(8), GPIO(9), GPIO(10), GPIO(11) },
18  .func = { GPIO8_FUNC_QUP0_L0, GPIO9_FUNC_QUP0_L1,
19  GPIO10_FUNC_QUP0_L2, GPIO11_FUNC_QUP0_L3 }
20  },
21  [QUPV3_0_SE3] = { .regs = (void *)QUP_SERIAL3_BASE,
22  .pin = { GPIO(12), GPIO(13), GPIO(14), GPIO(15) },
23  .func = { GPIO12_FUNC_QUP0_L0, GPIO13_FUNC_QUP0_L1,
24  GPIO14_FUNC_QUP0_L2, GPIO15_FUNC_QUP0_L3 }
25  },
26  [QUPV3_0_SE4] = { .regs = (void *)QUP_SERIAL4_BASE,
27  .pin = { GPIO(16), GPIO(17), GPIO(18), GPIO(19) },
28  .func = { GPIO16_FUNC_QUP0_L0, GPIO17_FUNC_QUP0_L1,
29  GPIO18_FUNC_QUP0_L2, GPIO19_FUNC_QUP0_L3 }
30  },
31  [QUPV3_0_SE5] = { .regs = (void *)QUP_SERIAL5_BASE,
32  .pin = { GPIO(20), GPIO(21), GPIO(22), GPIO(23) },
33  .func = { GPIO20_FUNC_QUP0_L0, GPIO21_FUNC_QUP0_L1,
34  GPIO22_FUNC_QUP0_L2, GPIO23_FUNC_QUP0_L3 }
35  },
36  [QUPV3_0_SE6] = { .regs = (void *)QUP_SERIAL6_BASE,
37  .pin = { GPIO(24), GPIO(25), GPIO(26), GPIO(27) },
38  .func = { GPIO24_FUNC_QUP0_L0, GPIO25_FUNC_QUP0_L1,
39  GPIO26_FUNC_QUP0_L2, GPIO27_FUNC_QUP0_L3 }
40  },
41  [QUPV3_0_SE7] = { .regs = (void *)QUP_SERIAL7_BASE,
42  .pin = { GPIO(28), GPIO(29), GPIO(30), GPIO(31) },
43  .func = { GPIO28_FUNC_QUP0_L0, GPIO29_FUNC_QUP0_L1,
44  GPIO30_FUNC_QUP0_L2, GPIO31_FUNC_QUP0_L3 }
45  },
46  [QUPV3_1_SE0] = { .regs = (void *)QUP_SERIAL8_BASE,
47  .pin = { GPIO(32), GPIO(33), GPIO(34), GPIO(35) },
48  .func = { GPIO32_FUNC_QUP1_L0, GPIO33_FUNC_QUP1_L1,
49  GPIO34_FUNC_QUP1_L2, GPIO35_FUNC_QUP1_L3 }
50  },
51  [QUPV3_1_SE1] = { .regs = (void *)QUP_SERIAL9_BASE,
52  .pin = { GPIO(36), GPIO(37), GPIO(38), GPIO(39) },
53  .func = { GPIO36_FUNC_QUP1_L0, GPIO37_FUNC_QUP1_L1,
54  GPIO38_FUNC_QUP1_L2, GPIO39_FUNC_QUP1_L3 }
55  },
56  [QUPV3_1_SE2] = { .regs = (void *)QUP_SERIAL10_BASE,
57  .pin = { GPIO(40), GPIO(41), GPIO(42), GPIO(43) },
58  .func = { GPIO40_FUNC_QUP1_L0, GPIO41_FUNC_QUP1_L1,
59  GPIO42_FUNC_QUP1_L2, GPIO43_FUNC_QUP1_L3 }
60  },
61  [QUPV3_1_SE3] = { .regs = (void *)QUP_SERIAL11_BASE,
62  .pin = { GPIO(44), GPIO(45), GPIO(46), GPIO(47) },
63  .func = { GPIO44_FUNC_QUP1_L0, GPIO45_FUNC_QUP1_L1,
64  GPIO46_FUNC_QUP1_L2, GPIO47_FUNC_QUP1_L3 }
65  },
66  [QUPV3_1_SE4] = { .regs = (void *)QUP_SERIAL12_BASE,
67  .pin = { GPIO(48), GPIO(49), GPIO(50), GPIO(51) },
68  .func = { GPIO48_FUNC_QUP1_L0, GPIO49_FUNC_QUP1_L1,
69  GPIO50_FUNC_QUP1_L2, GPIO51_FUNC_QUP1_L3 }
70  },
71  [QUPV3_1_SE5] = { .regs = (void *)QUP_SERIAL13_BASE,
72  .pin = { GPIO(52), GPIO(53), GPIO(54), GPIO(55) },
73  .func = { GPIO52_FUNC_QUP1_L0, GPIO53_FUNC_QUP1_L1,
74  GPIO54_FUNC_QUP1_L2, GPIO55_FUNC_QUP1_L3 }
75  },
76  [QUPV3_1_SE6] = { .regs = (void *)QUP_SERIAL14_BASE,
77  .pin = { GPIO(56), GPIO(57), GPIO(58), GPIO(59) },
78  .func = { GPIO56_FUNC_QUP1_L0, GPIO57_FUNC_QUP1_L1,
79  GPIO58_FUNC_QUP1_L2, GPIO59_FUNC_QUP1_L3 }
80  },
81  [QUPV3_1_SE7] = { .regs = (void *)QUP_SERIAL15_BASE,
82  .pin = { GPIO(60), GPIO(61), GPIO(62), GPIO(63) },
83  .func = { GPIO60_FUNC_QUP1_L0, GPIO61_FUNC_QUP1_L1,
84  GPIO62_FUNC_QUP1_L2, GPIO63_FUNC_QUP1_L3 }
85  },
86 };
@ GPIO
Definition: chip.h:84
@ QUPV3_0_SE2
Definition: qcom_qup_se.h:15
@ QUPV3_SE_MAX
Definition: qcom_qup_se.h:25
@ QUPV3_0_SE3
Definition: qcom_qup_se.h:16
@ QUPV3_0_SE5
Definition: qcom_qup_se.h:18
@ QUPV3_1_SE0
Definition: qcom_qup_se.h:19
@ QUPV3_1_SE4
Definition: qcom_qup_se.h:23
@ QUPV3_0_SE0
Definition: qcom_qup_se.h:13
@ QUPV3_1_SE5
Definition: qcom_qup_se.h:24
@ QUPV3_1_SE2
Definition: qcom_qup_se.h:21
@ QUPV3_0_SE1
Definition: qcom_qup_se.h:14
@ QUPV3_1_SE3
Definition: qcom_qup_se.h:22
@ QUPV3_0_SE4
Definition: qcom_qup_se.h:17
@ QUPV3_1_SE1
Definition: qcom_qup_se.h:20
@ QUPV3_0_SE6
Definition: qcom_qup_se.h:20
@ QUPV3_1_SE7
Definition: qcom_qup_se.h:29
@ QUPV3_1_SE6
Definition: qcom_qup_se.h:28
@ QUPV3_0_SE7
Definition: qcom_qup_se.h:21
#define QUP_SERIAL0_BASE
Definition: addressmap.h:20
#define QUP_SERIAL1_BASE
Definition: addressmap.h:21
#define QUP_SERIAL5_BASE
Definition: addressmap.h:25
#define QUP_SERIAL9_BASE
Definition: addressmap.h:32
#define QUP_SERIAL7_BASE
Definition: addressmap.h:30
#define QUP_SERIAL2_BASE
Definition: addressmap.h:22
#define QUP_SERIAL3_BASE
Definition: addressmap.h:23
#define QUP_SERIAL4_BASE
Definition: addressmap.h:24
#define QUP_SERIAL8_BASE
Definition: addressmap.h:31
#define QUP_SERIAL10_BASE
Definition: addressmap.h:33
#define QUP_SERIAL11_BASE
Definition: addressmap.h:34
#define QUP_SERIAL6_BASE
Definition: addressmap.h:29
#define QUP_SERIAL13_BASE
Definition: addressmap.h:52
#define QUP_SERIAL12_BASE
Definition: addressmap.h:51
#define QUP_SERIAL14_BASE
Definition: addressmap.h:53
#define QUP_SERIAL15_BASE
Definition: addressmap.h:54
struct qup_regs * regs
Definition: qcom_qup_se.h:29
gpio_t pin[6]
Definition: qcom_qup_se.h:30