19 #include <soc/data_fabric.h>
20 #include <soc/pci_devs.h>
21 #include <arch/mmio.h>
34 current += hsa_entry->
length;
39 uint64_t region_size,
unsigned long current)
49 mem_affinity->
length_low = region_size & 0xffffffff;
50 mem_affinity->
length_high = (region_size >> 32) & 0xffffffff;
52 mem_affinity->
width = 64;
54 current += mem_affinity->
length;
59 unsigned long current)
61 uint32_t dram_base_reg, dram_limit_reg, dram_hole_ctl;
62 uint64_t memory_length, memory_base, hole_base, size_below_hole;
63 size_t new_entries = 0;
76 memory_length = memory_length << 28;
80 if (memory_base == 0) {
83 memory_base = 1 *
MiB;
84 memory_length = memory_base;
92 size_below_hole = hole_base - memory_base;
94 size_below_hole, current);
99 memory_base = 0x100000000;
113 unsigned long current)
115 *cache_affinity = (
struct crat_cache *)current;
119 (*cache_affinity)->length =
sizeof(
struct crat_cache);
130 switch (encoded_associativity) {
136 return encoded_associativity;
173 size_t total_num_threads, num_threads_sharing0, num_threads_sharing1,
174 num_threads_sharing2, num_threads_sharing3, thread, new_entries;
175 struct cpuid_result cache_props0, cache_props1, cache_props2, cache_props3;
177 uint32_t l1_data_cache_ids, l1_inst_cache_ids, l2_cache_ids, l3_cache_ids;
192 num_threads_sharing0 =
194 num_threads_sharing1 =
196 num_threads_sharing2 =
198 num_threads_sharing3 =
202 for (thread = 0; thread < total_num_threads; thread++) {
204 if (thread % num_threads_sharing0 == 0) {
211 for (
size_t sibling = 1; sibling < num_threads_sharing0; sibling++)
212 sibling_mask = (sibling_mask << 1) + 1;
213 cache_affinity->
sibling_map[thread / 8] = sibling_mask << (thread % 8);
231 if (thread % num_threads_sharing1 == 0) {
238 for (
size_t sibling = 1; sibling < num_threads_sharing1; sibling++)
239 sibling_mask = (sibling_mask << 1) + 1;
240 cache_affinity->
sibling_map[thread / 8] = sibling_mask << (thread % 8);
258 if (thread % num_threads_sharing2 == 0) {
262 cache_affinity->
flags |=
266 for (
size_t sibling = 1; sibling < num_threads_sharing2; sibling++)
267 sibling_mask = (sibling_mask << 1) + 1;
268 cache_affinity->
sibling_map[thread / 8] = sibling_mask << (thread % 8);
284 if (thread % num_threads_sharing3 == 0) {
288 cache_affinity->
flags |=
292 for (
size_t sibling = 1; sibling < num_threads_sharing3; sibling++)
293 sibling_mask = (sibling_mask << 1) + 1;
294 cache_affinity->
sibling_map[thread / 8] = sibling_mask << (thread % 8);
318 if (raw_assoc_size >= 256) {
319 tlbsize = (
uint8_t)(raw_assoc_size / 256);
328 tlbsize = (
uint8_t)(raw_assoc_size);
335 *tlb_affinity = (
struct crat_tlb *)current;
339 (*tlb_affinity)->length =
sizeof(
struct crat_tlb);
348 size_t total_num_threads, num_threads_sharing0, num_threads_sharing1,
349 num_threads_sharing2, thread, new_entries;
350 struct cpuid_result cache_props0, cache_props1, cache_props2;
352 uint32_t l1_tlb_2M4M_ids, l1_tlb_4K_ids, l2_tlb_2M4M_ids, l2_tlb_4K_ids, l1_tlb_1G_ids,
368 num_threads_sharing0 =
370 num_threads_sharing1 =
372 num_threads_sharing2 =
376 for (thread = 0; thread < total_num_threads; thread++) {
379 if (thread % num_threads_sharing0 == 0) {
386 for (
size_t sibling = 1; sibling < num_threads_sharing0; sibling++)
387 sibling_mask = (sibling_mask << 1) + 1;
388 tlb_affinity->
sibling_map[thread / 8] = sibling_mask << (thread % 8);
417 if (thread % num_threads_sharing1 == 0) {
424 for (
size_t sibling = 1; sibling < num_threads_sharing1; sibling++)
425 sibling_mask = (sibling_mask << 1) + 1;
426 tlb_affinity->
sibling_map[thread / 8] = sibling_mask << (thread % 8);
454 if (thread % num_threads_sharing2 == 0) {
461 for (
size_t sibling = 1; sibling < num_threads_sharing2; sibling++)
462 sibling_mask = (sibling_mask << 1) + 1;
463 tlb_affinity->
sibling_map[thread / 8] = sibling_mask << (thread % 8);
491 if (thread % num_threads_sharing2 == 0) {
498 for (
size_t sibling = 1; sibling < num_threads_sharing2; sibling++)
499 sibling_mask = (sibling_mask << 1) + 1;
500 tlb_affinity->
sibling_map[thread / 8] = sibling_mask << (thread % 8);
550 current =
ALIGN(current, 8);
560 current =
ALIGN(current, 8);
void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long(*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current))
void acpi_add_table(acpi_rsdp_t *rsdp, void *table)
Add an ACPI table to the RSDT (and XSDT) structure, recalculate length and checksum.
void acpi_create_crat(struct acpi_crat_header *crat, unsigned long(*acpi_fill_crat)(struct acpi_crat_header *crat_struct, unsigned long current))
#define CRAT_TLB_FLAG_1GB_BASE_256
#define CRAT_TLB_FLAG_2MB_BASE_256
#define CRAT_CACHE_FLAG_CPU_CACHE
#define CRAT_HSA_PR_FLAG_CPU_PRES
#define CRAT_TLB_FLAG_CPU_TLB
#define CRAT_CACHE_FLAG_EN
#define CRAT_TLB_FLAG_INSTR_TLB
#define CRAT_TLB_FLAG_DATA_TLB
#define CRAT_HSA_PR_FLAG_EN
#define CRAT_CACHE_FLAG_DATA_CACHE
#define CRAT_CACHE_FLAG_INSTR_CACHE
#define CRAT_TLB_FLAG_4K_BASE_256
static unsigned int cpuid_edx(unsigned int op)
static unsigned int cpuid_ecx(unsigned int op)
static unsigned int cpuid_eax(unsigned int op)
static unsigned int cpuid_ebx(unsigned int op)
static struct cpuid_result cpuid_ext(int op, unsigned int ecx)
void * memset(void *dstpp, int c, size_t len)
uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp)
#define L1_DAT_TLB_4K_SIZE_MASK
#define L1_DAT_TLB_2M4M_ASSOC_SHFT
#define L2_DAT_TLB_1G_SIZE_SHFT
#define L2_DC_LINE_TAG_MASK
#define L1_INST_TLB_2M4M_SIZE_SHFT
#define L1_INST_TLB_4K_ASSOC_SHFT
#define L2_DAT_TLB_2M4M_ASSOC_MASK
#define L2_INST_TLB_4K_ASSOC_MASK
#define CPUID_TLB_L1L2_1G_IDS
#define L1_DAT_TLB_4K_ASSOC_SHFT
#define L1_INST_TLB_1G_SIZE_SHFT
#define L2_INST_TLB_1G_ASSOC_SHFT
#define L2_INST_TLB_2M4M_SIZE_MASK
#define L1_INST_TLB_2M4M_SIZE_MASK
#define L1_INST_TLB_4K_SIZE_SHFT
#define L1_DAT_TLB_1G_ASSOC_MASK
#define L1_INST_TLB_1G_ASSOC_SHFT
#define L2_DAT_TLB_2M4M_SIZE_SHFT
#define L1_INST_TLB_4K_ASSOC_MASK
#define L1_DC_LINE_SIZE_SHFT
#define L2_DAT_TLB_1G_ASSOC_MASK
#define L1_INST_TLB_2M4M_ASSOC_SHFT
#define L1_DAT_TLB_2M4M_SIZE_MASK
#define L2_INST_TLB_2M4M_SIZE_SHFT
#define L3_DC_LINE_TAG_SHFT
#define L2_DC_LINE_SIZE_MASK
#define L3_DC_LINE_SIZE_MASK
#define L3_DC_LINE_SIZE_SHFT
#define L1_DAT_TLB_4K_SIZE_SHFT
#define CPUID_CACHE_PROPS
#define L1_DAT_TLB_4K_ASSOC_MASK
#define CACHE_INCLUSIVE_MASK
#define L1_IC_LINE_SIZE_SHFT
#define L2_DC_LINE_TAG_SHFT
#define NUM_SHARE_CACHE_SHFT
#define L1_INST_TLB_1G_ASSOC_MASK
#define L2_INST_TLB_4K_SIZE_SHFT
#define L1_INST_TLB_2M4M_ASSOC_MASK
#define L2_DAT_TLB_1G_SIZE_MASK
#define L2_DAT_TLB_4K_ASSOC_SHFT
#define L1_IC_LINE_SIZE_MASK
#define L1_DAT_TLB_1G_SIZE_SHFT
#define L2_DAT_TLB_2M4M_ASSOC_SHFT
#define L2_DAT_TLB_4K_SIZE_MASK
#define L1_IC_LINE_TAG_MASK
#define L2_INST_TLB_1G_SIZE_SHFT
#define L1_DC_LINE_TAG_MASK
#define CPUID_L2_L3_CACHE_L2_TLB_IDS
#define CPUID_L1_TLB_CACHE_IDS
#define L1_DAT_TLB_1G_SIZE_MASK
#define L2_INST_TLB_1G_SIZE_MASK
#define L3_DC_LINE_TAG_MASK
#define L1_DC_LINE_TAG_SHFT
#define L2_INST_TLB_4K_SIZE_MASK
#define L1_DAT_TLB_2M4M_SIZE_SHFT
#define L2_DAT_TLB_4K_SIZE_SHFT
#define L2_DAT_TLB_1G_ASSOC_SHFT
#define L1_IC_LINE_TAG_SHFT
#define L2_INST_TLB_2M4M_ASSOC_MASK
#define L2_DC_LINE_SIZE_SHFT
#define L1_INST_TLB_4K_SIZE_MASK
#define L2_INST_TLB_2M4M_ASSOC_SHFT
#define L1_INST_TLB_1G_SIZE_MASK
#define L2_DAT_TLB_2M4M_SIZE_MASK
#define L2_INST_TLB_4K_ASSOC_SHFT
#define L2_INST_TLB_1G_ASSOC_MASK
#define L1_DC_LINE_SIZE_MASK
#define L1_DAT_TLB_1G_ASSOC_SHFT
#define NUM_SHARE_CACHE_MASK
#define L1_DAT_TLB_2M4M_ASSOC_MASK
uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id)
static int get_cpu_count(void)
static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
static unsigned long gen_crat_cache_entry(struct acpi_crat_header *crat, unsigned long current)
static unsigned long acpi_fill_crat(struct acpi_crat_header *crat, unsigned long current)
static unsigned long add_crat_tlb_entry(struct crat_tlb **tlb_affinity, unsigned long current)
static unsigned long gen_crat_hsa_entry(struct acpi_crat_header *crat, unsigned long current)
static unsigned long create_crat_memory_entry(uint32_t domain, uint64_t region_base, uint64_t region_size, unsigned long current)
static uint8_t get_tlb_size(enum tlb_type type, struct crat_tlb *crat_tlb_entry, uint16_t raw_assoc_size)
static uint8_t get_associativity(uint32_t encoded_associativity)
static unsigned long add_crat_cache_entry(struct crat_cache **cache_affinity, unsigned long current)
static unsigned long gen_crat_tlb_entry(struct acpi_crat_header *crat, unsigned long current)
static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, unsigned long current)
#define DF_DRAM_LIMIT(dram_map_pair)
#define PICASSO_NUM_DRAM_REG
#define DRAM_HOLE_CTL_BASE
#define D18F0_DRAM_HOLE_CTL
#define DRAM_BASE_REG_VALID
#define DRAM_BASE_HOLE_EN
#define DRAM_BASE_ADDR_SHFT
#define DRAM_LIMIT_ADDR_SHFT
#define DF_DRAM_BASE(dram_map_pair)
uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, uintptr_t current)
unsigned long long uint64_t
uint32_t base_address_low
uint32_t proximity_domain
uint32_t base_address_high
uint8_t data_tlb_4k_assoc
uint8_t data_tlb_2mb_assoc
uint8_t instr_tlb_1g_assoc
uint8_t instr_tlb_2mb_assoc
uint8_t data_tlb_2mb_size
uint8_t instr_tlb_2mb_size
uint8_t instr_tlb_4k_assoc
uint8_t instr_tlb_1g_size
uint8_t instr_tlb_4k_size
uint8_t data_tlb_1g_assoc