coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/mmio.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <option.h>
#include <acpi/acpi_sata.h>
#include <types.h>
#include "chip.h"
#include "pch.h"
Go to the source code of this file.
Functions | |
static u32 | sir_read (struct device *dev, int idx) |
static void | sir_write (struct device *dev, int idx, u32 value) |
static void | sata_init (struct device *dev) |
static void | sata_enable (struct device *dev) |
static void | sata_fill_ssdt (const struct device *dev) |
Variables | |
static struct device_operations | sata_ops |
static const unsigned short | pci_device_ids [] |
static const struct pci_driver pch_sata | __pci_driver |
Definition at line 166 of file sata.c.
References device::chip_info, config, get_uint_option(), and pci_write_config16().
Definition at line 189 of file sata.c.
References device::chip_info, config, and generate_sata_ssdt_ports().
Definition at line 28 of file sata.c.
References BIOS_DEBUG, BIOS_ERR, device::chip_info, config, get_uint_option(), IDE_DECODE_ENABLE, IDE_TIM_PRI, IDE_TIM_SEC, INTR_LN, NULL, PCI_BASE_ADDRESS_5, PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEMORY, pci_read_config16(), pci_read_config32(), pci_write_config16(), pci_write_config32(), pci_write_config8(), printk, read32(), sir_read(), sir_write(), void(), and write32().
Definition at line 16 of file sata.c.
References pci_read_config32(), pci_write_config32(), SATA_SIRD, and SATA_SIRI.
Referenced by sata_init().
Definition at line 22 of file sata.c.
References pci_write_config32(), SATA_SIRD, SATA_SIRI, and value.
Referenced by sata_init().
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