![]() |
coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
|
#include <acpi/acpi.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <soc/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <southbridge/intel/common/pmbase.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <elog.h>
#include <ec/google/chromeec/ec.h>
#include "ec.h"
Go to the source code of this file.
Functions | |
static u8 | mainboard_smi_ec (void) |
void | mainboard_smi_gpi (u32 gpi_sts) |
void | mainboard_smi_sleep (u8 slp_typ) |
int | mainboard_smi_apmc (u8 apmc) |
int mainboard_smi_apmc | ( | u8 | apmc | ) |
Definition at line 79 of file smihandler.c.
References APM_CNT_ACPI_DISABLE, APM_CNT_ACPI_ENABLE, EC_HOST_EVENT_NONE, google_chromeec_get_event(), google_chromeec_set_sci_mask(), google_chromeec_set_smi_mask(), LINK_EC_SCI_EVENTS, and LINK_EC_SMI_EVENTS.
Definition at line 17 of file smihandler.c.
References BIOS_DEBUG, EC_HOST_EVENT_LID_CLOSED, elog_gsmi_add_event_byte(), ELOG_TYPE_EC_EVENT, google_chromeec_get_event(), PM1_CNT, printk, read_pmbase32(), and write_pmbase32().
Referenced by mainboard_smi_gpi().
Definition at line 37 of file smihandler.c.
References EC_SMI_GPI, and mainboard_smi_ec().
Definition at line 45 of file smihandler.c.
References ACPI_S3, ACPI_S5, EC_HOST_EVENT_NONE, gnvs, google_chromeec_get_event(), google_chromeec_set_sci_mask(), google_chromeec_set_smi_mask(), google_chromeec_set_usb_charge_mode(), google_chromeec_set_wake_mask(), LINK_EC_S3_WAKE_EVENTS, global_nvs::s3u0, global_nvs::s3u1, global_nvs::s5u0, global_nvs::s5u1, and USB_CHARGE_MODE_DISABLED.