coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
lpss.c File Reference
#include <device/mmio.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <intelblocks/lpss.h>
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Macros

#define LPSS_CLOCK_CTL_REG   0x200
 
#define LPSS_CNT_CLOCK_EN   1
 
#define LPSS_CNT_CLK_UPDATE   (1 << 31)
 
#define LPSS_CLOCK_DIV_N(n)   (((n) & 0x7fff) << 16)
 
#define LPSS_CLOCK_DIV_M(m)   (((m) & 0x7fff) << 1)
 
#define LPSS_RESET_CTL_REG   0x204
 
#define LPSS_CNT_RST_RELEASE   3
 
#define LPSS_DMA_RST_RELEASE   (1 << 2)
 
#define PME_CTRL_STATUS   0x84
 
#define POWER_STATE_MASK   3
 

Functions

bool lpss_is_controller_in_reset (uintptr_t base)
 
void lpss_reset_release (uintptr_t base)
 
void lpss_clk_update (uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
 
void lpss_set_power_state (pci_devfn_t devfn, enum lpss_pwr_state state)
 

Macro Definition Documentation

◆ LPSS_CLOCK_CTL_REG

#define LPSS_CLOCK_CTL_REG   0x200

Definition at line 9 of file lpss.c.

◆ LPSS_CLOCK_DIV_M

#define LPSS_CLOCK_DIV_M (   m)    (((m) & 0x7fff) << 1)

Definition at line 13 of file lpss.c.

◆ LPSS_CLOCK_DIV_N

#define LPSS_CLOCK_DIV_N (   n)    (((n) & 0x7fff) << 16)

Definition at line 12 of file lpss.c.

◆ LPSS_CNT_CLK_UPDATE

#define LPSS_CNT_CLK_UPDATE   (1 << 31)

Definition at line 11 of file lpss.c.

◆ LPSS_CNT_CLOCK_EN

#define LPSS_CNT_CLOCK_EN   1

Definition at line 10 of file lpss.c.

◆ LPSS_CNT_RST_RELEASE

#define LPSS_CNT_RST_RELEASE   3

Definition at line 26 of file lpss.c.

◆ LPSS_DMA_RST_RELEASE

#define LPSS_DMA_RST_RELEASE   (1 << 2)

Definition at line 29 of file lpss.c.

◆ LPSS_RESET_CTL_REG

#define LPSS_RESET_CTL_REG   0x204

Definition at line 16 of file lpss.c.

◆ PME_CTRL_STATUS

#define PME_CTRL_STATUS   0x84

Definition at line 32 of file lpss.c.

◆ POWER_STATE_MASK

#define POWER_STATE_MASK   3

Definition at line 34 of file lpss.c.

Function Documentation

◆ lpss_clk_update()

void lpss_clk_update ( uintptr_t  base,
uint32_t  clk_m_val,
uint32_t  clk_n_val 
)

Definition at line 55 of file lpss.c.

References addr, base, LPSS_CLOCK_CTL_REG, LPSS_CLOCK_DIV_M, LPSS_CLOCK_DIV_N, LPSS_CNT_CLK_UPDATE, LPSS_CNT_CLOCK_EN, and write32().

Referenced by uart_lpss_init().

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◆ lpss_is_controller_in_reset()

bool lpss_is_controller_in_reset ( uintptr_t  base)

Definition at line 36 of file lpss.c.

References addr, base, LPSS_CNT_RST_RELEASE, LPSS_RESET_CTL_REG, read32(), and val.

Referenced by uart_is_controller_initialized().

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◆ lpss_reset_release()

void lpss_reset_release ( uintptr_t  base)

Definition at line 47 of file lpss.c.

References addr, base, LPSS_CNT_RST_RELEASE, LPSS_RESET_CTL_REG, and write32().

Referenced by lpss_i2c_early_init_bus(), and uart_lpss_init().

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◆ lpss_set_power_state()

void lpss_set_power_state ( pci_devfn_t  devfn,
enum lpss_pwr_state  state 
)

Definition at line 68 of file lpss.c.

References pci_s_read_config8(), pci_s_write_config8(), PME_CTRL_STATUS, and POWER_STATE_MASK.

Referenced by gspi_ctrlr_setup(), lpss_i2c_early_init_bus(), and uart_lpss_init().

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