15 #include <soc/iomap.h>
16 #include <soc/pci_devs.h>
22 #define SSCR0_EDSS_0 (0 << 20)
23 #define SSCR0_EDSS_1 (1 << 20)
24 #define SSCR0_SCR_SHIFT (8)
25 #define SSCR0_SCR_MASK (0xFFF)
26 #define SSCR0_SSE_DISABLE (0 << 7)
27 #define SSCR0_SSE_ENABLE (1 << 7)
28 #define SSCR0_ECS_ON_CHIP (0 << 6)
29 #define SSCR0_FRF_MOTOROLA (0 << 4)
30 #define SSCR0_DSS_SHIFT (0)
31 #define SSCR0_DSS_MASK (0xF)
33 #define SSCR1_IFS_LOW (0 << 16)
34 #define SSCR1_IFS_HIGH (1 << 16)
35 #define SSCR1_SPH_FIRST (0 << 4)
36 #define SSCR1_SPH_SECOND (1 << 4)
37 #define SSCR1_SPO_LOW (0 << 3)
38 #define SSCR1_SPO_HIGH (1 << 3)
40 #define SSSR_TUR (1 << 21)
41 #define SSSR_TINT (1 << 19)
42 #define SSSR_PINT (1 << 18)
44 #define SSSR_ROR (1 << 7)
45 #define SSSR_BSY (1 << 4)
46 #define SSSR_RNE (1 << 3)
47 #define SSSR_TNF (1 << 2)
51 #define SITF_LEVEL_SHIFT (16)
52 #define SITF_LEVEL_MASK (0x3f)
53 #define SITF_LWM_SHIFT (8)
54 #define SITF_LWM_MASK (0x3f)
55 #define SITF_LWM(x) ((((x) - 1) & SITF_LWM_MASK) << SITF_LWM_SHIFT)
56 #define SITF_HWM_SHIFT (0)
57 #define SITF_HWM_MASK (0x3f)
58 #define SITF_HWM(x) ((((x) - 1) & SITF_HWM_MASK) << SITF_HWM_SHIFT)
60 #define SIRF_LEVEL_SHIFT (8)
61 #define SIRF_LEVEL_MASK (0x3f)
62 #define SIRF_WM_SHIFT (0)
63 #define SIRF_WM_MASK (0x3f)
64 #define SIRF_WM(x) ((((x) - 1) & SIRF_WM_MASK) << SIRF_WM_SHIFT)
68 #define CLOCKS_UPDATE (1 << 31)
69 #define CLOCKS_N_SHIFT (16)
70 #define CLOCKS_N_MASK (0x7fff)
71 #define CLOCKS_M_SHIFT (1)
72 #define CLOCKS_M_MASK (0x7fff)
73 #define CLOCKS_DISABLE (0 << 0)
74 #define CLOCKS_ENABLE (1 << 0)
76 #define DMA_RESET (0 << 2)
77 #define DMA_ACTIVE (1 << 2)
78 #define CTRLR_RESET (0 << 0)
79 #define CTRLR_ACTIVE (3 << 0)
80 #define ACTIVELTR_VALUE 0x210
81 #define IDLELTR_VALUE 0x214
82 #define TX_BIT_COUNT 0x218
83 #define RX_BIT_COUNT 0x21c
85 #define DMA_FINISH_DISABLE (1 << 0)
86 #define SPI_CS_CONTROL 0x224
87 #define CS_0_POL_SHIFT (12)
88 #define CS_0_POL_MASK (1 << CS_0_POL_SHIFT)
89 #define CS_POL_LOW (0)
90 #define CS_POL_HIGH (1)
92 #define CS_STATE_SHIFT (1)
93 #define CS_STATE_MASK (1 << CS_STATE_SHIFT)
94 #define CS_V1_STATE_LOW (0)
95 #define CS_V1_STATE_HIGH (1)
96 #define CS_MODE_HW (0 << 0)
97 #define CS_MODE_SW (1 << 0)
99 #define GSPI_DATA_BIT_LENGTH (8)
100 #define GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
114 return &common_config->
gspi[0];
117 #if defined(__SIMPLE_DEVICE__)
137 unsigned int gspi_bus;
138 const unsigned int gspi_max = CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX;
151 if (!gspi_base_addr) {
157 for (gspi_bus = 0; gspi_bus < gspi_max; gspi_bus++) {
354 if (
CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
378 if (
CONFIG(SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2))
435 CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ;
449 uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol;
573 " (bus=%u).\n", __func__, p->
gspi_bus);
629 "(bus=%u)\n", __func__, p->
gspi_bus);
int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
void * memset(void *dstpp, int c, size_t len)
#define assert(statement)
static struct sdram_info params
#define DIV_ROUND_UP(x, y)
static uintptr_t gspi_get_early_base(void)
static int gspi_cs_assert(const struct spi_slave *dev)
static uintptr_t gspi_base[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
static uint32_t gspi_read_mmio_reg(const struct gspi_ctrlr_params *p, uint32_t offset)
static void gspi_write_mmio_reg(const struct gspi_ctrlr_params *p, uint32_t offset, uint32_t value)
static uint32_t gspi_csctrl_state(uint32_t pol, enum cs_assert cs_assert)
static uint32_t gspi_get_bus_clk_mhz(unsigned int gspi_bus)
static const struct gspi_cfg * gspi_get_cfg(void)
static uint32_t gspi_get_clk_div(unsigned int gspi_bus)
static uintptr_t gspi_calc_base_addr(unsigned int gspi_bus)
static int gspi_read_bus_range(unsigned int *start, unsigned int *end)
static uint32_t gspi_csctrl_polarity_v1(enum spi_polarity active_pol)
static void gspi_read_data(struct gspi_ctrlr_params *p)
int __weak gspi_get_soc_spi_cfg(unsigned int gspi_bus, struct spi_cfg *cfg)
#define GSPI_BUS_BASE(bar, bus)
#define GSPI_DATA_BIT_LENGTH
static void gspi_clear_status(const struct gspi_ctrlr_params *p)
static void gspi_clear_cached_base(void *unused)
static void gspi_cs_deassert(const struct spi_slave *dev)
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_cached_base, NULL)
static bool gspi_tx_fifo_full(const struct gspi_ctrlr_params *p)
static bool gspi_rx_fifo_empty(const struct gspi_ctrlr_params *p)
static int gspi_ctrlr_flush(const struct gspi_ctrlr_params *p)
static uint32_t gspi_csctrl_polarity(enum spi_polarity active_pol)
static uint32_t gspi_csctrl_state_v1(uint32_t pol, enum cs_assert cs_assert)
static uintptr_t gspi_get_bus_base_addr(unsigned int gspi_bus)
static int gspi_ctrlr_params_init(struct gspi_ctrlr_params *p, unsigned int spi_bus)
static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base)
#define SSCR0_ECS_ON_CHIP
static uint8_t gspi_read_byte(const struct gspi_ctrlr_params *p)
static int gspi_ctrlr_xfer(const struct spi_slave *dev, const void *dout, size_t bytesout, void *din, size_t bytesin)
static int gspi_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
static uintptr_t gspi_get_base_addr(int devfn, struct device *dev)
static int __gspi_xfer(struct gspi_ctrlr_params *p)
static void __gspi_cs_change(const struct gspi_ctrlr_params *p, enum cs_assert cs_assert)
static uint32_t gspi_csctrl_state_v2(uint32_t pol, enum cs_assert cs_assert)
static uint32_t gspi_read_status(const struct gspi_ctrlr_params *p)
static int gspi_cs_change(const struct spi_slave *dev, enum cs_assert cs_assert)
static void gspi_write_dummy(struct gspi_ctrlr_params *p)
#define SSCR0_SSE_DISABLE
static void gspi_write_data(struct gspi_ctrlr_params *p)
static bool gspi_rx_fifo_overrun(const struct gspi_ctrlr_params *p)
static void gspi_read_dummy(struct gspi_ctrlr_params *p)
static uint32_t gspi_csctrl_polarity_v2(enum spi_polarity active_pol)
static void gspi_write_byte(const struct gspi_ctrlr_params *p, uint8_t data)
const struct spi_ctrlr gspi_ctrlr
static int gspi_ctrlr_setup(const struct spi_slave *dev)
#define SSCR0_FRF_MOTOROLA
#define printk(level,...)
DEVTREE_CONST struct device * pcidev_path_on_root(pci_devfn_t devfn)
void gspi_early_bar_init(void)
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
static int stopwatch_expired(struct stopwatch *sw)
static void stopwatch_init_msecs_expire(struct stopwatch *sw, long ms)
#define EARLY_GSPI_BASE_ADDRESS
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state)
#define PCI_COMMAND_MASTER
#define PCI_COMMAND_MEMORY
#define PCI_BASE_ADDRESS_0
#define PCI_DEV(SEGBUS, DEV, FN)
const struct smm_save_state_ops *legacy_ops __weak
const struct soc_intel_common_config * chip_get_common_soc_structure(void)
#define SPI_CTRLR_DEFAULT_MAX_XFER_SIZE
const struct spi_ctrlr_buses spi_ctrlr_bus_map[]
const size_t spi_ctrlr_bus_map_count
struct mtk_spi_bus spi_bus[]
struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]
enum spi_wire_mode wire_mode
unsigned int data_bit_length
enum spi_clock_phase clk_phase
enum spi_polarity cs_polarity
enum spi_polarity clk_polarity
const struct spi_ctrlr * ctrlr
int(* claim_bus)(const struct spi_slave *slave)
typedef void(X86APIP X86EMU_intrFuncs)(int num)