coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_usb.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/pci_ops.h>
4 #include <device/pci_def.h>
5 #include "pch.h"
6 
7 /* HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
8  * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
9  */
10 #if CONFIG_USBDEBUG_HCD_INDEX != 2
11 #define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
12 #define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
13 #else
14 #define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
15 #define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
16 #endif
17 
18 /*
19  * Setup USB controller MMIO BAR to prevent the
20  * reference code from resetting the controller.
21  *
22  * The BAR will be re-assigned during device
23  * enumeration so these are only temporary.
24  */
26 {
29 }
30 
31 void enable_usb_bar(void)
32 {
34  if (!pch_is_lp())
36 }
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline void pci_or_config16(const struct device *dev, u16 reg, u16 ormask)
Definition: pci_ops.h:180
void enable_usb_bar(void)
Definition: early_usb.c:31
static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar)
Definition: early_usb.c:25
#define PCH_EHCI1_TEMP_BAR0
Definition: early_usb.c:11
#define PCH_EHCI2_TEMP_BAR0
Definition: early_usb.c:12
#define PCI_COMMAND_MASTER
Definition: pci_def.h:13
#define PCI_COMMAND_MEMORY
Definition: pci_def.h:12
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
#define PCI_COMMAND
Definition: pci_def.h:10
u32 pci_devfn_t
Definition: pci_type.h:8
#define PCH_EHCI1_DEV
Definition: pch.h:77
#define PCH_EHCI2_DEV
Definition: pch.h:78
static int pch_is_lp(void)
Definition: pch.h:104
uint32_t u32
Definition: stdint.h:51