10 #include <soc/symbols.h>
13 #define SPM_SYSTEM_BASE_OFFSET 0x40000000
22 .reg_dpmaif_srcclkena_mask_b = 1,
23 .reg_dpmaif_infra_req_mask_b = 1,
24 .reg_dpmaif_apsrc_req_mask_b = 1,
25 .reg_dpmaif_vrf18_req_mask_b = 1,
26 .reg_dpmaif_ddr_en_mask_b = 1,
29 .reg_spm_ddr_en_req = 1,
32 .reg_md_srcclkena_0_mask_b = 1,
33 .reg_md_apsrc2infra_req_0_mask_b = 1,
34 .reg_md_apsrc_req_0_mask_b = 1,
35 .reg_md_vrf18_req_0_mask_b = 1,
36 .reg_md_ddr_en_0_mask_b = 1,
37 .reg_conn_srcclkena_mask_b = 1,
38 .reg_conn_infra_req_mask_b = 1,
39 .reg_conn_apsrc_req_mask_b = 1,
40 .reg_conn_vrf18_req_mask_b = 1,
41 .reg_conn_ddr_en_mask_b = 1,
42 .reg_srcclkeni0_srcclkena_mask_b = 1,
43 .reg_srcclkeni0_infra_req_mask_b = 1,
44 .reg_infrasys_ddr_en_mask_b = 1,
45 .reg_md32_srcclkena_mask_b = 1,
46 .reg_md32_infra_req_mask_b = 1,
47 .reg_md32_apsrc_req_mask_b = 1,
48 .reg_md32_vrf18_req_mask_b = 1,
49 .reg_md32_ddr_en_mask_b = 1,
52 .reg_scp_srcclkena_mask_b = 1,
53 .reg_scp_infra_req_mask_b = 1,
54 .reg_scp_apsrc_req_mask_b = 1,
55 .reg_scp_vrf18_req_mask_b = 1,
56 .reg_scp_ddr_en_mask_b = 1,
57 .reg_audio_dsp_srcclkena_mask_b = 1,
58 .reg_audio_dsp_infra_req_mask_b = 1,
59 .reg_audio_dsp_apsrc_req_mask_b = 1,
60 .reg_audio_dsp_vrf18_req_mask_b = 1,
61 .reg_audio_dsp_ddr_en_mask_b = 1,
62 .reg_ufs_srcclkena_mask_b = 1,
63 .reg_ufs_infra_req_mask_b = 1,
64 .reg_ufs_apsrc_req_mask_b = 1,
65 .reg_ufs_vrf18_req_mask_b = 1,
66 .reg_ufs_ddr_en_mask_b = 1,
67 .reg_disp0_apsrc_req_mask_b = 1,
68 .reg_disp0_ddr_en_mask_b = 1,
69 .reg_disp1_apsrc_req_mask_b = 1,
70 .reg_disp1_ddr_en_mask_b = 1,
71 .reg_gce_infra_req_mask_b = 1,
72 .reg_gce_apsrc_req_mask_b = 1,
73 .reg_gce_vrf18_req_mask_b = 1,
74 .reg_gce_ddr_en_mask_b = 1,
75 .reg_apu_srcclkena_mask_b = 1,
76 .reg_apu_infra_req_mask_b = 1,
77 .reg_apu_apsrc_req_mask_b = 1,
78 .reg_apu_vrf18_req_mask_b = 1,
79 .reg_apu_ddr_en_mask_b = 1,
82 .reg_dvfsrc_event_trigger_mask_b = 1,
83 .reg_csyspwrreq_mask = 1,
84 .reg_mcupm_srcclkena_mask_b = 1,
85 .reg_mcupm_infra_req_mask_b = 1,
86 .reg_mcupm_apsrc_req_mask_b = 1,
87 .reg_mcupm_vrf18_req_mask_b = 1,
88 .reg_mcupm_ddr_en_mask_b = 1,
89 .reg_msdc0_srcclkena_mask_b = 1,
90 .reg_msdc0_infra_req_mask_b = 1,
91 .reg_msdc0_apsrc_req_mask_b = 1,
92 .reg_msdc0_vrf18_req_mask_b = 1,
93 .reg_msdc0_ddr_en_mask_b = 1,
94 .reg_msdc1_srcclkena_mask_b = 1,
95 .reg_msdc1_infra_req_mask_b = 1,
96 .reg_msdc1_apsrc_req_mask_b = 1,
97 .reg_msdc1_vrf18_req_mask_b = 1,
98 .reg_msdc1_ddr_en_mask_b = 1,
101 .ccif_event_mask_b = 0xFFF,
102 .reg_dramc0_md32_infra_req_mask_b = 1,
103 .reg_dramc1_md32_infra_req_mask_b = 1,
104 .reg_dramc0_md32_wakeup_mask = 1,
105 .reg_dramc1_md32_wakeup_mask = 1,
108 .reg_mcusys_merge_apsrc_req_mask_b = 0x11,
109 .reg_mcusys_merge_ddr_en_mask_b = 0x11,
110 .reg_msdc2_srcclkena_mask_b = 1,
111 .reg_msdc2_infra_req_mask_b = 1,
112 .reg_msdc2_apsrc_req_mask_b = 1,
113 .reg_msdc2_vrf18_req_mask_b = 1,
114 .reg_msdc2_ddr_en_mask_b = 1,
115 .reg_pcie_srcclkena_mask_b = 1,
116 .reg_pcie_infra_req_mask_b = 1,
117 .reg_pcie_apsrc_req_mask_b = 1,
118 .reg_pcie_vrf18_req_mask_b = 1,
119 .reg_pcie_ddr_en_mask_b = 1,
122 .reg_wakeup_event_mask = 0xEFFFFFFF,
125 .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
394 bool first_load_fw =
true;
399 first_load_fw =
false;
401 if (!first_load_fw) {
439 dmem_words = total_words - pmem_words;
444 __func__, (
long)ptr, pmem_words, dmem_words);
449 assert(pmem_words % 4 == 0);
450 assert(dmem_words % 4 == 0);
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
#define assert(statement)
void spm_parse_firmware(struct mtk_mcu *mcu)
#define printk(level,...)
#define setbits32(addr, set)
#define clrsetbits32(addr, clear, set)
#define clrbits32(addr, clear)
#define REGION_SIZE(name)
static void stopwatch_init(struct stopwatch *sw)
static long stopwatch_duration_msecs(struct stopwatch *sw)
#define BIOS_INFO
BIOS_INFO - Expected events.
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
int mtk_init_mcu(struct mtk_mcu *mcu)
static struct mtk_spm_regs *const mtk_spm
#define SPM_WAKEUP_EVENT_MASK_DEF
#define SPM_REGWR_CFG_KEY
#define POWER_ON_VAL1_DEF
#define SPM_FLAG_DISABLE_VCORE_DVS
#define REG_MD32_APB_INTERNAL_EN_LSB
#define SPM_ACK_CHK_3_SEL_HW_S1
#define ARMPLL_CLK_SEL_DEF
#define RG_PCM_WDT_WAKE_LSB
#define MD32PCM_DMA0_START_VAL
#define SPM_RESOURCE_ACK_CON0_DEF
#define SPM_BUS_PROTECT2_MASK_B_DEF
#define MD32PCM_DMA0_CON_VAL
#define SPM_ACK_CHK_3_HW_S1_CNT
#define SPM_FLAG_DISABLE_VCORE_DFS
#define SPM_RESOURCE_ACK_CON2_DEF
#define MD32PCM_CFGREG_SW_RSTN_RUN
#define SPM_RESOURCE_ACK_CON1_DEF
#define SPM_RESOURCE_ACK_CON3_DEF
#define SPM_WAKEUP_EVENT_MASK_BIT0
#define SPM_SYSCLK_SETTLE
#define SPM_BUS_PROTECT_MASK_B_DEF
#define RG_PCM_TIMER_EN_LSB
#define RG_AHBMIF_APBEN_LSB
#define SPM_DVS_DFS_LEVEL_DEF
#define SPM_FLAG_RUN_COMMON_SCENARIO
#define SPM_DVFS_LEVEL_DEF
#define SYS_TIMER_START_EN_LSB
#define REG_EVENT_LOCK_EN_LSB
#define REG_SPM_SRAM_ISOINT_B_LSB
#define SPM_EVENT_COUNTER_CLR_LSB
#define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B
#define SPM_DVFSRC_ENABLE_LSB
#define DDR_EN_DBC_CON0_DEF
#define SPM_DVFS_FORCE_ENABLE_LSB
#define MD32PCM_CFGREG_SW_RSTN_RESET
#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG
#define REG_SYSCLK1_SRC_MD2_SRCCLKENA
#define SPM_ACK_CHK_3_CON_CLR_ALL
#define REG_ALL_DDR_EN_DBC_EN_LSB
#define SPM_ACK_CHK_3_CON_EN
static void spm_code_swapping(void)
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
static void reset_spm(struct mtk_mcu *mcu)
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
static void spm_init_pcm_register(void)
static void spm_reset_and_init_pcm(void)
static void spm_set_sysclk_settle(void)
static void spm_register_init(void)
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
static struct mtk_mcu spm
#define SPM_SYSTEM_BASE_OFFSET
static const struct pwr_ctrl spm_init_ctrl
const char * firmware_name
uint32_t spm_bus_protect_mask_b
uint32_t spm_resource_ack_con2
uint32_t spm_resource_ack_con1
u32 md32pcm_cfgreg_sw_rstn
uint32_t spm_bus_protect2_mask_b
uint32_t spm_dvs_dfs_level
u32 spm_wakeup_event_ext_mask
uint32_t spm_ack_chk_timer_3
uint32_t spm_resource_ack_con0
u32 spm_wakeup_event_mask
uint32_t spm_ack_chk_sel_3
uint32_t spm_resource_ack_con3
uint32_t spm_ack_chk_con_3
uint8_t reg_dpmaif_srcclkena_mask_b
uint8_t reg_conn_vfe28_mask_b
u8 reg_infrasys_ddr_en_mask_b
uint8_t reg_bak_psri_apsrc_req_mask_b
u8 reg_sw2spm_int3_mask_b
uint8_t reg_msdc1_infra_req_mask_b
uint8_t reg_apu_vrf18_req_mask_b
uint8_t reg_apu_infra_req_mask_b
uint8_t reg_ufs_infra_req_mask_b
uint8_t reg_msdc0_vrf18_req_mask_b
uint8_t reg_ufs_srcclkena_mask_b
u8 reg_md_ddr_en_1_mask_b
u8 reg_srcclkeni0_infra_req_mask_b
u8 reg_md_srcclkena2infra_req_1_mask_b
uint8_t reg_msdc2_srcclkena_mask_b
uint8_t reg_gce_vrf18_req_mask_b
uint8_t reg_disp0_apsrc_req_mask_b
u8 reg_srcclkeni2_srcclkena_mask_b
uint8_t reg_cg_check_vrf18_req_mask_b
uint8_t reg_disp1_apsrc_req_mask_b
u8 reg_md_ddr_en_0_mask_b
uint8_t reg_ufs_apsrc_req_mask_b
u8 reg_cg_check_ddr_en_mask_b
u8 reg_md_srcclkena_1_mask_b
uint8_t reg_scp_infra_req_mask_b
uint8_t reg_msdc0_srcclkena_mask_b
uint32_t pcm_flags_cust_set
uint8_t reg_msdc2_apsrc_req_mask_b
uint8_t reg_pcie_vrf18_req_mask_b
u8 reg_dpmaif_ddr_en_mask_b
uint8_t reg_audio_dsp_apsrc_req_mask_b
u8 reg_dramc0_md32_wakeup_mask
uint8_t reg_spm_vrf18_req
u8 reg_msdc2_ddr_en_mask_b
uint8_t reg_msdc2_vrf18_req_mask_b
u8 reg_md32_infra_req_mask_b
uint8_t reg_gce_infra_req_mask_b
uint8_t reg_msdc0_infra_req_mask_b
u8 reg_mcupm_ddr_en_mask_b
uint8_t reg_conn_srcclkenb_mask_b
uint8_t reg_conn_srcclkenb2pwrap_mask_b
u8 reg_srcclkeni0_srcclkena_mask_b
u8 reg_disp0_ddr_en_mask_b
uint32_t reg_wakeup_event_mask
u8 reg_md32_srcclkena_mask_b
uint8_t reg_dpmaif_apsrc_req_mask_b
uint8_t reg_scp_vrf18_req_mask_b
u8 reg_md32_apsrc_req_mask_b
u8 reg_srcclkeni1_srcclkena_mask_b
uint8_t reg_apu_srcclkena_mask_b
u8 reg_spm_apsrc_req_reserved_mask_b
uint8_t reg_md_apsrc_1_sel
u8 reg_md_apsrc_req_0_mask_b
uint8_t reg_msdc2_infra_req_mask_b
u8 reg_pcie_ddr_en_mask_b
uint8_t reg_mcupm_vrf18_req_mask_b
u8 reg_sc_sspm2spm_wakeup_mask_b
u8 reg_disp1_ddr_en_mask_b
uint8_t reg_bak_psri_vrf18_req_mask_b
uint8_t reg_apu_apsrc_req_mask_b
u8 reg_dramc0_md32_vrf18_req_mask_b
u8 reg_dramc1_md32_vrf18_req_mask_b
uint32_t pcm_flags_cust_clr
uint8_t reg_conn_apsrc_sel
uint8_t reg_spm_adsp_mailbox_req
uint8_t reg_mcupm_apsrc_req_mask_b
uint8_t reg_audio_dsp_infra_req_mask_b
uint8_t reg_dpmaif_infra_req_mask_b
u8 reg_sc_adsp2spm_wakeup_mask_b
uint8_t reg_infrasys_apsrc_req_mask_b
u8 reg_md_vrf18_req_1_mask_b
u8 reg_md_vrf18_req_0_mask_b
uint8_t reg_mp1_cputop_idle_mask
uint8_t reg_conn_srcclkena_mask_b
uint8_t reg_audio_dsp_vrf18_req_mask_b
u8 reg_md_srcclkena2infra_req_0_mask_b
u8 reg_msdc0_ddr_en_mask_b
uint8_t reg_bak_psri_srcclkena_mask_b
u8 reg_sw2spm_int2_mask_b
u8 reg_bak_psri_ddr_en_mask_b
uint8_t reg_msdc1_vrf18_req_mask_b
u8 reg_spm_vrf18_req_reserved_mask_b
u8 reg_dramc0_md32_infra_req_mask_b
uint8_t reg_cg_check_srcclkena_mask_b
uint8_t reg_msdc1_apsrc_req_mask_b
uint8_t reg_md_apsrc_0_sel
uint8_t reg_gce_apsrc_req_mask_b
uint8_t reg_mcusys_idle_mask
uint8_t reg_spm_sspm_mailbox_req
uint8_t reg_mcupm_infra_req_mask_b
uint8_t reg_dpmaif_vrf18_req_mask_b
uint8_t reg_scp_apsrc_req_mask_b
uint8_t reg_pcie_apsrc_req_mask_b
uint8_t reg_conn_apsrc_req_mask_b
u8 reg_md_srcclkena_0_mask_b
uint8_t reg_cg_check_apsrc_req_mask_b
uint8_t reg_mcupm_srcclkena_mask_b
u8 reg_sw2spm_int0_mask_b
u8 reg_sc_scp2spm_wakeup_mask_b
u8 reg_dramc1_md32_infra_req_mask_b
u8 reg_spm_ddr_en_reserved_mask_b
uint8_t reg_ufs_vrf18_req_mask_b
u8 reg_spm_srcclkena_reserved_mask_b
uint8_t reg_conn_infra_req_mask_b
u8 reg_spm_infra_req_reserved_mask_b
uint32_t pcm_flags1_cust_set
u8 reg_md32_vrf18_req_mask_b
u8 reg_md_apsrc_req_1_mask_b
uint32_t reg_mcusys_merge_apsrc_req_mask_b
uint32_t pcm_flags1_cust_clr
uint8_t reg_pcie_srcclkena_mask_b
uint8_t reg_msdc1_srcclkena_mask_b
u8 reg_md_apsrc2infra_req_0_mask_b
uint8_t reg_conn_vrf18_req_mask_b
u8 reg_audio_dsp_ddr_en_mask_b
u8 reg_dramc1_md32_wakeup_mask
uint8_t reg_pcie_infra_req_mask_b
uint32_t reg_ext_wakeup_event_mask
uint8_t reg_msdc0_apsrc_req_mask_b
uint8_t reg_scp_srcclkena_mask_b
uint8_t reg_bak_psri_infra_req_mask_b
uint8_t reg_spm_sw_mailbox_req
uint8_t reg_spm_infra_req
uint8_t reg_spm_apsrc_req
u8 reg_srcclkeni2_infra_req_mask_b
u8 reg_md32_ddr_en_mask_b
u8 reg_srcclkeni1_infra_req_mask_b
uint8_t reg_dvfsrc_event_trigger_mask_b
u8 reg_msdc1_ddr_en_mask_b
u8 reg_sw2spm_int1_mask_b
u32 reg_mcusys_merge_ddr_en_mask_b
uint8_t reg_audio_dsp_srcclkena_mask_b
uint8_t reg_spm_scp_mailbox_req
uint8_t reg_mp0_cputop_idle_mask
u8 reg_md_apsrc2infra_req_1_mask_b
u8 reg_conn_ddr_en_mask_b