coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/mmio.h>
#include <bootstate.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/reset.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/acpi.h>
#include <amdblocks/gpio.h>
#include <amdblocks/i2c.h>
#include <amdblocks/smi.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
#include <soc/i2c.h>
#include <soc/iomap.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
#include <soc/amd_pci_int_defs.h>
#include <soc/pci_devs.h>
#include <types.h>
#include "chip.h"
Go to the source code of this file.
Functions | |
const struct irq_idx_name * | sb_get_apic_reg_association (size_t *size) |
static void | fch_clk_output_48Mhz (void) |
static void | sb_rfmux_config_override (void) |
static void | fch_init_acpi_ports (void) |
static void | al2ahb_clock_gate (void) |
static void | gpp_clk_setup (void) |
void | fch_init (void *chip_info) |
void | fch_final (void *chip_info) |
static void | set_pci_irqs (void *unused) |
BOOT_STATE_INIT_ENTRY (BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL) | |
Variables | |
static const struct irq_idx_name | irq_association [] |
Definition at line 164 of file fch.c.
References ALINK_AHB_ADDRESS, read8(), and write8().
Referenced by fch_init().
BOOT_STATE_INIT_ENTRY | ( | BS_DEV_ENABLE | , |
BS_ON_ENTRY | , | ||
set_pci_irqs | , | ||
NULL | |||
) |
Definition at line 88 of file fch.c.
References soc_amd_common_config::acp_config, soc_amd_picasso_config::acp_i2s_use_external_48mhz_osc, acp_config::acp_pin_cfg, BP_X48M0_OUTPUT_EN, soc_amd_picasso_config::common_config, config_of_soc, MISC_CLK_CNTL1, misc_read32(), and misc_write32().
Referenced by fch_init().
Definition at line 219 of file fch.c.
References acpi_pm_gpe_add_events_print_events(), al2ahb_clock_gate(), fch_clk_output_48Mhz(), fch_init_acpi_ports(), gpio_add_events(), gpp_clk_setup(), i2c_soc_init(), and sb_rfmux_config_override().
Definition at line 119 of file fch.c.
References ACPI_GPE0_BLK, ACPI_PM1_CNT_BLK, ACPI_PM_EVT_BLK, ACPI_PM_TMR_BLK, APM_CNT, CONFIG, configure_smi(), FORCE_SLPSTATE_RETRY, PM1_CNT_BLK, PM_ACPI_CONF, PM_ACPI_DECODE_STD, PM_ACPI_GLOBAL_EN, PM_ACPI_RTC_EN_EN, PM_ACPI_SMI_CMD, PM_ACPI_TIMER_EN_EN, PM_EVT_BLK, PM_GPE0_BLK, PM_PCI_CTRL, pm_read32(), pm_read8(), PM_RST_CTRL1, PM_TMR_BLK, pm_write16(), pm_write32(), pm_write8(), SLPTYPE_CONTROL_EN, SMI_MODE_SMI, SMITYPE_SLP_TYP, and SMITYPE_SMI_CMD_PORT.
Referenced by fch_init().
Definition at line 178 of file fch.c.
References config_of_soc, GPP_CLK0_REQ_SHIFT, GPP_CLK1_REQ_SHIFT, GPP_CLK2_REQ_SHIFT, GPP_CLK3_REQ_SHIFT, GPP_CLK4_REQ_SHIFT, GPP_CLK5_REQ_SHIFT, GPP_CLK6_REQ_SHIFT, GPP_CLK_CNTRL, soc_amd_picasso_config::gpp_clk_config, GPP_CLK_OFF, GPP_CLK_ON, GPP_CLK_OUTPUT_COUNT, GPP_CLK_REQ, GPP_CLK_REQ_EXT, GPP_CLK_REQ_MASK, GPP_CLK_REQ_OFF, GPP_CLK_REQ_ON, misc_read32(), and misc_write32().
Referenced by fch_init().
const struct irq_idx_name* sb_get_apic_reg_association | ( | size_t * | size | ) |
Definition at line 82 of file fch.c.
References ARRAY_SIZE, and irq_association.
Definition at line 103 of file fch.c.
References config_of_soc, PD_PORT_MUX_OFFSET, usb_pd_control::rfmux_config, usb_pd_control::rfmux_override_en, soc_amd_picasso_config::usb_pd_config_override, USB_PD_PORT_CONTROL, USB_PD_PORT_COUNT, USB_PD_RFMUX_OVERRIDE, and write32().
Referenced by fch_init().
Definition at line 244 of file fch.c.
References populate_pirq_data(), write_pci_cfg_irqs(), and write_pci_int_table().
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static |
Definition at line 36 of file fch.c.
Referenced by sb_get_apic_reg_association().