coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
bootblock_common.h
>
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#include <
device/pci_def.h
>
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#include <
device/pci_ops.h
>
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#include <
intelblocks/lpc_lib.h
>
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#include <
intelblocks/pcr.h
>
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#include <
soc/intel/common/block/lpc/lpc_def.h
>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <
superio/aspeed/ast2400/ast2400.h
>
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#include <
superio/aspeed/common/aspeed.h
>
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#include <
cpxsp_dl_gpio.h
>
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#define ASPEED_SIO_PORT 0x2E
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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static
void
enable_espi_lpc_io_windows
(
void
)
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{
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/*
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* Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
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* one is connected to debug header (SUART1) and another is used as SOL (SUART2).
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* For that end it is wired into BMC virtual port.
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*/
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uint16_t
lpciod = (
LPC_IOD_COMB_RANGE
|
LPC_IOD_COMA_RANGE
);
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uint16_t
lpcioe = (
LPC_IOE_SUPERIO_2E_2F
|
LPC_IOE_COMB_EN
|
LPC_IOE_COMA_EN
);
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/* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */
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pcr_or32
(
PID_DMI
,
PCR_DMI_LPCIOD
, lpciod);
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/* LPC I/O enable: com1 and com2 */
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pcr_or32
(
PID_DMI
,
PCR_DMI_LPCIOE
, lpcioe);
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/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
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pci_write_config16
(
PCH_DEV_LPC
,
LPC_IO_DECODE
, lpciod);
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pci_write_config16
(
PCH_DEV_LPC
,
LPC_IO_ENABLES
, lpcioe);
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}
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static
uint8_t
com_to_ast_sio
(
uint8_t
com)
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{
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switch
(com) {
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case
0:
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return
AST2400_SUART1
;
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case
1:
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return
AST2400_SUART2
;
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case
2:
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return
AST2400_SUART3
;
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case
4:
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return
AST2400_SUART4
;
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default
:
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return
AST2400_SUART1
;
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}
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}
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void
bootblock_mainboard_early_init
(
void
)
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{
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/* pre-configure Lewisburg PCH GPIO pads */
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gpio_configure_pads
(
early_gpio_table
,
ARRAY_SIZE
(
early_gpio_table
));
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/* Open IO windows */
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enable_espi_lpc_io_windows
();
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/* Configure appropriate physical port of SuperIO chip off BMC */
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const
pnp_devfn_t
serial_dev =
PNP_DEV
(
ASPEED_SIO_PORT
,
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com_to_ast_sio
(CONFIG_UART_FOR_CONSOLE));
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aspeed_enable_serial
(serial_dev, CONFIG_TTYS0_BASE);
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}
early_gpio_table
static const struct pad_config early_gpio_table[]
Definition:
gpio_early.c:7
PID_DMI
#define PID_DMI
Definition:
pcr_ids.h:23
aspeed.h
aspeed_enable_serial
void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase)
Definition:
early_serial.c:45
ast2400.h
AST2400_SUART3
#define AST2400_SUART3
Definition:
ast2400.h:11
AST2400_SUART1
#define AST2400_SUART1
Definition:
ast2400.h:6
AST2400_SUART4
#define AST2400_SUART4
Definition:
ast2400.h:12
AST2400_SUART2
#define AST2400_SUART2
Definition:
ast2400.h:7
bootblock_common.h
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
pcr.h
pcr_or32
void pcr_or32(uint8_t pid, uint16_t offset, uint32_t ordata)
Definition:
pcr.c:184
cpxsp_dl_gpio.h
pci_ops.h
pci_write_config16
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
Definition:
pci_ops.h:70
bootblock_mainboard_early_init
__weak void bootblock_mainboard_early_init(void)
Definition:
bootblock.c:16
lpc_def.h
LPC_IOD_COMA_RANGE
#define LPC_IOD_COMA_RANGE
Definition:
lpc_def.h:12
LPC_IO_ENABLES
#define LPC_IO_ENABLES
Definition:
lpc_def.h:16
LPC_IOD_COMB_RANGE
#define LPC_IOD_COMB_RANGE
Definition:
lpc_def.h:13
LPC_IO_DECODE
#define LPC_IO_DECODE
Definition:
lpc_def.h:9
lpc_lib.h
LPC_IOE_COMB_EN
#define LPC_IOE_COMB_EN
Definition:
lpc_lib.h:24
LPC_IOE_SUPERIO_2E_2F
#define LPC_IOE_SUPERIO_2E_2F
Definition:
lpc_lib.h:17
LPC_IOE_COMA_EN
#define LPC_IOE_COMA_EN
Definition:
lpc_lib.h:25
enable_espi_lpc_io_windows
static void enable_espi_lpc_io_windows(void)
Definition:
bootblock.c:19
PCR_DMI_LPCIOD
#define PCR_DMI_LPCIOD
Definition:
bootblock.c:16
PCR_DMI_LPCIOE
#define PCR_DMI_LPCIOE
Definition:
bootblock.c:17
com_to_ast_sio
static uint8_t com_to_ast_sio(uint8_t com)
Definition:
bootblock.c:39
ASPEED_SIO_PORT
#define ASPEED_SIO_PORT
Definition:
bootblock.c:15
pci_def.h
PNP_DEV
#define PNP_DEV(PORT, FUNC)
Definition:
pnp_type.h:10
pnp_devfn_t
u32 pnp_devfn_t
Definition:
pnp_type.h:8
gpio_configure_pads
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition:
gpio.c:307
PCH_DEV_LPC
#define PCH_DEV_LPC
Definition:
pci_devs.h:224
uint16_t
unsigned short uint16_t
Definition:
stdint.h:11
uint8_t
unsigned char uint8_t
Definition:
stdint.h:8
src
mainboard
ocp
deltalake
bootblock.c
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