pmc.c

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/* SPDX-License-Identifier: GPL-2.0-only */
 
#include <bootstate.h>
#include <console/console.h>
#include <device/mmio.h>
#include <device/device.h>
#include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/soc_chip.h>
 
static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
{
        uint32_t reg;
        uint8_t *pmcbase = pmc_mmio_regs();
 
        printk(BIOS_DEBUG, "%sabling Deep S%c\n",
                enable ? "En" : "Dis", sx + '0');
        reg = read32(pmcbase + offset);
        if (enable)
                reg |= mask;
        else
                reg &= ~mask;
        write32(pmcbase + offset, reg);
}
 
static void config_deep_s5(int on_ac, int on_dc)
{
        /* Treat S4 the same as S5. */
        config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
        config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
        config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
        config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
}
 
static void config_deep_s3(int on_ac, int on_dc)
{
        config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
        config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
}
 
static void config_deep_sx(uint32_t deepsx_config)
{
        uint32_t reg;
        uint8_t *pmcbase = pmc_mmio_regs();
 
        reg = read32(pmcbase + DSX_CFG);
        reg &= ~DSX_CFG_MASK;
        reg |= deepsx_config;
        write32(pmcbase + DSX_CFG, reg);
}
 
static void pmc_init(void *unused)
{
        const config_t *config = config_of_soc();
 
        rtc_init();
 
        pmc_set_power_failure_state(true);
        pmc_gpe_init();
 
        pmc_set_acpi_mode();
 
        config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
        config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
        config_deep_sx(config->deep_sx_config);
 
        /*
         * Disable ACPI PM timer based on Kconfig
         *
         * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
         * Disabling ACPI PM timer also switches off TCO
         */
        if (!CONFIG(USE_PM_ACPI_TIMER))
                setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
 
        /*
         * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits)
         *
         * Perform the PMCON status bit clear operation from `.final`
         * to cover any such chances where later boot stage requested a global
         * reset and PMCON status bit remains set.
         */
        pmc_clear_pmcon_sts();
}
 
/*
* Initialize PMC controller.
*
* PMC controller gets hidden from PCI bus during FSP-Silicon init call.
* Hence PCI enumeration can't be used to initialize bus device and
* allocate resources.
*/
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);