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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | EHCI_BAR_INDEX 0x10 |
#define | PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ |
#define | pci_ehci_read_resources pci_dev_read_resources |
Functions | |
pci_devfn_t | pci_ehci_dbg_dev (unsigned int hcd_idx) |
u8 * | pci_ehci_base_regs (pci_devfn_t dev) |
void | pci_ehci_dbg_set_port (pci_devfn_t dev, unsigned int port) |
#define EHCI_BAR_INDEX 0x10 |
Definition at line 10 of file pci_ehci.h.
#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ |
Definition at line 11 of file pci_ehci.h.
#define pci_ehci_read_resources pci_dev_read_resources |
Definition at line 22 of file pci_ehci.h.
u8* pci_ehci_base_regs | ( | pci_devfn_t | dev | ) |
Definition at line 105 of file pci_ehci.c.
References base, EHCI_BAR_INDEX, HC_LENGTH, pci_s_read_config32(), and read32().
Referenced by pci_ehci_dbg_set_port().
pci_devfn_t pci_ehci_dbg_dev | ( | unsigned int | hcd_idx | ) |
Definition at line 14 of file enable_usbdebug.c.
References CONFIG, outb(), PCI_CLASS_REVISION, PCI_DEV, PCI_EHCI_CLASSCODE, pci_read_config32(), PM_DATA, PM_INDEX, pm_io_write8(), PM_USB_ALL_CONTROLLERS, PM_USB_ENABLE, and SOC_EHCI1_DEV.
Referenced by ehci_debug_hw_enable(), and ehci_debug_select_port().
void pci_ehci_dbg_set_port | ( | pci_devfn_t | dev, |
unsigned int | port | ||
) |
Definition at line 20 of file enable_usbdebug.c.
References DEBUG_PORT_ENABLE, DEBUG_PORT_MASK, DEBUG_PORT_SELECT_SHIFT, DEBUGPORT_MISC_CONTROL, EHCI_HUB_CONFIG4, pci_ehci_base_regs(), pci_read_config32(), pci_write_config32(), read32(), SOC_EHCI1_DEV, value, and write32().
Referenced by ehci_debug_select_port().