coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <
bootblock_common.h
>
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#include <
device/pnp_ops.h
>
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#include <
northbridge/intel/x4x/x4x.h
>
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#include <
southbridge/intel/i82801gx/i82801gx.h
>
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#include <
superio/nuvoton/common/nuvoton.h
>
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#include <
superio/nuvoton/nct6776/nct6776.h
>
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#include <
superio/winbond/common/winbond.h
>
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#include <
superio/winbond/w83627dhg/w83627dhg.h
>
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#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
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#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
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void
bootblock_mainboard_early_init
(
void
)
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{
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/* Set GPIOs on superio, enable UART */
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if
(
CONFIG
(SUPERIO_NUVOTON_NCT6776)) {
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nuvoton_pnp_enter_conf_state
(
SERIAL_DEV_R2
);
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pnp_set_logical_device
(
SERIAL_DEV_R2
);
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pnp_write_config
(
SERIAL_DEV_R2
, 0x1c, 0x80);
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pnp_write_config
(
SERIAL_DEV_R2
, 0x27, 0x80);
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pnp_write_config
(
SERIAL_DEV_R2
, 0x2a, 0x60);
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nuvoton_pnp_exit_conf_state
(
SERIAL_DEV_R2
);
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nuvoton_enable_serial
(
SERIAL_DEV_R2
, CONFIG_TTYS0_BASE);
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}
else
{
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winbond_enable_serial
(
SERIAL_DEV_R1
, CONFIG_TTYS0_BASE);
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}
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/* IRQ routing */
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RCBA16
(
D31IR
) = 0x0132;
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RCBA16
(
D29IR
) = 0x0237;
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}
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void
mb_get_spd_map
(
u8
spd_map[4])
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{
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spd_map[0] = 0x50;
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spd_map[2] = 0x52;
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}
bootblock_common.h
CONFIG
@ CONFIG
Definition:
dsi_common.h:201
i82801gx.h
bootblock_mainboard_early_init
void bootblock_mainboard_early_init(void)
Definition:
early_init.c:11
mb_get_spd_map
void mb_get_spd_map(u8 spd_map[4])
Definition:
early_init.c:27
SERIAL_DEV_R2
#define SERIAL_DEV_R2
Definition:
early_init.c:12
SERIAL_DEV_R1
#define SERIAL_DEV_R1
Definition:
early_init.c:13
nct6776.h
nuvoton_pnp_enter_conf_state
void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
Definition:
early_serial.c:33
nuvoton_enable_serial
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
Definition:
early_serial.c:48
nuvoton_pnp_exit_conf_state
void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
Definition:
early_serial.c:41
nuvoton.h
pnp_set_logical_device
void pnp_set_logical_device(struct device *dev)
Definition:
pnp_device.c:59
pnp_write_config
void pnp_write_config(struct device *dev, u8 reg, u8 value)
Definition:
pnp_device.c:38
pnp_ops.h
D31IR
#define D31IR
Definition:
rcba.h:87
D29IR
#define D29IR
Definition:
rcba.h:89
RCBA16
#define RCBA16(x)
Definition:
rcba.h:13
u8
uint8_t u8
Definition:
stdint.h:45
winbond_enable_serial
void winbond_enable_serial(pnp_devfn_t dev, u16 iobase)
Definition:
early_init.c:47
w83627dhg.h
winbond.h
x4x.h
src
mainboard
asrock
g41c-gs
early_init.c
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