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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/mmio.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/sata.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "chip.h"
Go to the source code of this file.
Typedefs | |
typedef struct soc_intel_baytrail_config | config_t |
Functions | |
static void | sir_write (struct device *dev, int idx, u32 value) |
static void | sata_init (struct device *dev) |
static void | sata_enable (struct device *dev) |
Variables | |
static struct device_operations | sata_ops |
static const unsigned short | pci_device_ids [] |
static const struct pci_driver baytrail_sata | __pci_driver |
typedef struct soc_intel_baytrail_config config_t |
Definition at line 139 of file sata.c.
References config, config_of(), pci_read_config16(), pci_read_config32(), pci_read_config8(), pci_write_config16(), pci_write_config32(), pci_write_config8(), sir_write(), and southcluster_enable_dev().
Referenced by i82801gx_enable().
Definition at line 24 of file sata.c.
References BIOS_DEBUG, config, config_of(), PCI_BASE_ADDRESS_5, pci_read_config16(), pci_read_config32(), pci_read_config8(), pci_write_config16(), pci_write_config32(), pci_write_config8(), printk, read32(), read8(), udelay(), write32(), and write8().
Definition at line 18 of file sata.c.
References pci_write_config32(), SATA_SIRD, SATA_SIRI, and value.
Referenced by sata_enable().
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