coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
watchdog.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_def.h>
7 #include <device/pci_ops.h>
10 #include <watchdog.h>
11 
12 /*
13  * Disable ICH-NM10-PCH watchdog timer
14  */
15 void watchdog_off(void)
16 {
17  unsigned int value;
18  struct device *dev;
19 
20  /* Get LPC device. */
21  dev = pcidev_on_root(0x1f, 0);
22 
24 
25  /* Disable interrupt. */
28 
29  /* Disable the watchdog timer. */
31  value |= TCO_TMR_HLT;
33 
34  /* Clear TCO timeout status. */
37 
38  printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");
39 }
pte_t value
Definition: mmu.c:91
#define SECOND_TO_STS
Definition: pm.h:227
#define printk(level,...)
Definition: stdlib.h:16
DEVTREE_CONST struct device * pcidev_on_root(uint8_t dev, uint8_t fn)
Definition: device_const.c:260
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
Definition: pci_ops.h:52
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
Definition: pci_ops.h:70
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
#define PCI_COMMAND_INT_DISABLE
Definition: pci_def.h:21
#define PCI_COMMAND
Definition: pci_def.h:10
void write_pmbase16(const u8 addr, const u16 val)
Definition: pmbase.c:43
u16 read_pmbase16(const u8 addr)
Definition: pmbase.c:64
#define TCO_TMR_HLT
Definition: smbus.h:14
#define TCO2_STS
Definition: smbus.h:9
#define TCO1_CNT
Definition: smbus.h:12
#define TCO1_STS
Definition: smbus.h:7
#define TCO1_TIMEOUT
Definition: pch.h:468
#define PMBASE_TCO_OFFSET
Definition: tco.h:6
void watchdog_off(void)
Definition: watchdog.c:15
Definition: device.h:107