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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <acpi/acpi.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
#include <elog.h>
#include <soc/nvs.h>
#include <soc/pm.h>
#include <soc/gpio.h>
#include <variant/onboard.h>
Go to the source code of this file.
Macros | |
#define | WAKE_GPIO_EN SUS_GPIO_EN0 |
#define | GPIO_SUS7_WAKE_MASK (1 << 12) |
#define | GPIO_SUS1_WAKE_MASK (1 << 13) |
Functions | |
int | mainboard_io_trap_handler (int smif) |
static uint8_t | mainboard_smi_ec (void) |
void | mainboard_smi_gpi (uint32_t alt_gpio_smi) |
void | mainboard_smi_sleep (uint8_t slp_typ) |
int | mainboard_smi_apmc (uint8_t apmc) |
#define GPIO_SUS1_WAKE_MASK (1 << 13) |
Definition at line 20 of file smihandler.c.
#define GPIO_SUS7_WAKE_MASK (1 << 12) |
Definition at line 19 of file smihandler.c.
#define WAKE_GPIO_EN SUS_GPIO_EN0 |
Definition at line 18 of file smihandler.c.
int mainboard_io_trap_handler | ( | int | smif | ) |
Definition at line 22 of file smihandler.c.
References BIOS_DEBUG, gnvs, printk, and global_nvs::smif.
int mainboard_smi_apmc | ( | uint8_t | apmc | ) |
Definition at line 138 of file smihandler.c.
References APM_CNT_ACPI_DISABLE, APM_CNT_ACPI_ENABLE, EC_HOST_EVENT_NONE, google_chromeec_get_event(), google_chromeec_set_sci_mask(), google_chromeec_set_smi_mask(), MAINBOARD_EC_SCI_EVENTS, and MAINBOARD_EC_SMI_EVENTS.
Definition at line 44 of file smihandler.c.
References BIOS_DEBUG, EC_HOST_EVENT_LID_CLOSED, elog_gsmi_add_event_byte(), ELOG_TYPE_EC_EVENT, get_pmbase(), google_chromeec_get_event(), inl(), outl(), PM1_CNT, pmbase, printk, SLP_EN, SLP_TYP_S5, and SLP_TYP_SHIFT.
Referenced by mainboard_smi_gpi().
Definition at line 72 of file smihandler.c.
References EC_SMI_GPI, and mainboard_smi_ec().
Definition at line 81 of file smihandler.c.
References ACPI_S3, ACPI_S5, addr, COMMUNITY_OFFSET_GPNORTH, EC_HOST_EVENT_NONE, enable_gpe(), gnvs, google_chromeec_get_event(), google_chromeec_set_sci_mask(), google_chromeec_set_smi_mask(), google_chromeec_set_usb_charge_mode(), google_chromeec_set_wake_mask(), GPIO_SUS1_WAKE_MASK, GPIO_SUS7_WAKE_MASK, GPIO_WAKE_MASK_REG0, IO_BASE_ADDRESS, lpc_set_low_power(), MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS, mask, read32(), global_nvs::s3u0, global_nvs::s3u1, global_nvs::s5u0, global_nvs::s5u1, USB_CHARGE_MODE_DISABLED, WAKE_GPIO_EN, and write32().