coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
variants.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef __BASEBOARD_VARIANTS_H__
4 #define __BASEBOARD_VARIANTS_H__
5 
6 #include <soc/gpio.h>
7 #include <stdint.h>
8 
9 /*
10  * The next set of functions return the gpio table and fill in the number of
11  * entries for each table.
12  */
13 const struct pad_config *variant_gpio_table(size_t *num);
14 const struct pad_config *variant_early_gpio_table(size_t *num);
15 
16 /*
17  * Callback to get GPIOs to configure in romstage before memory training is
18  * performed.
19  */
20 const struct pad_config *variant_romstage_gpio_table(size_t *num);
21 
22 /* Config gpio by different sku id */
23 const struct pad_config *variant_sku_gpio_table(size_t *num);
24 
29 };
30 
31 struct memory_params {
32  enum memory_type type;
33  const void *dq_map;
34  size_t dq_map_size;
35  const void *dqs_map;
36  size_t dqs_map_size;
37  const void *rcomp_resistor;
39  const void *rcomp_target;
42 
43  /* Enable SA overclocking mailbox commands */
45 
46  /* The voltage offset applied to the SA in mV. 1000(mV) = Maximum */
48 
49  /* This would be set to true if only have single DDR channel */
51 };
52 
53 void variant_memory_params(struct memory_params *p);
54 int variant_memory_sku(void);
55 void variant_devtree_update(void);
57 void variant_smi_sleep(u8 slp_typ);
58 
59 struct nhlt;
60 void variant_nhlt_init(struct nhlt *nhlt);
61 void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id,
62  uint32_t *oem_revision);
63 
65 /*
66  * Read google_chromeec_event_info structure from variant to set different masks
67  * on the EC e.g. SCI, S3, S5, S0ix, SMI.
68  */
70 
71 #endif /* __BASEBOARD_VARIANTS_H__ */
const struct pad_config * variant_romstage_gpio_table(size_t *num)
Definition: gpio.c:210
const struct pad_config * variant_gpio_table(size_t *num)
Definition: gpio.c:406
const struct mb_cfg * variant_memory_params(void)
Definition: memory.c:67
void variant_devtree_update(void)
Definition: mainboard.c:86
const struct pad_config * variant_early_gpio_table(size_t *num)
Definition: gpio.c:204
int variant_memory_sku(void)
Definition: memory.c:74
void variant_smi_sleep(u8 slp_typ)
Definition: smihandler.c:52
void variant_nhlt_init(struct nhlt *nhlt)
Definition: nhlt.c:7
void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, uint32_t *oem_revision)
Definition: nhlt.c:16
uint8_t variant_board_sku(void)
Definition: mainboard.c:172
const struct pad_config * variant_sku_gpio_table(size_t *num)
Definition: gpio.c:408
memory_type
Definition: variants.h:25
@ MEMORY_DDR4
Definition: variants.h:27
@ MEMORY_LPDDR3
Definition: variants.h:26
@ MEMORY_COUNT
Definition: variants.h:28
const struct google_chromeec_event_info * variant_get_event_info(void)
Definition: ec.c:9
unsigned short uint16_t
Definition: stdint.h:11
unsigned int uint32_t
Definition: stdint.h:14
uint8_t u8
Definition: stdint.h:45
size_t dq_map_size
Definition: variants.h:34
enum memory_type type
Definition: variants.h:32
const void * rcomp_target
Definition: variants.h:39
size_t dqs_map_size
Definition: variants.h:36
uint16_t sa_voltage_offset_val
Definition: variants.h:47
bool enable_sa_oc_support
Definition: variants.h:44
const void * rcomp_resistor
Definition: variants.h:37
bool single_channel
Definition: variants.h:50
size_t rcomp_resistor_size
Definition: variants.h:38
const void * dq_map
Definition: variants.h:33
bool use_sec_spd
Definition: variants.h:41
size_t rcomp_target_size
Definition: variants.h:40
const void * dqs_map
Definition: variants.h:35
Definition: nhlt.h:287