coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
struct | cpu_power_limits |
struct | system_power_limits |
struct | psys_config |
Enumerations | |
enum | s0ix_entry { S0IX_EXIT , S0IX_ENTRY } |
enum s0ix_entry |
Enumerator | |
---|---|
S0IX_EXIT | |
S0IX_ENTRY |
Definition at line 27 of file variants.h.
Definition at line 86 of file mainboard.c.
const struct pad_config* variant_early_gpio_table | ( | size_t * | num | ) |
Definition at line 158 of file mainboard.c.
Referenced by mainboard_fill_ssdt().
Definition at line 184 of file mainboard.c.
Referenced by mainboard_final().
void variant_generate_s0ix_hook | ( | enum s0ix_entry | entry | ) |
Definition at line 163 of file mainboard.c.
References acpigen_soc_clear_tx_gpio(), acpigen_soc_set_tx_gpio(), NFC_POWER, S0IX_ENTRY, and S0IX_EXIT.
Referenced by mainboard_generate_s0ix_hook().
Definition at line 32 of file memory.c.
References MEM_TOPO_DIMM_MODULE, MEM_TOPO_MEMORY_DOWN, and variant_memory_sku().
Referenced by mainboard_memory_init_params().
const struct pad_config* variant_gpio_override_table | ( | size_t * | num | ) |
Definition at line 198 of file gpio.c.
References ARRAY_SIZE, board_id(), board_id0_1_overrides, board_id0_overrides, BOARD_ID_UNKNOWN, NULL, and override_gpio_table.
Referenced by mainboard_init().
const struct pad_config* variant_gpio_table | ( | size_t * | num | ) |
Definition at line 67 of file mainboard.c.
Referenced by mainboard_init().
Definition at line 27 of file memory.c.
References gpio_get(), GPP_E13, and GPP_E5.
Referenced by mainboard_memory_init_params().
const struct pad_config* variant_romstage_gpio_table | ( | size_t * | num | ) |
Definition at line 19 of file bootblock.c.
References ARRAY_SIZE, BIOS_INFO, configure_descriptor(), FW_CONFIG, fw_config_probe(), and printk.
Referenced by bootblock_mainboard_init().
void variant_update_power_limits | ( | const struct cpu_power_limits * | limits, |
size_t | num_entries | ||
) |
Definition at line 51 of file ramstage.c.
References BIOS_INFO, device::chip_info, config, config_of_soc, cpu_tdp, DEV_PTR, DIV_ROUND_UP, get_cpu_tdp(), get_sku_index(), limits, dptf_power_limit_config::max_power, mchid, MILLIWATTS_TO_WATTS, dptf_power_limit_config::min_power, PCI_DEV, PCI_DEVICE_ID, pci_s_read_config16(), dptf_power_limits::pl1, cpu_power_limits::pl1_max_power, cpu_power_limits::pl1_min_power, dptf_power_limits::pl2, cpu_power_limits::pl2_max_power, cpu_power_limits::pl2_min_power, printk, soc_power_limits_config::tdp_pl2_override, and soc_power_limits_config::tdp_pl4.
Referenced by variant_devtree_update().
void variant_update_psys_power_limits | ( | const struct cpu_power_limits * | limits, |
const struct system_power_limits * | sys_limits, | ||
size_t | num_entries, | ||
const struct psys_config * | config | ||
) |
Definition at line 96 of file ramstage.c.
References BIOS_INFO, psys_config::bj_volts_mv, config_of_soc, DEV_PTR, DIV_ROUND_UP, psys_config::efficiency, get_sku_index(), google_chromeec_get_usb_pd_power_info(), limits, MILLIWATTS_TO_WATTS, printk, psys_config::psys_imax_ma, system_power_limits::psys_pl2_power, soc_power_limits_config::psys_pmax, SET_PSYSPL2, sys_limits, soc_power_limits_config::tdp_pl2_override, soc_power_limits_config::tdp_pl4, soc_power_limits_config::tdp_psyspl2, type, and USB_CHG_TYPE_PD.
Referenced by variant_devtree_update().
void variant_update_soc_chip_config | ( | struct soc_intel_alderlake_config * | config | ) |
Definition at line 62 of file mainboard.c.
References AUDIO, config, FW_CONFIG, fw_config_probe(), GPP_A19, and GPP_A20.
Referenced by mainboard_update_soc_chip_config().