coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
struct | memory_params |
Enumerations | |
enum | memory_type { MEMORY_LPDDR3 , MEMORY_DDR4 , MEMORY_COUNT } |
Functions | |
const struct pad_config * | variant_gpio_table (size_t *num) |
const struct pad_config * | variant_early_gpio_table (size_t *num) |
const struct pad_config * | variant_romstage_gpio_table (size_t *num) |
const struct pad_config * | variant_sku_gpio_table (size_t *num) |
void | variant_memory_params (struct memory_params *p) |
int | variant_memory_sku (void) |
void | variant_devtree_update (void) |
uint32_t | variant_board_sku (void) |
void | variant_smi_sleep (u8 slp_typ) |
void | variant_nhlt_init (struct nhlt *nhlt) |
void | variant_nhlt_oem_overrides (const char **oem_id, const char **oem_table_id, uint32_t *oem_revision) |
const struct google_chromeec_event_info * | variant_get_event_info (void) |
enum memory_type |
Enumerator | |
---|---|
MEMORY_LPDDR3 | |
MEMORY_DDR4 | |
MEMORY_COUNT |
Definition at line 25 of file variants.h.
Definition at line 172 of file mainboard.c.
Definition at line 86 of file mainboard.c.
const struct pad_config* variant_early_gpio_table | ( | size_t * | num | ) |
const struct google_chromeec_event_info* variant_get_event_info | ( | void | ) |
Definition at line 9 of file ec.c.
References board_id(), EC_HOST_EVENT_MASK, EC_HOST_EVENT_MKBP, info, MAINBOARD_EC_LOG_EVENTS, MAINBOARD_EC_S0IX_WAKE_EVENTS, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS, MAINBOARD_EC_SCI_EVENTS, and MAINBOARD_EC_SMI_EVENTS.
Referenced by elog_gsmi_cb_mainboard_log_wake_source(), mainboard_ec_init(), mainboard_smi_apmc(), and mainboard_smi_sleep().
const struct pad_config* variant_gpio_table | ( | size_t * | num | ) |
void variant_memory_params | ( | struct memory_params * | p | ) |
Definition at line 29 of file memory.c.
References assert, dq_map, memory_params::dq_map, memory_params::dq_map_size, dqs_map, memory_params::dqs_map, memory_params::dqs_map_size, memory_params::enable_sa_oc_support, fill_ddr4_memory_params(), fill_lpddr3_memory_params(), gpio_get(), gpio_input_pulldown(), GPIO_MEM_CONFIG_4, GPP_D10, MEMORY_LPDDR3, memset(), rcomp_resistor, memory_params::rcomp_resistor, memory_params::rcomp_resistor_size, rcomp_target, memory_params::rcomp_target, rcomp_target_samsung_c_die, memory_params::rcomp_target_size, memory_params::sa_voltage_offset_val, SAMSUNG_C_DIE_2G, SAMSUNG_C_DIE_4G, memory_params::single_channel, SKU_0_NAUTILUS, spd_index, memory_params::type, variant_board_sku(), and variant_memory_sku().
const struct pad_config* variant_romstage_gpio_table | ( | size_t * | num | ) |
Definition at line 210 of file gpio.c.
References ARRAY_SIZE, gpio_set_stage_rom, NULL, and romstage_gpio_table.
Referenced by mainboard_memory_init_params(), and mainboard_romstage_entry().
const struct pad_config* variant_sku_gpio_table | ( | size_t * | num | ) |
Definition at line 52 of file smihandler.c.
References ACPI_S5, ELAN_ENABLE_OFF_DELAY, ELAN_RESET_OFF_DELAY, ELAN_STOP_OFF_DELAY, FP_PWR_ENABLE, google_chromeec_get_board_sku(), gpio_set(), is_lte_sku(), LTE3_PWROFF_L, mdelay(), power_off_lte_module(), SKU_17_LTE, SKU_18_LTE_TS, SKU_1_LTE, SKU_1_NAUTILUS_LTE, SKU_37_DROID, SKU_38_DROID, SKU_39_1A2C_360_LTE_TS_NO_STYLUES, SKU_39_DROID, SKU_3_LTE_2CAM, SKU_40_DROID, sku_id(), TOUCH_DISABLE, TOUCH_ENABLE, TOUCH_RESET, TS_ENABLE, and variant_board_sku().
Referenced by mainboard_smi_sleep().