coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
emmc.c File Reference
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <reg_script.h>
#include <soc/device_nvs.h>
#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include "chip.h"
Include dependency graph for emmc.c:

Go to the source code of this file.

Functions

static void emmc_init (struct device *dev)
 

Variables

static const struct reg_script emmc_ops []
 
static struct device_operations device_ops
 
static const struct pci_driver southcluster __pci_driver
 

Function Documentation

◆ emmc_init()

static void emmc_init ( struct device dev)
static

Definition at line 33 of file emmc.c.

Variable Documentation

◆ __pci_driver

const struct pci_driver southcluster __pci_driver
static
Initial value:
= {
.ops = &device_ops,
.vendor = PCI_VID_INTEL,
.device = MMC45_DEVID,
}
static struct device_operations device_ops
Definition: emmc.c:44
#define PCI_VID_INTEL
Definition: pci_ids.h:2157
#define MMC45_DEVID
Definition: pci_devs.h:119

Definition at line 33 of file emmc.c.

◆ device_ops

struct device_operations device_ops
static
Initial value:
= {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = emmc_init,
.ops_pci = &soc_pci_ops,
}
static void emmc_init(struct device *dev)
Definition: emmc.c:33
void pci_dev_enable_resources(struct device *dev)
Definition: pci_device.c:721
void pci_dev_read_resources(struct device *dev)
Definition: pci_device.c:534
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691
struct pci_operations soc_pci_ops
Definition: chip.c:51

Definition at line 33 of file emmc.c.

◆ emmc_ops

const struct reg_script emmc_ops[]
static
Initial value:
= {
REG_PCI_OR32(0xa8, (1 << 24)),
REG_PCI_WRITE32(0xa0, 0x446cc801),
REG_PCI_WRITE32(0xa4, 0x80000807),
REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)),
REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c),
}
#define IOSF_PORT_SCORE
Definition: iosf.h:104
#define IOSF_PORT_CCU
Definition: iosf.h:116
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
#define REG_PCI_OR32(reg_, value_)
Definition: reg_script.h:187
#define REG_RES_WRITE8(bar_, reg_, value_)
Definition: reg_script.h:321
#define REG_PCI_WRITE32(reg_, value_)
Definition: reg_script.h:169
#define REG_SCRIPT_END
Definition: reg_script.h:427

Definition at line 1 of file emmc.c.