coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Data Structures | Macros | Functions | Variables
clk.h File Reference
#include <soc/cpu.h>
#include <soc/dmc.h>
#include <soc/pinmux.h>
#include <stdint.h>
Include dependency graph for clk.h:

Go to the source code of this file.

Data Structures

struct  exynos5420_clock
 
struct  exynos5_mct
 
struct  st_epll_con_val
 
struct  arm_clk_ratios
 

Macros

#define APLL   0
 
#define MPLL   1
 
#define EPLL   2
 
#define HPLL   3
 
#define VPLL   4
 
#define BPLL   5
 
#define RPLL   6
 
#define SPLL   7
 
#define CPLL   8
 
#define DPLL   9
 
#define IPLL   10
 
#define MCT_HZ   24000000
 
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT   29 /* EPLL Locked bit position*/
 
#define EPLL_SRC_CLOCK   24000000 /*24 MHz Crystal Input */
 
#define TIMEOUT_EPLL_LOCK   1000
 
#define AUDIO_0_RATIO_MASK   0x0f
 
#define AUDIO_1_RATIO_MASK   0x0f
 
#define CLK_SRC_PERIC1   0x254
 
#define AUDIO1_SEL_MASK   0xf
 
#define CLK_SRC_AUDIOCDCLK1   0x0
 
#define CLK_SRC_XXTI   0x1
 
#define CLK_SRC_SCLK_EPLL   0x7
 
#define EPLL_CON0_MDIV_MASK   0x1ff
 
#define EPLL_CON0_PDIV_MASK   0x3f
 
#define EPLL_CON0_SDIV_MASK   0x7
 
#define EPLL_CON0_LOCKED_SHIFT   29
 
#define EPLL_CON0_MDIV_SHIFT   16
 
#define EPLL_CON0_PDIV_SHIFT   8
 
#define EPLL_CON0_SDIV_SHIFT   0
 
#define EPLL_CON0_LOCK_DET_EN_SHIFT   28
 
#define EPLL_CON0_LOCK_DET_EN_MASK   1
 

Functions

unsigned long get_pll_clk (int pllreg)
 
unsigned long get_arm_clk (void)
 
unsigned long get_pwm_clk (void)
 
unsigned long get_uart_clk (int dev_index)
 
void set_mmc_clk (int dev_index, unsigned int div)
 
unsigned long clock_get_periph_rate (enum periph_id peripheral)
 get the clk frequency of the required peripheral More...
 
int clock_set_mshci (enum periph_id peripheral)
 
int clock_set_dwmci (enum periph_id peripheral)
 
int clock_epll_set_rate (unsigned long rate)
 
void clock_select_i2s_clk_source (void)
 
int clock_set_i2s_clk_prescaler (unsigned int src_frq, unsigned int dst_frq)
 
 check_member (exynos5420_clock, cmu_kfc_version, 0x2bff0)
 
 check_member (exynos5_mct, l1_wstat, 0x440)
 
void clock_ll_set_pre_ratio (enum periph_id periph_id, unsigned int divisor)
 Low-level function to set the clock pre-ratio for a peripheral. More...
 
void clock_ll_set_ratio (enum periph_id periph_id, unsigned int divisor)
 Low-level function to set the clock ratio for a peripheral. More...
 
int clock_set_rate (enum periph_id periph_id, unsigned int rate)
 Low-level function that selects the best clock scalars for a given rate and sets up the given peripheral's clock accordingly. More...
 
void clock_gate (void)
 
struct arm_clk_ratios * get_arm_clk_ratios (void)
 Get the clock ratios for CPU configuration. More...
 
void system_clock_init (void)
 

Variables

static struct exynos5420_clock *const exynos_clock
 
static struct exynos5_mct *const exynos_mct
 

Macro Definition Documentation

◆ APLL

#define APLL   0

Definition at line 14 of file clk.h.

◆ AUDIO1_SEL_MASK

#define AUDIO1_SEL_MASK   0xf

Definition at line 654 of file clk.h.

◆ AUDIO_0_RATIO_MASK

#define AUDIO_0_RATIO_MASK   0x0f

Definition at line 650 of file clk.h.

◆ AUDIO_1_RATIO_MASK

#define AUDIO_1_RATIO_MASK   0x0f

Definition at line 651 of file clk.h.

◆ BPLL

#define BPLL   5

Definition at line 19 of file clk.h.

◆ CLK_SRC_AUDIOCDCLK1

#define CLK_SRC_AUDIOCDCLK1   0x0

Definition at line 655 of file clk.h.

◆ CLK_SRC_PERIC1

#define CLK_SRC_PERIC1   0x254

Definition at line 653 of file clk.h.

◆ CLK_SRC_SCLK_EPLL

#define CLK_SRC_SCLK_EPLL   0x7

Definition at line 657 of file clk.h.

◆ CLK_SRC_XXTI

#define CLK_SRC_XXTI   0x1

Definition at line 656 of file clk.h.

◆ CPLL

#define CPLL   8

Definition at line 22 of file clk.h.

◆ DPLL

#define DPLL   9

Definition at line 23 of file clk.h.

◆ EPLL

#define EPLL   2

Definition at line 16 of file clk.h.

◆ EPLL_CON0_LOCK_DET_EN_MASK

#define EPLL_CON0_LOCK_DET_EN_MASK   1

Definition at line 668 of file clk.h.

◆ EPLL_CON0_LOCK_DET_EN_SHIFT

#define EPLL_CON0_LOCK_DET_EN_SHIFT   28

Definition at line 667 of file clk.h.

◆ EPLL_CON0_LOCKED_SHIFT

#define EPLL_CON0_LOCKED_SHIFT   29

Definition at line 663 of file clk.h.

◆ EPLL_CON0_MDIV_MASK

#define EPLL_CON0_MDIV_MASK   0x1ff

Definition at line 660 of file clk.h.

◆ EPLL_CON0_MDIV_SHIFT

#define EPLL_CON0_MDIV_SHIFT   16

Definition at line 664 of file clk.h.

◆ EPLL_CON0_PDIV_MASK

#define EPLL_CON0_PDIV_MASK   0x3f

Definition at line 661 of file clk.h.

◆ EPLL_CON0_PDIV_SHIFT

#define EPLL_CON0_PDIV_SHIFT   8

Definition at line 665 of file clk.h.

◆ EPLL_CON0_SDIV_MASK

#define EPLL_CON0_SDIV_MASK   0x7

Definition at line 662 of file clk.h.

◆ EPLL_CON0_SDIV_SHIFT

#define EPLL_CON0_SDIV_SHIFT   0

Definition at line 666 of file clk.h.

◆ EPLL_SRC_CLOCK

#define EPLL_SRC_CLOCK   24000000 /*24 MHz Crystal Input */

Definition at line 647 of file clk.h.

◆ EXYNOS5_EPLLCON0_LOCKED_SHIFT

#define EXYNOS5_EPLLCON0_LOCKED_SHIFT   29 /* EPLL Locked bit position*/

Definition at line 646 of file clk.h.

◆ HPLL

#define HPLL   3

Definition at line 17 of file clk.h.

◆ IPLL

#define IPLL   10

Definition at line 24 of file clk.h.

◆ MCT_HZ

#define MCT_HZ   24000000

Definition at line 41 of file clk.h.

◆ MPLL

#define MPLL   1

Definition at line 15 of file clk.h.

◆ RPLL

#define RPLL   6

Definition at line 20 of file clk.h.

◆ SPLL

#define SPLL   7

Definition at line 21 of file clk.h.

◆ TIMEOUT_EPLL_LOCK

#define TIMEOUT_EPLL_LOCK   1000

Definition at line 648 of file clk.h.

◆ VPLL

#define VPLL   4

Definition at line 18 of file clk.h.

Function Documentation

◆ check_member() [1/2]

check_member ( exynos5420_clock  ,
cmu_kfc_version  ,
0x2bff0   
)

◆ check_member() [2/2]

check_member ( exynos5_mct  ,
l1_wstat  ,
0x440   
)

◆ clock_epll_set_rate()

int clock_epll_set_rate ( unsigned long  rate)

Definition at line 577 of file clock.c.

References ARRAY_SIZE, BIOS_DEBUG, st_epll_con_val::en_lock_det, exynos5_clock::epll_con0, EPLL_CON0_LOCK_DET_EN_MASK, EPLL_CON0_LOCK_DET_EN_SHIFT, EPLL_CON0_MDIV_MASK, EPLL_CON0_MDIV_SHIFT, EPLL_CON0_PDIV_MASK, EPLL_CON0_PDIV_SHIFT, EPLL_CON0_SDIV_MASK, EPLL_CON0_SDIV_SHIFT, exynos5_clock::epll_con1, epll_div, exynos5_clock::epll_lock, EXYNOS5_EPLLCON0_LOCKED_SHIFT, exynos_clock, st_epll_con_val::k_dsm, st_epll_con_val::m_div, st_epll_con_val::p_div, printk, read32(), st_epll_con_val::s_div, stopwatch_expired(), stopwatch_init_msecs_expire(), TIMEOUT_EPLL_LOCK, and write32().

Referenced by mainboard_enable().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ clock_gate()

void clock_gate ( void  )

Definition at line 267 of file clock_init.c.

References CLK_3DNR_MASK, CLK_AC97_MASK, CLK_ACP_MASK, CLK_ARM9S_MASK, CLK_ASYNCTVX_MASK, CLK_C2C_MASK, CLK_CAMIF_TOP_MASK, CLK_DIS_MASK, CLK_DPHY0_MASK, CLK_DPHY1_MASK, CLK_DRC_MASK, CLK_DSIM1_MASK, CLK_EFCLK_MASK, CLK_FD_MASK, CLK_G2D_MASK, CLK_GICISP_MASK, CLK_GSCL0_MASK, CLK_GSCL1_MASK, CLK_GSCL2_MASK, CLK_GSCL3_MASK, CLK_GSCL_WRAP_A_MASK, CLK_GSCL_WRAP_B_MASK, CLK_HDMI_MASK, CLK_HS_I2C0_MASK, CLK_HS_I2C1_MASK, CLK_HS_I2C2_MASK, CLK_HS_I2C3_MASK, CLK_I2C0_ISP_MASK, CLK_I2C1_ISP_MASK, CLK_I2S2_MASK, CLK_ID_REMAPPER_MASK, CLK_INT_COMB_ISP_MASK, CLK_ISP_MASK, CLK_JPEG_MASK, CLK_MCU_IOP_MASK, CLK_MCUCTL_ISP_MASK, CLK_MCUCTL_MASK, CLK_MCUISP_MASK, CLK_MDMA1_MASK, CLK_MDMA_MASK, CLK_MFC_MASK, CLK_MIPI_HSI_MASK, CLK_MIXER_MASK, CLK_MPWM_ISP_MASK, CLK_MTCADC_ISP_MASK, CLK_NFCON_MASK, CLK_ODC_MASK, CLK_PCM1_MASK, CLK_PCM2_MASK, CLK_PDMA0_MASK, CLK_PDMA1_MASK, CLK_PWM_ISP_MASK, CLK_ROTATOR_MASK, CLK_RTC_MASK, CLK_RTIC_MASK, CLK_SATA_MASK, CLK_SATA_PHY_CTRL_MASK, CLK_SATA_PHY_I2C_MASK, CLK_SCALERC_MASK, CLK_SCALERP_MASK, CLK_SECJTAG_MASK, CLK_SMMU3DNR_MASK, CLK_SMMU_DRC_MASK, CLK_SMMU_FD_MASK, CLK_SMMU_ISP_MASK, CLK_SMMU_MCUISP_MASK, CLK_SMMU_SCALERC_MASK, CLK_SMMU_SCALERP_MASK, CLK_SMMUDIS0_MASK, CLK_SMMUDIS1_MASK, CLK_SMMUFIMC_LITE0_MASK, CLK_SMMUFIMC_LITE1_MASK, CLK_SMMUFIMC_LITE2_MASK, CLK_SMMUG2D_MASK, CLK_SMMUGSCL0_MASK, CLK_SMMUGSCL1_MASK, CLK_SMMUGSCL2_MASK, CLK_SMMUGSCL3_MASK, CLK_SMMUJPEG_MASK, CLK_SMMUMCU_IOP_MASK, CLK_SMMUMDMA1_MASK, CLK_SMMUMDMA_MASK, CLK_SMMUMFCL_MASK, CLK_SMMUMFCR_MASK, CLK_SMMUODC_MASK, CLK_SMMUROTATOR_MASK, CLK_SMMURTIC_MASK, CLK_SMMUSSS_MASK, CLK_SMMUTVX_MASK, CLK_SPDIF_MASK, CLK_SPI0_ISP_MASK, CLK_SPI0_MASK, CLK_SPI1_ISP_MASK, CLK_SPI2_MASK, CLK_SSS_MASK, CLK_TZASC_DRBXR_MASK, CLK_TZPC0_MASK, CLK_TZPC1_MASK, CLK_TZPC2_MASK, CLK_TZPC3_MASK, CLK_TZPC4_MASK, CLK_TZPC5_MASK, CLK_TZPC6_MASK, CLK_TZPC7_MASK, CLK_TZPC8_MASK, CLK_TZPC9_MASK, CLK_UART_ISP_MASK, CLK_USBOTG_MASK, CLK_WDT_IOP_MASK, CLK_WDT_ISP_MASK, clrbits32, exynos_clock, exynos5_clock::gate_block, exynos5_clock::gate_bus_syslft, exynos5_clock::gate_ip_acp, exynos5_clock::gate_ip_cdrex, exynos5_clock::gate_ip_disp1, exynos5_clock::gate_ip_fsys, exynos5_clock::gate_ip_gen, exynos5_clock::gate_ip_gscl, exynos5_clock::gate_ip_isp0, exynos5_clock::gate_ip_isp1, exynos5_clock::gate_ip_mfc, exynos5_clock::gate_ip_peric, exynos5_clock::gate_ip_peris, exynos5_clock::gate_ip_sysrgt, exynos5_clock::gate_sclk_isp, and SCLK_MPWM_ISP_MASK.

Referenced by mainboard_init().

Here is the caller graph for this function:

◆ clock_get_periph_rate()

unsigned long clock_get_periph_rate ( enum periph_id  peripheral)

get the clk frequency of the required peripheral

Parameters
peripheralPeripheral id
Returns
frequency of the peripheral clk

Definition at line 220 of file clock.c.

References BIOS_DEBUG, BPLL, clock_select_to_pll(), CPLL, clk_bit_info::div_bit, exynos5_clock::div_fsys0, exynos5_clock::div_fsys1, exynos5_clock::div_peric0, exynos5_clock::div_peric1, exynos5_clock::div_peric2, exynos5_clock::div_peric3, exynos5_clock::div_top0, exynos5_clock::div_top1, DPLL, EPLL, exynos_clock, get_pll_clk(), MPLL, clk_bit_info::n_src_bits, PERIPH_ID_I2C0, PERIPH_ID_I2C1, PERIPH_ID_I2C10, PERIPH_ID_I2C2, PERIPH_ID_I2C3, PERIPH_ID_I2C4, PERIPH_ID_I2C5, PERIPH_ID_I2C6, PERIPH_ID_I2C7, PERIPH_ID_I2C8, PERIPH_ID_I2C9, PERIPH_ID_PWM0, PERIPH_ID_PWM1, PERIPH_ID_PWM2, PERIPH_ID_PWM3, PERIPH_ID_PWM4, PERIPH_ID_SATA, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3, PERIPH_ID_SPI0, PERIPH_ID_SPI1, PERIPH_ID_SPI2, PERIPH_ID_SPI3, PERIPH_ID_SPI4, PERIPH_ID_UART0, PERIPH_ID_UART1, PERIPH_ID_UART2, PERIPH_ID_UART3, clk_bit_info::prediv_bit, printk, read32(), exynos5_clock::sclk_div_isp, exynos5_clock::sclk_src_isp, clk_bit_info::src_bit, SRC_EPLL, exynos5_clock::src_fsys, SRC_MPLL, exynos5_clock::src_peric0, exynos5_clock::src_peric1, SRC_VPLL, and VPLL.

Referenced by hsi2c_get_clk_details(), i2c_ch_init(), i2c_init(), and serial_setbrg_dev().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ clock_ll_set_pre_ratio()

void clock_ll_set_pre_ratio ( enum periph_id  periph_id,
unsigned int  divisor 
)

Low-level function to set the clock pre-ratio for a peripheral.

Parameters
periph_idPeripheral ID of peripheral to change
divisorNew divisor for this peripheral's clock

Definition at line 339 of file clock.c.

References BIOS_DEBUG, clrsetbits32, exynos_clock, mask, PERIPH_ID_SPI0, PERIPH_ID_SPI1, PERIPH_ID_SPI2, PERIPH_ID_SPI3, PERIPH_ID_SPI4, and printk.

◆ clock_ll_set_ratio()

void clock_ll_set_ratio ( enum periph_id  periph_id,
unsigned int  divisor 
)

Low-level function to set the clock ratio for a peripheral.

Parameters
periph_idPeripheral ID of peripheral to change
divisorNew divisor for this peripheral's clock

Definition at line 382 of file clock.c.

References BIOS_DEBUG, clrsetbits32, exynos_clock, mask, PERIPH_ID_SPI0, PERIPH_ID_SPI1, PERIPH_ID_SPI2, PERIPH_ID_SPI3, PERIPH_ID_SPI4, and printk.

◆ clock_select_i2s_clk_source()

void clock_select_i2s_clk_source ( void  )

Definition at line 631 of file clock.c.

References AUDIO1_SEL_MASK, CLK_SRC_SCLK_EPLL, clrsetbits32, exynos_clock, and exynos5_clock::src_peric1.

Referenced by mainboard_enable().

Here is the caller graph for this function:

◆ clock_set_dwmci()

int clock_set_dwmci ( enum periph_id  peripheral)

Definition at line 309 of file clock.c.

References ASSERT, BIOS_DEBUG, DIV_ROUND_UP, get_mmc_clk(), PERIPH_ID_SDMMC0, printk, and set_mmc_clk().

Referenced by setup_storage().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ clock_set_i2s_clk_prescaler()

int clock_set_i2s_clk_prescaler ( unsigned int  src_frq,
unsigned int  dst_frq 
)

Definition at line 637 of file clock.c.

References AUDIO_1_RATIO_MASK, BIOS_DEBUG, clrsetbits32, exynos5_clock::div_peric4, exynos_clock, and printk.

Referenced by mainboard_enable().

Here is the caller graph for this function:

◆ clock_set_mshci()

int clock_set_mshci ( enum periph_id  peripheral)

Definition at line 540 of file clock.c.

References addr, BIOS_DEBUG, exynos5_clock::div_fsys1, exynos5_clock::div_fsys2, exynos_clock, get_pll_clk(), MPLL, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC2, printk, read32(), and write32().

Referenced by setup_storage().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ clock_set_rate()

int clock_set_rate ( enum periph_id  periph_id,
unsigned int  rate 
)

Low-level function that selects the best clock scalars for a given rate and sets up the given peripheral's clock accordingly.

Parameters
periph_idPeripheral ID of peripheral to change
rateDesired clock rate in Hz
Returns
zero on success, negative on error

Definition at line 476 of file clock.c.

References BIOS_DEBUG, clock_calc_best_scalar(), clock_ll_set_pre_ratio(), clock_ll_set_ratio(), PERIPH_ID_SPI0, PERIPH_ID_SPI1, PERIPH_ID_SPI2, PERIPH_ID_SPI3, PERIPH_ID_SPI4, and printk.

Here is the call graph for this function:

◆ get_arm_clk()

unsigned long get_arm_clk ( void  )

Definition at line 315 of file clock.c.

References APLL, exynos5_clock::div_cpu0, exynos_clock, get_pll_clk(), and read32().

Referenced by cpu_init().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ get_arm_clk_ratios()

struct arm_clk_ratios* get_arm_clk_ratios ( void  )

Get the clock ratios for CPU configuration.

Returns
pointer to the clock ratios that we should use

Definition at line 334 of file clock.c.

References arm_clk_ratios::arm_ratio, ARRAY_SIZE, and NULL.

Referenced by setup_clock().

Here is the caller graph for this function:

◆ get_pll_clk()

unsigned long get_pll_clk ( int  pllreg)

Definition at line 156 of file clock.c.

References APLL, exynos5_clock::apll_con0, BIOS_DEBUG, BPLL, exynos5_clock::bpll_con0, CONF_SYS_CLK_FREQ, CPLL, exynos5_clock::cpll_con0, DPLL, EPLL, exynos5_clock::epll_con0, exynos5_clock::epll_con1, exynos_clock, m, mask, MPLL, exynos5_clock::mpll_con0, printk, read32(), RPLL, s, SPLL, VPLL, exynos5_clock::vpll_con0, and exynos5_clock::vpll_con1.

Referenced by clock_get_periph_rate(), clock_set_mshci(), get_arm_clk(), get_lcd_clk(), and get_mmc_clk().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ get_pwm_clk()

unsigned long get_pwm_clk ( void  )

◆ get_uart_clk()

unsigned long get_uart_clk ( int  dev_index)

◆ set_mmc_clk()

void set_mmc_clk ( int  dev_index,
unsigned int  div 
)

Definition at line 350 of file clock.c.

References addr, exynos5_clock::div_fsys1, exynos5_clock::div_fsys2, exynos_clock, read32(), val, and write32().

Referenced by clock_set_dwmci().

Here is the call graph for this function:
Here is the caller graph for this function:

◆ system_clock_init()

void system_clock_init ( void  )

Definition at line 12 of file clock_init.c.

References exynos5_clock::apll_con0, exynos5_clock::apll_con1, APLL_CON1_VAL, APLL_FOUT, exynos5_clock::apll_lock, APLL_LOCK_VAL, AUDIO0_SEL_EPLL, exynos5_clock::bpll_con0, exynos5_clock::bpll_con1, BPLL_CON1_VAL, exynos5_clock::bpll_lock, BPLL_LOCK_VAL, CLK_DIV2_RATIO, CLK_DIV4_RATIO, CLK_DIV_CDREX0_VAL, CLK_DIV_CDREX1_VAL, CLK_DIV_CPERI1_VAL, CLK_DIV_CPU0_VAL, CLK_DIV_DISP1_0_VAL, CLK_DIV_FSYS0_VAL, CLK_DIV_FSYS1_VAL, CLK_DIV_FSYS2_VAL, CLK_DIV_G2D, CLK_DIV_ISP0_VAL, CLK_DIV_ISP1_VAL, CLK_DIV_KFC_VAL, CLK_DIV_PERIC0_VAL, CLK_DIV_PERIC1_VAL, CLK_DIV_PERIC2_VAL, CLK_DIV_PERIC3_VAL, CLK_DIV_PERIC4_VAL, CLK_DIV_TOP0_VAL, CLK_DIV_TOP1_VAL, CLK_DIV_TOP2_VAL, CLK_SRC_CDREX_VAL, CLK_SRC_CPU_VAL, CLK_SRC_DISP1_0_VAL, CLK_SRC_FSYS0_VAL, CLK_SRC_ISP_VAL, CLK_SRC_KFC_VAL, CLK_SRC_PERIC0_VAL, CLK_SRC_PERIC1_VAL, CLK_SRC_TOP0_VAL, CLK_SRC_TOP1_VAL, CLK_SRC_TOP2_VAL, CLK_SRC_TOP3_VAL, CLK_SRC_TOP4_VAL, CLK_SRC_TOP5_VAL, CLK_SRC_TOP6_VAL, CLK_SRC_TOP7_VAL, clrbits32, exynos5_clock::cpll_con0, exynos5_clock::cpll_con1, CPLL_CON1_VAL, exynos5_clock::cpll_lock, CPLL_LOCK_VAL, DIV_MAU_VAL, DPLL_CON1_VAL, DPLL_LOCK_VAL, exynos5_clock::epll_con0, exynos5_clock::epll_con1, EPLL_CON1_VAL, exynos5_clock::epll_con2, EPLL_CON2_VAL, exynos5_clock::epll_lock, EPLL_LOCK_VAL, exynos_clock, exynos_mct, exynos5_mct::g_tcon, HPM_RATIO, IPLL_CON1_VAL, IPLL_LOCK_VAL, KPLL_CON1_VAL, KPLL_FOUT, KPLL_LOCK_VAL, exynos5_clock::mpll_con0, exynos5_clock::mpll_con1, MPLL_CON1_VAL, exynos5_clock::mpll_lock, MPLL_LOCK_VAL, MUX_HPM_SEL_MASK, PLL_LOCKED, read32(), RPLL_CON1_VAL, RPLL_CON2_VAL, RPLL_LOCK_VAL, set_pll, setbits32, SPLL_CON1_VAL, SPLL_LOCK_VAL, SRC_KFC_HPM_SEL, val, exynos5_clock::vpll_con0, exynos5_clock::vpll_con1, VPLL_CON1_VAL, exynos5_clock::vpll_lock, VPLL_LOCK_VAL, and write32().

Here is the call graph for this function:

Variable Documentation

◆ exynos_clock

struct exynos5420_clock* const exynos_clock
static
Initial value:
=
(void *)EXYNOS5_CLOCK_BASE
EXYNOS5_CLOCK_BASE
#define EXYNOS5_CLOCK_BASE
Definition: cpu.h:12

Definition at line 581 of file clk.h.

◆ exynos_mct

struct exynos5_mct* const exynos_mct
static
Initial value:
=
(void *)EXYNOS5_MULTI_CORE_TIMER_BASE
EXYNOS5_MULTI_CORE_TIMER_BASE
#define EXYNOS5_MULTI_CORE_TIMER_BASE
Definition: cpu.h:16

Definition at line 643 of file clk.h.