7 #include <soc/periph.h>
11 #define CONF_SYS_CLK_FREQ 24000000
15 { 192000000, 0, 48, 3, 1, 0 },
16 { 180000000, 0, 45, 3, 1, 0 },
17 { 73728000, 1, 73, 3, 3, 47710 },
18 { 67737600, 1, 90, 4, 3, 20762 },
19 { 49152000, 0, 49, 3, 3, 9961 },
20 { 45158400, 0, 45, 3, 3, 10381 },
21 { 180633600, 0, 45, 3, 1, 10381 }
27 unsigned long r,
m, p,
s, k = 0,
mask, fout;
72 if (pllreg ==
APLL || pllreg ==
BPLL || pllreg ==
MPLL ||
87 if (pllreg ==
EPLL || pllreg ==
RPLL) {
90 fout = (
m + k / 65536) * (
freq / (p * (1 <<
s)));
91 }
else if (pllreg ==
VPLL) {
94 fout = (
m + k / 1024) * (
freq / (p * (1 <<
s)));
97 fout =
m * (
freq / (p * (1 <<
s)));
153 switch (peripheral) {
230 __func__, peripheral);
242 return sclk / (div + 1);
249 unsigned long armclk;
250 unsigned int arm_ratio;
251 unsigned int arm2_ratio;
256 arm_ratio = (div >> 0) & 0x7;
257 arm2_ratio = (div >> 28) & 0x7;
260 armclk /= (arm2_ratio + 1);
268 unsigned long uclk, sclk;
269 unsigned int sel, ratio;
273 sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
284 shift = dev_index * 10;
286 ratio = (ratio >> shift) & 0x3ff;
287 uclk = (sclk / (ratio + 1));
297 unsigned int val, shift;
300 shift = dev_index * 10;
303 val &= ~(0x3ff << shift);
304 val |= (div & 0x3ff) << shift;
312 const unsigned long freq = 52000000;
313 unsigned long sdclkin, cclkin;
316 ASSERT(device_index >= 0 && device_index < 4);
328 if (device_index == 0 || device_index == 2){
330 sdclkin /= (divratio + 1);
332 printk(
BIOS_DEBUG,
"%s(%d): sdclkin: %ld\n", __func__, device_index, sdclkin);
342 unsigned int mask = 0xff;
385 unsigned int mask = 0xf;
433 unsigned int fine_scalar_bits,
unsigned int input_rate,
434 unsigned int target_rate,
unsigned int *best_fine_scalar)
437 int best_main_scalar = -1;
438 unsigned int best_error = target_rate;
439 const unsigned int cap = (1 << fine_scalar_bits) - 1;
440 const unsigned int loops = 1 << main_scaler_bits;
442 printk(
BIOS_DEBUG,
"Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
446 ASSERT(main_scaler_bits <= fine_scalar_bits);
448 *best_fine_scalar = 1;
450 if (input_rate == 0 || target_rate == 0)
453 if (target_rate >= input_rate)
456 for (i = 1; i <= loops; i++) {
457 const unsigned int effective_div =
MAX(
MIN(input_rate / i /
458 target_rate, cap), 1);
459 const unsigned int effective_rate = input_rate / i /
461 const int error = target_rate - effective_rate;
463 printk(
BIOS_DEBUG,
"%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
464 effective_rate, error);
466 if (error >= 0 && error <= best_error) {
468 best_main_scalar = i;
469 *best_fine_scalar = effective_div;
473 return best_main_scalar;
488 if (main_scalar < 0) {
521 switch (peripheral) {
533 for (i = 0; i <= 0xf; i++) {
534 if ((clock / (i + 1)) <= 400) {
544 unsigned int epll_con, epll_con_k;
546 unsigned int lockcnt;
604 if ((dst_frq == 0) || (src_frq == 0)) {
605 printk(
BIOS_DEBUG,
"%s: Invalid frequency input for prescaler\n", __func__);
610 div = (src_frq / dst_frq);
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
#define DIV_ROUND_UP(x, y)
#define printk(level,...)
#define EPLL_CON0_LOCK_DET_EN_SHIFT
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT
#define EPLL_CON0_SDIV_SHIFT
#define EPLL_CON0_MDIV_SHIFT
#define EPLL_CON0_SDIV_MASK
#define EPLL_CON0_PDIV_MASK
#define CLK_SRC_SCLK_EPLL
#define EPLL_CON0_MDIV_MASK
#define AUDIO_1_RATIO_MASK
#define EPLL_CON0_LOCK_DET_EN_MASK
#define EPLL_CON0_PDIV_SHIFT
static struct exynos5_clock *const exynos_clock
#define TIMEOUT_EPLL_LOCK
#define clrsetbits32(addr, clear, set)
static int stopwatch_expired(struct stopwatch *sw)
static void stopwatch_init_msecs_expire(struct stopwatch *sw, long ms)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor)
Low-level function to set the clock ratio for a peripheral.
void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor)
Low-level function to set the clock pre-ratio for a peripheral.
void clock_select_i2s_clk_source(void)
unsigned long get_arm_clk(void)
unsigned long clock_get_periph_rate(enum periph_id peripheral)
get the clk frequency of the required peripheral
int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
int clock_set_rate(enum periph_id periph_id, unsigned int rate)
Low-level function that selects the best clock scalars for a given rate and sets up the given periphe...
unsigned long get_pll_clk(int pllreg)
void set_mmc_clk(int dev_index, unsigned int div)
int clock_set_mshci(enum periph_id peripheral)
int clock_epll_set_rate(unsigned long rate)
static unsigned long get_mmc_clk(int dev_index)
int clock_set_dwmci(enum periph_id peripheral)
static int clock_select_to_pll(enum peripheral_clock_select sel)
#define CONF_SYS_CLK_FREQ
static int clock_calc_best_scalar(unsigned int main_scaler_bits, unsigned int fine_scalar_bits, unsigned int input_rate, unsigned int target_rate, unsigned int *best_fine_scalar)
Linearly searches for the most accurate main and fine stage clock scalars (divisors) for a specified ...
static struct st_epll_con_val epll_div[]
#define s(param, src_bits, pmcreg, dst_bits)
#define m(clkreg, src_bits, pmcreg, dst_bits)