coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
pci.c
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
6 #include <device/pci_ops.h>
7 #include "i82801dx.h"
8 
9 static void pci_init(struct device *dev)
10 {
11  /* System error enable */
13 }
14 
15 static struct device_operations pci_ops = {
17  .set_resources = pci_dev_set_resources,
18  .enable_resources = pci_bus_enable_resources,
19  .init = pci_init,
20  .scan_bus = pci_scan_bridge,
21 };
22 
23 /* 82801DB */
24 static const struct pci_driver pci_driver_db __pci_driver = {
25  .ops = &pci_ops,
26  .vendor = PCI_VID_INTEL,
27  .device = PCI_DID_INTEL_82801DB_PCI,
28 };
29 
30 /* 82801DBM/DBL */
31 static const struct pci_driver pci_driver_dbm __pci_driver = {
32  .ops = &pci_ops,
33  .vendor = PCI_VID_INTEL,
35 };
static __always_inline void pci_or_config16(const struct device *dev, u16 reg, u16 ormask)
Definition: pci_ops.h:180
static const struct pci_driver pci_driver_db __pci_driver
Definition: pci.c:24
static void pci_init(struct device *dev)
Definition: pci.c:9
static struct device_operations pci_ops
Definition: pci.c:15
#define PCI_COMMAND_PARITY
Definition: pci_def.h:17
#define PCI_COMMAND_SERR
Definition: pci_def.h:19
#define PCI_COMMAND
Definition: pci_def.h:10
void pci_bus_enable_resources(struct device *dev)
Definition: pci_device.c:758
void pci_bus_read_resources(struct device *dev)
Definition: pci_device.c:540
void pci_scan_bridge(struct device *dev)
Scan a PCI bridge and the buses behind the bridge.
Definition: pci_device.c:1598
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691
#define PCI_DID_INTEL_82801DBM_PCI
Definition: pci_ids.h:2299
#define PCI_VID_INTEL
Definition: pci_ids.h:2157
#define PCI_DID_INTEL_82801DB_PCI
Definition: pci_ids.h:2274
void(* read_resources)(struct device *dev)
Definition: device.h:39
Definition: device.h:107