coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
northbridge.c File Reference
#include <console/console.h>
#include <acpi/acpi.h>
#include <arch/hpet.h>
#include <device/pci_ops.h>
#include <stdint.h>
#include <cpu/intel/model_2065x/model_2065x.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "chip.h"
#include <commonlib/bsd/helpers.h>
#include "ironlake.h"
#include <cpu/intel/smm_reloc.h>
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Go to the source code of this file.

Functions

int bridge_silicon_revision (void)
 
static void add_fixed_resources (struct device *dev, int index)
 
static void mc_read_resources (struct device *dev)
 
static void northbridge_init (struct device *dev)
 
static void ironlake_init (void *const chip_info)
 
static void enable_dev (struct device *dev)
 

Variables

static int bridge_revision_id = -1
 
static const int legacy_hole_base_k = 0xa0000 / 1024
 
static struct device_operations pci_domain_ops
 
static struct device_operations mc_ops
 
static const unsigned short pci_device_ids []
 
static const struct pci_driver mc_driver_ilk __pci_driver
 
static struct device_operations cpu_bus_ops
 
struct chip_operations northbridge_intel_ironlake_ops
 

Function Documentation

◆ add_fixed_resources()

static void add_fixed_resources ( struct device dev,
int  index 
)
static

Definition at line 38 of file northbridge.c.

References resource::base, resource::flags, HPET_BASE_ADDRESS, resource::index, IORESOURCE_ASSIGNED, IORESOURCE_FIXED, IORESOURCE_MEM, IORESOURCE_RESERVE, IORESOURCE_STORED, KiB, legacy_hole_base_k, mmio_resource, new_resource(), reserved_ram_resource, and resource::size.

Referenced by mc_read_resources().

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◆ bridge_silicon_revision()

int bridge_silicon_revision ( void  )

Definition at line 19 of file northbridge.c.

References bridge_revision_id, cpuid_eax(), PCI_DEVICE_ID, pci_read_config16(), pcidev_on_root(), and stepping.

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◆ enable_dev()

static void enable_dev ( struct device dev)
static

◆ ironlake_init()

static void ironlake_init ( void *const  chip_info)
static

Definition at line 162 of file northbridge.c.

References BIOS_DEBUG, DEVEN, DEVEN_IGD, DEVEN_PEG10, device::enabled, pci_update_config32(), pcidev_on_root(), printk, and UINT32_MAX.

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◆ mc_read_resources()

static void mc_read_resources ( struct device dev)
static

◆ northbridge_init()

static void northbridge_init ( struct device dev)
static

Definition at line 148 of file northbridge.c.

References dmibar_setbits32, dmibar_write32(), DMICESTS, DMILCTL, DMILLTC, and DMIUESTS.

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Variable Documentation

◆ __pci_driver

const struct pci_driver mc_driver_ilk __pci_driver
static
Initial value:
= {
.ops = &mc_ops,
.vendor = PCI_VID_INTEL,
.devices = pci_device_ids,
}
static struct device_operations mc_ops
Definition: northbridge.c:183
static const unsigned short pci_device_ids[]
Definition: northbridge.c:203
#define PCI_VID_INTEL
Definition: pci_ids.h:2157

Definition at line 203 of file northbridge.c.

◆ bridge_revision_id

int bridge_revision_id = -1
static

Definition at line 17 of file northbridge.c.

Referenced by bridge_silicon_revision().

◆ cpu_bus_ops

struct device_operations cpu_bus_ops
static
Initial value:
= {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.init = mp_cpu_bus_init,
}
static void noop_read_resources(struct device *dev)
Standard device operations function pointers shims.
Definition: device.h:73
static void noop_set_resources(struct device *dev)
Definition: device.h:74
static void mp_cpu_bus_init(struct device *dev)
Definition: device.h:240

Definition at line 203 of file northbridge.c.

Referenced by enable_dev().

◆ legacy_hole_base_k

const int legacy_hole_base_k = 0xa0000 / 1024
static

Definition at line 36 of file northbridge.c.

Referenced by add_fixed_resources().

◆ mc_ops

struct device_operations mc_ops
static
Initial value:
= {
.read_resources = mc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.acpi_fill_ssdt = generate_cpu_entries,
.ops_pci = &pci_dev_ops_pci,
}
void generate_cpu_entries(const struct device *device)
Definition: acpi.c:334
static void mc_read_resources(struct device *dev)
Definition: northbridge.c:88
static void northbridge_init(struct device *dev)
Definition: northbridge.c:148
void pci_dev_enable_resources(struct device *dev)
Definition: pci_device.c:721
struct pci_operations pci_dev_ops_pci
Default device operation for PCI devices.
Definition: pci_device.c:911
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691

Definition at line 162 of file northbridge.c.

◆ northbridge_intel_ironlake_ops

struct chip_operations northbridge_intel_ironlake_ops
Initial value:
= {
.enable_dev = enable_dev,
.init = ironlake_init,
}
static void enable_dev(struct device *dev)
Definition: northbridge.c:228
static void ironlake_init(void *const chip_info)
Definition: northbridge.c:162

Definition at line 228 of file northbridge.c.

◆ pci_device_ids

const unsigned short pci_device_ids[]
static
Initial value:
= {
0x0040,
0x0044,
0x0048,
0x0062,
0x0069,
0x006a,
0
}

Definition at line 203 of file northbridge.c.

◆ pci_domain_ops

struct device_operations pci_domain_ops
static
Initial value:
= {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus,
}
void pci_domain_read_resources(struct device *dev)
Definition: pci_device.c:547
void pci_domain_set_resources(struct device *dev)
Definition: pci_device.c:564
void pci_domain_scan_bus(struct device *dev)
Scan a PCI domain.
Definition: pci_device.c:1610

Definition at line 38 of file northbridge.c.

Referenced by enable_dev().