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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/mmio.h>
#include <assert.h>
#include <console/console.h>
#include <delay.h>
#include <soc/addressmap.h>
#include <soc/dramc_common.h>
#include <soc/dramc_register.h>
#include <soc/dramc_pi_api.h>
#include <soc/dramc_soc.h>
#include <soc/emi.h>
#include <soc/mt6391.h>
#include <soc/pll.h>
#include <soc/spm.h>
#include <types.h>
Go to the source code of this file.
Data Structures | |
struct | mem_pll |
Definition at line 651 of file dramc_pi_basic_api.c.
References ch, CHANNEL_B, clrbits32, ddrphy_regs, MEMCLKENB_SHIFT, dramc_ddrphy_regs::mempll_divider, setbits32, and udelay().
Referenced by init_dram(), and mem_pll_init().
u32 dramc_engine2 | ( | u32 | channel, |
enum dram_tw_op | wr, | ||
u32 | test2_1, | ||
u32 | test2_2, | ||
u8 | testaudpat, | ||
u8 | log2loopcount | ||
) |
Definition at line 758 of file dramc_pi_basic_api.c.
References ao_regs, AUDIO, ch, clrbits32, clrsetbits32, dramc_nao_regs::cmp_err, dramc_ao_regs::conf2, CONF2_TEST1_EN, CONF2_TEST2R_EN, CONF2_TEST2W_EN, die(), ISI, nao_regs, read32(), setbits32, TE_OP_READ_CHECK, TE_OP_WRITE_READ_CHECK, dramc_nao_regs::test2_1, dramc_nao_regs::test2_2, dramc_ao_regs::test2_3, TEST2_3_TESTAUDPAT_EN, TEST2_3_TESTCNT_MASK, TEST2_3_TESTCNT_SHIFT, dramc_ao_regs::test2_4, TEST2_4_TESTAUDBITINV_EN, TEST2_4_TESTAUDINC_MASK, TEST2_4_TESTAUDINC_SHIFT, TEST2_4_TESTAUDINIT_MASK, TEST2_4_TESTAUDINIT_SHIFT, TEST2_4_TESTAUDMODE_EN, TEST2_4_TESTXTALKPAT_EN, dramc_nao_regs::testrpt, TESTRPT_DM_CMP_CPT_SHIFT, udelay(), value, write32(), and XTALK.
Referenced by dqs_gw_test(), dram_k_perbit(), and rx_datlat_cal().
void dramc_init | ( | u32 | channel, |
const struct mt8173_sdram_params * | sdram_params | ||
) |
Definition at line 451 of file dramc_pi_basic_api.c.
References dramc_ao_regs::actim0, dramc_ao_regs::actim1, ao_regs, dramc_ao_regs::arbctl0, assert, ch, dramc_ao_regs::clk1delay, dramc_ao_regs::clkctl, clrbits32, dramc_ao_regs::conf1, dramc_ao_regs::conf2, dramc_ao_regs::ddr2ctl, dramc_ddrphy_regs::ddr2ctl, ddrphy_regs, DEFAULT_DRIVING, dramc_ao_regs::dllconf, dramc_ao_regs::dqidly, DQS_BIT_NUMBER, dramc_ao_regs::dqscal0, dramc_ddrphy_regs::dqscal0, dramc_ao_regs::dqsctl1, dramc_ao_regs::dqsctl2, dramc_ddrphy_regs::dqsgctl, dramc_ao_regs::dqsien, dramc_ddrphy_regs::dqsisel, dramc_ao_regs::dramc_pd_ctrl, dramc_set_mrs_value(), DRIVING_DS2_0, dramc_ao_regs::drvctl1, dramc_ddrphy_regs::drvctl1, dramc_ao_regs::dummy, dramc_ao_regs::gddr3ctl1, dramc_ddrphy_regs::gddr3ctl1, dramc_ddrphy_regs::ioctl, dramc_ao_regs::iodrv6, is_dual_rank(), dramc_ao_regs::mckdly, dramc_ddrphy_regs::mckdly, dramc_ao_regs::misc, dramc_ao_regs::misctl0, dramc_ddrphy_regs::misctl0, dramc_ao_regs::ocdk, dramc_ddrphy_regs::ocdk, dramc_ddrphy_regs::padctl1, dramc_ddrphy_regs::padctl2, dramc_ao_regs::padctl4, dramc_ao_regs::padctl7, dramc_ao_regs::perfctl0, dramc_ddrphy_regs::peri, dramc_ddrphy_regs::phyclkduty, dramc_ao_regs::phyctl1, dramc_ao_regs::r0deldly, dramc_ao_regs::r1deldly, dramc_ao_regs::rkcfg, mt8173_calib_params::rx_dq_dly, mt8173_calib_params::rx_dqs_dly, setbits32, dramc_ddrphy_regs::tdsel, dramc_ao_regs::test2_3, dramc_ao_regs::test2_4, udelay(), dramc_ao_regs::wodt, write32(), and dramc_ao_regs::zqcs.
Referenced by dfs_init_for_calibration(), and init_dram().
Definition at line 661 of file dramc_pi_basic_api.c.
References ao_regs, ch, clrbits32, ddrphy_regs, dramc_ao_regs::gddr3ctl1, GDDR3CTL1_RDATRST_SHIFT, dramc_ddrphy_regs::phyctl1, PHYCTL1_PHYRST_SHIFT, setbits32, and udelay().
Referenced by dqs_gw_counter_reset(), and perbit_window_cal().
void dramc_pre_init | ( | u32 | channel, |
const struct mt8173_sdram_params * | sdram_params | ||
) |
Definition at line 396 of file dramc_pi_basic_api.c.
References dramc_ao_regs::ac_time_05t, ao_regs, ch, dramc_ao_regs::selph1, dramc_ao_regs::selph10, dramc_ao_regs::selph11, dramc_ao_regs::selph2, dramc_ao_regs::selph3, dramc_ao_regs::selph4, dramc_ao_regs::selph5, dramc_ao_regs::selph6_1, dramc_ao_regs::selph7, dramc_ao_regs::selph8, dramc_ao_regs::selph9, and write32().
Referenced by init_dram().
void dramc_runtime_config | ( | u32 | channel, |
const struct mt8173_sdram_params * | sdram_params | ||
) |
Definition at line 680 of file dramc_pi_basic_api.c.
References ao_regs, BIT, ch, CHANNEL_A, clrbits32, dramc_ddrphy_regs::ddrphy_cg_ctrl, ddrphy_regs, die(), dramc_ao_regs::dqscal0, DQSCAL0_STBCALEN_SHIFT, dramc_ddrphy_regs::dqsgctl, dramc_ao_regs::dummy, MHz, dramc_ao_regs::perfctl0, setbits32, and dramc_ao_regs::spcmd.
Referenced by after_calib(), and do_calib().
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static |
Definition at line 434 of file dramc_pi_basic_api.c.
References mrs_write().
Referenced by dramc_init().
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inline |
Definition at line 24 of file dramc_pi_basic_api.c.
Referenced by do_calib(), dramc_init(), dramc_rankinctl_config(), and set_rank_info_to_conf().
void mem_pll_init | ( | const struct mt8173_sdram_params * | sdram_params | ) |
Definition at line 295 of file dramc_pi_basic_api.c.
References BIOS_DEBUG, ch, CHANNEL_NUM, clrbits32, ddrphy_regs, div2_phase_sync(), mem_pll_init_phase_sync(), mem_pll_init_set_params(), mem_pll_phase_cali(), mem_pll_pre_init(), dramc_ddrphy_regs::mempll, mt_mem_pll_config_post(), mt_mem_pll_config_pre(), mt_mem_pll_mux(), mtk_spm, mtk_spm_regs::power_on_val0, mtk_spm_regs::poweron_config_set, printk, setbits32, SPM_PROJECT_CODE, udelay(), and write32().
Referenced by mt_mem_init().
Definition at line 141 of file dramc_pi_basic_api.c.
References BIT, ch, clrsetbits32, ddrphy_regs, dramc_ddrphy_regs::mempll_divider, and write32().
Referenced by mem_pll_init().
Definition at line 94 of file dramc_pi_basic_api.c.
References ch, ddrphy_regs, dramc_ddrphy_regs::mempll, and write32().
Referenced by mem_pll_init().
Definition at line 225 of file dramc_pi_basic_api.c.
References ch, clrbits32, clrsetbits32, ddrphy_regs, delay(), die(), mem_pll::done, dramc_dbg, dramc_ddrphy_regs::jmeter, JMETER_COUNT, JMETER_COUNTER_MASK, JMETER_COUNTER_SHIFT, JMETER_EN_BIT, JMETER_WAIT_DONE_US, pll_phase_adjust(), pll_phase_check(), setbits32, and udelay().
Referenced by mem_pll_init().
Definition at line 31 of file dramc_pi_basic_api.c.
References ao_regs, ch, CHANNEL_A, clrbits32, dramc_ao_regs::ddr2ctl, dramc_ddrphy_regs::ddrphy_cg_ctrl, ddrphy_regs, dramc_ddrphy_regs::lpddr2_3, dramc_ddrphy_regs::lpddr2_4, dramc_ddrphy_regs::mempll05_divider, dramc_ddrphy_regs::mempll_divider, dramc_ddrphy_regs::peri, dramc_ddrphy_regs::selph12, dramc_ddrphy_regs::selph13, dramc_ddrphy_regs::selph14, dramc_ddrphy_regs::selph15, setbits32, and write32().
Referenced by mem_pll_init().
Definition at line 425 of file dramc_pi_basic_api.c.
References ao_regs, ch, dramc_ao_regs::mrs, dramc_ao_regs::spcmd, udelay(), and write32().
Referenced by dramc_set_mrs_value().
Definition at line 154 of file dramc_pi_basic_api.c.
References ch, clrbits32, clrsetbits32, ddrphy_regs, mem_pll::delay, dramc_ddrphy_regs::mempll, MEMPLL_FB_DL_SHIFT, MEMPLL_INIT, MEMPLL_REF_DL_SHIFT, MEMPLL_REF_LAG, MEMPLL_REF_LEAD, and mem_pll::phase.
Referenced by mem_pll_phase_cali().
Definition at line 182 of file dramc_pi_basic_api.c.
References ch, ddrphy_regs, mem_pll::delay, mem_pll::done, dramc_dbg, JMETER_COUNT_N, dramc_ddrphy_regs::jmeter_pll_st, MEMPLL_INIT, MEMPLL_REF_LAG, MEMPLL_REF_LEAD, mem_pll::phase, read32(), and value.
Referenced by mem_pll_phase_cali().
Definition at line 740 of file dramc_pi_basic_api.c.
References BIT, ch, CHANNEL_A, CHANNEL_B, ddrphy_regs, mtk_apmixed, dramc_ddrphy_regs::peri, setbits32, val, and write32().
Referenced by do_calib().
Definition at line 722 of file dramc_pi_basic_api.c.
References BIT, ch, CHANNEL_A, CHANNEL_B, clrbits32, ddrphy_regs, mtk_apmixed, and dramc_ddrphy_regs::peri.
Referenced by do_calib().