12 #if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
16 #define BYTE_TO_DWORD_OFFSET(x) (x/4)
17 #define AHCI_BASE_ADDRESS_REG 0x24
18 #define MISC_CONTROL_REG 0x40
19 #define UNLOCK_BIT (1<<0)
20 #define SATA_CAPABILITIES_REG 0xFC
21 #define CFG_CAP_SPM (1<<12)
23 volatile u32 *ahci_ptr =
42 static struct pci_operations
lops_pci = {
54 static const struct pci_driver sata0_driver
__pci_driver = {
60 static const struct pci_driver sata0_driver_ahci
__pci_driver = {
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
void pci_dev_enable_resources(struct device *dev)
void pci_dev_read_resources(struct device *dev)
void pci_dev_set_resources(struct device *dev)
#define PCI_DID_AMD_SB900_SATA_AHCI
#define PCI_DID_AMD_SB900_SATA
#define SATA_CAPABILITIES_REG
static struct pci_operations lops_pci
static void sata_init(struct device *dev)
static struct device_operations sata_ops
static const struct pci_driver sata0_driver __pci_driver
void(* read_resources)(struct device *dev)