coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/pci_ops.h>
8 #include <device/device.h>
9 
10 static void hybrid_graphics_init(void)
11 {
12  bool peg, igd;
13  u32 reg32;
14 
15  early_hybrid_graphics(&igd, &peg);
16 
17  if (peg && igd)
18  return;
19 
20  /* Hide disabled devices */
21  reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
22  reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD);
23 
24  if (peg)
25  reg32 |= DEVEN_PEG10;
26 
27  if (igd)
28  reg32 |= DEVEN_IGD;
29  else
30  /* Disable IGD VGA decode, no GTT or GFX stolen */
31  pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);
32 
33  pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
34 }
35 
36 // OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13
38  { 1, 1, 0 }, /* P0: system port 4, OC0 */
39  { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */
40  { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */
41  { 1, 0, -1 }, /* P3: WWAN, no OC */
42  { 1, 0, -1 }, /* P4: smartcard, no OC */
43  { 1, 1, -1 }, /* P5: ExpressCard, no OC */
44  { 0, 0, -1 }, /* P6: empty */
45  { 0, 0, -1 }, /* P7: empty */
46  { 1, 1, 4 }, /* P8: system port 3, OC4*/
47  { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */
48  { 1, 0, -1 }, /* P10: fingerprint reader, no OC */
49  { 1, 0, -1 }, /* P11: bluetooth, no OC. */
50  { 1, 1, -1 }, /* P12: docking, no OC */
51  { 1, 1, -1 }, /* P13: camera (LCD), no OC */
52 };
53 
54 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
55 {
56  read_spd(&spd[0], 0x50, id_only);
57  read_spd(&spd[2], 0x51, id_only);
58 }
59 
60 void mainboard_early_init(int s3resume)
61 {
63 }
#define GGC
Definition: host_bridge.h:9
#define DEVEN
Definition: host_bridge.h:16
void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
Definition: romstage.c:17
u8 spd_raw_data[256]
Definition: ddr3.h:156
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition: pci_ops.h:58
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
Definition: pci_ops.h:70
#define DEVEN_PEG10
Definition: host_bridge.h:11
#define DEVEN_IGD
Definition: host_bridge.h:10
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition: early_init.c:25
const struct southbridge_usb_port mainboard_usb_ports[]
Definition: early_init.c:8
void mainboard_early_init(void)
Definition: early_init.c:13
static void hybrid_graphics_init(void)
Definition: early_init.c:10
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition: raminit.c:138
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
uint32_t u32
Definition: stdint.h:51