coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
device/pci_ops.h
>
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#include <
northbridge/intel/sandybridge/raminit_native.h
>
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#include <
southbridge/intel/bd82x6x/pch.h
>
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#include <
drivers/lenovo/hybrid_graphics/hybrid_graphics.h
>
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#include <
northbridge/intel/sandybridge/sandybridge.h
>
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#include <
device/device.h
>
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static
void
hybrid_graphics_init
(
void
)
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{
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bool
peg, igd;
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u32
reg32;
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early_hybrid_graphics
(&igd, &peg);
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if
(peg && igd)
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return
;
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/* Hide disabled devices */
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reg32 =
pci_read_config32
(
PCI_DEV
(0, 0, 0),
DEVEN
);
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reg32 &= ~(
DEVEN_PEG10
|
DEVEN_IGD
);
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if
(peg)
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reg32 |=
DEVEN_PEG10
;
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if
(igd)
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reg32 |=
DEVEN_IGD
;
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else
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/* Disable IGD VGA decode, no GTT or GFX stolen */
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pci_write_config16
(
PCI_DEV
(0, 0, 0),
GGC
, 2);
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pci_write_config32
(
PCI_DEV
(0, 0, 0),
DEVEN
, reg32);
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}
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// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13
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const
struct
southbridge_usb_port
mainboard_usb_ports
[] = {
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{ 1, 1, 0 },
/* P0: system port 4, OC0 */
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{ 1, 1, 1 },
/* P1: system port 2 (EHCI debug), OC 1 */
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{ 1, 1, -1 },
/* P2: HALF MINICARD (WLAN) no oc */
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{ 1, 0, -1 },
/* P3: WWAN, no OC */
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{ 1, 0, -1 },
/* P4: smartcard, no OC */
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{ 1, 1, -1 },
/* P5: ExpressCard, no OC */
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{ 0, 0, -1 },
/* P6: empty */
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{ 0, 0, -1 },
/* P7: empty */
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{ 1, 1, 4 },
/* P8: system port 3, OC4*/
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{ 1, 1, 5 },
/* P9: system port 1 (EHCI debug), OC 5 */
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{ 1, 0, -1 },
/* P10: fingerprint reader, no OC */
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{ 1, 0, -1 },
/* P11: bluetooth, no OC. */
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{ 1, 1, -1 },
/* P12: docking, no OC */
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{ 1, 1, -1 },
/* P13: camera (LCD), no OC */
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};
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void
mainboard_get_spd
(
spd_raw_data
*spd,
bool
id_only)
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{
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read_spd
(&spd[0], 0x50, id_only);
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read_spd
(&spd[2], 0x51, id_only);
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}
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void
mainboard_early_init
(
int
s3resume)
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{
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hybrid_graphics_init
();
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}
GGC
#define GGC
Definition:
host_bridge.h:9
DEVEN
#define DEVEN
Definition:
host_bridge.h:16
hybrid_graphics.h
early_hybrid_graphics
void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
Definition:
romstage.c:17
device.h
spd_raw_data
u8 spd_raw_data[256]
Definition:
ddr3.h:156
pci_ops.h
pci_write_config32
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition:
pci_ops.h:76
pci_read_config32
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition:
pci_ops.h:58
pci_write_config16
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
Definition:
pci_ops.h:70
DEVEN_PEG10
#define DEVEN_PEG10
Definition:
host_bridge.h:11
DEVEN_IGD
#define DEVEN_IGD
Definition:
host_bridge.h:10
mainboard_get_spd
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition:
early_init.c:25
mainboard_usb_ports
const struct southbridge_usb_port mainboard_usb_ports[]
Definition:
early_init.c:8
mainboard_early_init
void mainboard_early_init(void)
Definition:
early_init.c:13
hybrid_graphics_init
static void hybrid_graphics_init(void)
Definition:
early_init.c:10
read_spd
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition:
raminit.c:138
PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN)
Definition:
pci_type.h:14
raminit_native.h
sandybridge.h
pch.h
u32
uint32_t u32
Definition:
stdint.h:51
southbridge_usb_port
Definition:
pch.h:56
src
mainboard
lenovo
t420
early_init.c
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