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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include "memmap.h"
#include <types.h>
#include "registers/host_bridge.h"
#include <northbridge/intel/common/fixed_bars.h>
#include "registers/mchbar.h"
#include "registers/epbar.h"
#include "registers/dmibar.h"
#include <device/device.h>
Go to the source code of this file.
Macros | |
#define | BASE_REV_SNB 0x00 |
#define | BASE_REV_IVB 0x50 |
#define | BASE_REV_MASK 0x50 |
#define | HOST_BRIDGE PCI_DEV(0, 0, 0) |
#define | AFE_PWRON 0xc24 /* PEG Analog Front-End Power-On */ |
#define | MSAC 0x62 /* Multi Size Aperture Control */ |
Enumerations | |
enum | platform_type { PLATFORM_MOBILE = 0 , PLATFORM_DESKTOP_SERVER } |
Functions | |
bool | is_sandybridge (void) |
void | intel_sandybridge_finalize_smm (void) |
void | systemagent_early_init (void) |
void | sandybridge_init_iommu (void) |
void | sandybridge_late_initialization (void) |
void | northbridge_romstage_finalize (void) |
void | early_init_dmi (void) |
void | mainboard_early_init (int s3resume) |
int | mainboard_should_reset_usb (int s3resume) |
void | perform_raminit (int s3resume) |
void | report_memory_config (void) |
enum platform_type | get_platform_type (void) |
unsigned long | northbridge_write_acpi_tables (const struct device *device, unsigned long start, struct acpi_rsdp *rsdp) |
#define AFE_PWRON 0xc24 /* PEG Analog Front-End Power-On */ |
Definition at line 30 of file sandybridge.h.
#define BASE_REV_IVB 0x50 |
Definition at line 8 of file sandybridge.h.
#define BASE_REV_MASK 0x50 |
Definition at line 9 of file sandybridge.h.
#define BASE_REV_SNB 0x00 |
Definition at line 7 of file sandybridge.h.
#define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Definition at line 24 of file sandybridge.h.
#define MSAC 0x62 /* Multi Size Aperture Control */ |
Definition at line 34 of file sandybridge.h.
enum platform_type |
Enumerator | |
---|---|
PLATFORM_MOBILE | |
PLATFORM_DESKTOP_SERVER |
Definition at line 18 of file sandybridge.h.
Definition at line 171 of file early_dmi.c.
References BIOS_DEBUG, dmi_recipe(), dmibar_clrsetbits32(), dmibar_read16(), dmibar_setbits8, dmibar_write32(), DMILCAP, DMILCTL, DMILSTS, DMIPVCCAP1, DMIVC0RCTL, DMIVC0RSTS, DMIVC1RCTL, DMIVC1RSTS, DMIVCMRCTL, DMIVCMRSTS, DMIVCPRCTL, DMIVCPRSTS, early_pch_init_native_dmi_post(), early_pch_init_native_dmi_pre(), printk, TXTRN, VC0NP, VC1NP, VCMNP, and VCPNP.
Referenced by init_dram_ddr3().
enum platform_type get_platform_type | ( | void | ) |
Definition at line 1 of file common.c.
References BIOS_WARNING, get_platform_id(), PLATFORM_DESKTOP_SERVER, PLATFORM_MOBILE, and printk.
Referenced by enable_clock_gating(), northbridge_fill_pei_data(), and systemagent_early_init().
Definition at line 6 of file finalize.c.
References BDSM, BGSM, CRDTLCK, DMIVCLIM, DPR, GGC, HDAUDRID, HOST_BRIDGE, MC_LOCK, mchbar_setbits32, mchbar_write8(), MELCK, MESEG_MASK, PAVP_MSG, PAVPC, pci_or_config16(), pci_or_config32(), REMAPBASE, REMAPLIMIT, REQLIM, SAPMCTL, TOLUD, TOM, TOUUD, TSEGMB, UMAGFXCTL, VDMBDFBARKVM, VDMBDFBARPAVP, and VTDTRKLCK.
Referenced by southbridge_finalize_all().
Definition at line 25 of file northbridge.c.
References BASE_REV_MASK, BASE_REV_SNB, PCI_DEVICE_ID, pci_read_config16(), and pcidev_on_root().
Referenced by add_fixed_resources(), gma_pm_init_post_vbios(), gma_pm_init_pre_vbios(), northbridge_dmi_init(), and northbridge_init().
void mainboard_early_init | ( | int | s3resume | ) |
Definition at line 27 of file romstage.c.
References BIOS_DEBUG, BIOS_SPEW, DEVEN, DEVEN_PEG10, early_ec_init(), get_uint_option(), GGC, google_chromeec_kbbacklight(), HOST_BRIDGE, hybrid_graphics_init(), outb(), pci_and_config32(), PCI_DEV, pci_read_config32(), pci_write_config16(), pci_write_config32(), pmh7_dgpu_power_enable(), pmh7_dgpu_power_state(), printk, sch5545_ec_hwm_early_init(), sch5545_emi_get_int_mask_high(), sch5545_emi_init(), sch5545_get_ec_fw_version(), SCH5545_RR_SMI_EN, SCH5545_RR_SMI_STS, SCH5545_RUNTIME_REG_BASE, SCH5545_SMI_GLOBAL_STS, and sch5545_update_ec_firmware().
Referenced by mainboard_romstage_entry(), platform_romstage_main(), and verstage_mainboard_init().
int mainboard_should_reset_usb | ( | int | s3resume | ) |
Definition at line 53 of file early_init.c.
References BIOS_DEBUG, cmos_read(), CMOS_USB_RESET_DISABLE, cmos_write(), printk, and USB_RESET_DISABLE_MAGIC.
Referenced by perform_raminit().
Definition at line 195 of file early_init.c.
References mchbar_write16(), and SSKPD_HI.
Referenced by mainboard_romstage_entry().
void perform_raminit | ( | int | s3resume | ) |
Definition at line 342 of file raminit.c.
References addr, spd_info::addresses, ARRAY_SIZE, BIOS_CRIT, BIOS_DEBUG, BIOS_ERR, pei_data::boot_mode, cbmem_recovery(), CONFIG, config_of_soc, copy_spd(), cpu_get_cpuid(), DCACHE_RAM_MRC_VAR_BASE, DEFAULT_GPIOBASE, DEFAULT_PMBASE, devicetree_fill_pei_data(), die(), pei_data::dimm_channel0_disabled, pei_data::dimm_channel1_disabled, disable_p2p(), northbridge_intel_haswell_config::dq_pins_interleaved, northbridge_intel_haswell_config::ec_present, pei_usb2_port_setting::enable, pei_usb3_port_setting::enable, usb2_port_config::enable, usb3_port_config::enable, enable_usb_bar(), device::enabled, get_pch_platform_type(), hexdump(), HPET_BASE_ADDRESS, init_dram_ddr3(), intel_early_me_status(), pei_usb2_port_setting::length, usb2_port_config::length, pei_usb2_port_setting::location, usb2_port_config::location, mainboard_fill_pei_data(), mainboard_should_reset_usb(), mainboard_usb2_ports, mainboard_usb3_ports, make_channel_disabled_mask(), map_to_pei_oc_pin(), map_to_pei_usb2_location(), mb_get_spd_map(), memcmp(), memcpy(), memset(), northbridge_fill_pei_data(), usb2_port_config::oc_pin, usb3_port_config::oc_pin, pei_usb2_port_setting::over_current_pin, pei_usb3_port_setting::over_current_pin, pcidev_on_root(), PEI_USB_OC_PIN_SKIP, PEI_USB_PORT_SKIP, PEI_VERSION, pei_data::pei_version, mrc_var_data::pool_base, mrc_var_data::pool_used, post_code, printk, save_mrc_data(), sdram_initialize(), setup_sdram_meminfo(), southbridge_fill_pei_data(), pei_data::spd_addresses, pei_data::spd_data, SPD_MEMORY_DOWN, system_reset(), timestamp_add_now(), TS_INITRAM_END, TS_INITRAM_START, pei_data::tx_byte, mrc_var_data::tx_byte, pei_data::usb2_ports, pei_data::usb3_ports, and northbridge_intel_haswell_config::usb_xhci_on_resume.
Referenced by mainboard_romstage_entry().
Definition at line 19 of file raminit_shared.c.
References ARRAY_SIZE, BIOS_DEBUG, ecc_decoder, MAD_CHNL, MAD_DIMM_CH0, MAD_DIMM_CH1, MC_BIOS_DATA, MC_BIOS_REQ, mchbar_read32(), ON_OFF, and printk.
Definition at line 151 of file early_init.c.